JP3568265B2 - Semiconductor memory device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor memory device, and more particularly, to a redundancy system of a multi-bit line batch switching system.
[0002]
[Prior art]
2. Description of the Related Art In recent years, the storage capacity of semiconductor memory devices has been increasing, and the number of cells constituting a memory has become enormous.
For this reason, a defect occurs in a part of the cell, and the probability that the memory becomes defective is increasing.
[0003]
Therefore, conventionally, a redundant memory cell portion is provided separately from a normal memory cell portion (hereinafter, referred to as a real cell portion), and when a defective portion exists in the real cell portion, the defective portion is replaced with the redundant memory cell portion. A method is employed in which the yield of the real cell portion is improved by replacing the memory cell with a predetermined memory cell.
FIG. 4 is a block diagram illustrating the structure of one configuration example of a conventional semiconductor memory device.
[0004]
In other words, you Itewa the conventional semiconductor memory device 1, for example, an address buffer 2, row decoder 3, a column decoder 4, the real cell unit 5, the redundant cell portion 6, a sense amplifier unit 7, the real cell unit 5 or the redundant cell unit switch array 8, the output buffer 9 which are connected to the sense amplifier unit 7 for connecting your stomach selected bit line pair to 6 in the sense amplifier portion 7, a redundant cell addresses corresponding to your Keru defective cell to the real cell unit redundant cell address storage means 10 storing, and what is a comparator circuit 11 for comparing the redundant cell addresses stored in the address information and the redundant cell address storage means 10 are inputted from the address buffer 2 a is, specifically, the address information input from the address buffer 2 comprises a contact Keru defective cell real cell unit 5 In the case of the of, comparing the redundant cell addresses stored in the redundancy cell address storage means 10 in the comparison circuit 11, since both the address data will correspond, the output of the comparator circuit 11, as appropriate Of the switch array 8 for driving the bit line pair of the real cell unit 5 corresponding to the address including the defective cell, is disabled via the column decoder, based on the redundant cell address information, including a redundant cell corresponding to the address including the cell, the switching means switches the column 8 corresponding to the redundant cell address, by the driving state is redundant cells that can be selected.
[0005]
Contact Itewa the conventional redundant cell usage according, for the address of one of the defective cells real cell unit 5, in which the contact Keru redundant cell addresses in the redundancy cell section 6 are in one-to-one correspondence, the redundant cell portion and the number of redundant cells is limited, in the case that requires a large number of redundant cells, at the same time it is necessary to increase the area of the redundant cell portion 6, you Keru storage medium in the redundant unit storage means, for example, ROM Therefore, it is necessary to increase the capacity, and the control circuit is inevitably increased accordingly.
[0006]
According view of the conventional problems, a plurality of redundancy bit line pairs constituting the redundancy cell section 6 collects some predetermined number constitutes one single unit, consists of the same number of redundancy bit line pair according A so-called multi-bit line batch switching method has been proposed in which a plurality of units are assembled and a redundancy process is performed for each unit.
Multibit lines collectively switching method your Itewa according, since the selection switching of each unit redundant cells for each as described above, with may simplify the control circuit, although it is possible to shorten the processing time, in FIG. 5 as shown, the four redundancy bit line pair and the first constituting one unit as a group by have you the multibit lines collectively switching method which the second unit is present, the address data sequentially sequentially output from the address buffer 2 address information of the defective cells included in information, if output is divided individually into the first unit and the second unit is no problem, ie upon 5, defective cells address, there is no problem if occurring in ○ mark or triangle, as shown in the × mark in FIG. 5, there is address information of one of the defective cell, included in the first unit, Address information of the next defective cell But if it is intended to be included in the second unit, that is, have you the multibit lines collectively switching method for processing collectively four redundancy bit line pair, a defect over two redundant units, defective cell If such a system exists, it is impossible for one system to execute the above-described redundancy processing, and it is necessary to provide a processing control circuit for individually driving the first and second units. It has been difficult to realize a simplified circuit configuration or a higher processing speed.
[0007]
The applicant of the present invention has proposed a specific example of a method for improving the efficiency of the redundancy processing in Japanese Patent Application Laid-Open No. 6-203594. In such a method, the number of redundant addresses is smaller than the number of redundant systems. It has a storage ROM and allows the redundant system to have selectivity, thereby enabling the use of redundant systems as many as the number of redundant address storage ROMs. It has the problem of.
[0008]
[Problems to be solved by the invention]
An object of the present invention is to improve the above-mentioned disadvantages of the prior art, and to reduce the number of processing systems without complicating a redundant cell selection control circuit in a conventional semiconductor memory device and without increasing the number of ROMs. An object of the present invention is to provide a semiconductor memory device capable of executing redundancy processing by one system even when a defect such as a defective cell exists across two units without increasing.
[0009]
[Means for Solving the Problems]
The present invention employs the following technical configuration to achieve the above object.
That is, an address buffer, a row decoder, a column decoder, a real cell section, a redundant cell section, a sense amplifier section, a switch column for connecting a bit line pair selected in the real cell section or the redundant cell section to the sense amplifier section, An output buffer connected to the sense amplifier unit, a redundant cell address storage unit for storing a redundant cell address corresponding to a defective cell in the real cell unit, and an input address and stored in the redundant cell address storage unit. In a semiconductor memory device comprising a switch array control means configured to compare each address with each other and selectively operate each switch means in the switch row, the redundant cell unit includes a plurality of redundant cell units. A plurality of redundant bit line pair groups each having one bit line pair as one unit are arranged, and a switching operation is executed for each unit. And a combination of a plurality of redundant bit lines (real cell units) constituting each unit can be arbitrarily changed. Semiconductor memory device.
[0010]
[Action]
Since the semiconductor memory device according to the present invention has the above-described technical configuration, a combination of a predetermined number of redundant bit line pairs forming one unit is determined based on information stored in the redundant unit storage means. Is temporarily changed, and some of the redundant bit line pairs of the predetermined number of redundant bit line pairs forming one unit are rearranged with some of the redundant bit line pairs belonging to another adjacent unit. With this configuration, an operation of switching a specific defective cell of the real cell unit 5 existing over two redundant units to a corresponding redundant cell by one system of redundant processing becomes possible.
[0011]
【Example】
Hereinafter, a specific example of the semiconductor memory device 1 according to the present invention will be described in detail with reference to the drawings.
That is, FIG. 1 is a block diagram showing an example of the configuration of a semiconductor memory device 1 according to the present invention. In the figure, an address buffer 2, a row decoder 3, a column decoder 4, a real cell unit 5, a redundant cell unit 6, A sense amplifier unit 7, a switch array 8 for connecting a bit line pair selected in the real cell unit 5 or the redundant cell unit 6 to the sense amplifier unit 7, an output buffer 9 connected to the sense amplifier unit 7, The redundant cell address storage means 10 storing the redundant cell address corresponding to the defective cell in the real cell section, and comparing the input address with the address stored in the redundant cell address storage means, A switch array control means 20 configured to selectively activate each switch means in the semiconductor memory device. The long cell unit 6 employs a multiple bit line batch switching method in which a plurality of redundant bit line pairs each including a plurality of bit line pairs as one unit are arranged and a switching operation is performed for each unit. And the switch array control means 20 is configured to be able to arbitrarily change a combination of a plurality of redundant bit lines constituting each unit. The memory device 1 is shown.
[0012]
Then, the switch column control unit 20 Keru Contact in a semiconductor memory device 1 according to the present invention, further, a redundant unit memory means 21, based on the output information from said redundant unit storage unit 21 and the redundant cell address storage means 10 Te, comparison means for comparing the redundant cell address switching means 22 for switching redundant cell address, and the address information output from the output and the address buffer 2 in the redundant cell address switching means 22 (i.e., the comparator circuit of FIG. 1 23 ) is provided.
[0013]
That is, in the semiconductor memory device 1 according to the present invention, in the redundant cell section, a plurality of redundant bit line pair groups each including a plurality of bit line pairs as one unit are arranged and switched for each unit. The multi-bit line batch switching system in which the operation is executed is adopted. In the multi-bit line batch switching system composed of a combination of a plurality of bit line pairs, the defect of the real cell portion is adjacently redundant. If the number of redundant bit lines is within the predetermined number of redundant bit lines, the redundant bit line unit is configured as a new unit and redundant processing is performed by one system. The processing is performed so as to change a predetermined combination of bit lines on the redundant side so as to be changed.
[0014]
Specifically, as shown in FIG. 5, have you the multibit lines collectively switching method, when making up a unit for each pair of four redundant bit line, is first outputted from the address buffer 2 When the redundant cell address JADD4 is included in the first unit and the subsequently output redundant cell address JADD5 is included in the second unit, conventionally, the first unit and the second unit are used. Although a required two systems were it means performing separate redundancy processing for each, you Itewa the present invention, and the redundant cell addresses JADD4 and JADD5 is a redundant bit line pair number constituting the units 4 because it contains the redundancy bit line pair within the, since it is possible to construct a new unit, as shown in FIG. 5, new from the redundant cell addresses JADD3 by four redundancy bit line pairs JADD6 Unit Recreate 1, it is possible to perform similar to the conventional redundant treated since it is that to perform a redundant process with a new unit S1 1 system of a control system according.
[0015]
The present invention your information, the related processing, the output state and the respective redundant cell addresses of the redundant cell address of the address data output from the address buffer 2, or constantly to determine included in any unit, the the combination of the side of the bit line redundancy is included in each unit, in which so as to perform a redundant process change and appropriately at any time.
[0016]
That is, in the above-described redundancy processing according to the present invention, the process of changing the combination of a plurality of redundant bit lines constituting each unit is, in other words, the plurality of bit lines constituting each unit. Of a plurality of redundant bit lines in each unit so that a part of a redundant bit line in the unit includes a part of a plurality of redundant bit lines in an adjacent unit. In other words, a combination of a plurality of redundant bit lines constituting each unit is replaced by a redundant combination in each adjacent unit. The combination of bit lines on the redundant side is changed so that the bit line on the other side is shifted so as to be included in one new unit.
[0017]
Therefore, in the redundant address processing by the multi-bit line batch switching method according to the present invention, the combination of a predetermined number of redundant bit lines constituting each unit is not fixed, but is redundant. Each time the process is executed, the unit may be changed. In the end, each unit is composed of a first combination of a plurality of predetermined bit lines on the redundant side and the first combination. Either a part of the bit line on the redundant side in the combination or a second combination composed of a part of the bit line on the redundant side forming another unit adjacent to the unit Is configured to be selectively employed.
[0018]
If explaining the method of operating the semiconductor memory device 1 according to the present invention in more detail, as shown in FIG. 3, the conventional your information, the redundant cell address storage means 10, for example, the side of the bit to be redundant Address data consisting of three bits, that is, A2, A3, and A4, is output as an address for specifying a line, and is compared with output data of an address buffer. If the data match, the address corresponds to the address of the redundant cell unit. were configured to select the bit line of the redundant is the side, but you Itewa the present invention, the redundant cell address storage means 10, in addition to the above 3 bits, the predetermined in which the redundant address data belongs is intended to output the data in a form that adds data representing the units, for example, by adding, for example, 2 bits A0, A1 as shown in FIG. 3 so as to output Than it is.
[0019]
On the other hand, the redundant unit memory means 21 disposed in the switch array controller 20 which is provided have you in the semiconductor memory device 1 according to the present invention described above, can contact by storing the data of the unit, the address at the same time if it contains redundant cell addresses in the output from the buffer 2 is had contact to the redundant cell address switching means 22 to check the actual redundant cell address location the redundant cell address storage unit 10, the redundant and have you in the unit storage unit 21, the redundancy the redundancy cell address, determines whether or not contained in the same unit, if it is determined to belong to different units from each other, which is supplied to the comparator circuit by switching to the redundant address data needed to address data, in which so as to perform a redundant process 1 sequence.
[0020]
That is, the redundant unit memory means 21 constituting the redundant unit storage element with respect to the redundant cell address storage means 10 has stored a conventional redundant cell address provided by the redundant unit memory means 21 according to the defect two redundant units Determine if it is straddling.
And if in the case where a defect is present straddling the two redundant units, in accordance with the logic of the output of the redundant unit storage unit 21 inverts the redundant address data output from the redundant cell address storage means 10 Te by Switch to the address data of another unit, it is possible to remedy the defect which extends over the two redundant units in a redundant processing circuit of a series.
[0021]
More specifically, the redundant address information outputted from the address buffer 2, is configured to output an address including information specifying redundant units, the redundant cell address storage means 10, the said redundant address information among them, along with configured to store the redundant address information except the information that specifies the redundant units, the redundancy unit memory means 21 is provided for storing information that specifies the redundant units, further wherein the address buffer 2. A redundant cell address switching means 22 connected to the redundant cell address storage means 10 and the redundant unit storage means 21 for switching redundant cell addresses based on the output of the redundant unit storage means 21 is included. The comparing means (that is, the comparing circuit 23 in FIG. 1 ) outputs the output of the redundant cell address switching means 22 and the address buffer. Are those configured to compare the output from the file.
[0022]
Next, a specific example the configuration of the redundant cell address switching means 22 that is used to contact Keru semiconductor memory device 1 of the present invention, a specific procedure in our Keru redundant addressing the present invention with reference to FIG. 2 described I do.
FIG. 2 is a block diagram showing an example of the configuration of the redundant cell address switching means 22 according to the present invention. The input unit is provided for each bit of the redundant cell address storage means 10 and each data of A2, A3 and A4. Input terminals 221 to 223 for individually inputting the outputs of the redundant cell address storage elements 101 to 103 storing the data, an input terminal 225 for inputting the output of the redundant unit storage means 21, and the output of the address buffer 2. An input terminal 224 is provided.
[0023]
In this specific example, an example is shown in which the output of the redundant unit storage means 22 is controlled only by one bit A1.
On the other hand, the output of the redundant cell address switching means 22 outputs the outputs A2 ', A3', A4 'corresponding to each bit, A2, A3, A4 of the redundant cell address storage means 10 to the comparison circuit 23. Output terminals 226 to 228 to be connected.
[0024]
Further, inside the redundant cell address switching means 22 , switching circuits K1 to K3 provided corresponding to each bit, A2, A3, A4 of the redundant cell address storage means 10 are provided. Each of K1 to K3 is provided with a NOR gate circuit NOR, first and second inverters INV1 and INV2, and a pair of transfer gate circuits TRG as shown.
[0025]
Further, the output of the address buffer 2 and the inverted output of the redundant cell address storage means 10 are input to the NOR gate circuits NOR1 to NOR3 of the switching circuits K1 to K3, respectively. The output of the first inverter INV1 of the switching circuit K1 is input to the circuit NOR2, and the NOR gate circuit NOR3 of the switching circuit K3 receives the output of the switching circuit K1 and the first inverter INV1 of the switching circuit K2. The output of the inverter INV2 is configured to be input.
[0026]
Now, a description will be given of a redundant address processing method based on the 4-bit line batch switching method using the redundant cell address switching means 22. If the real cell unit 5 has a defect such as a defective cell, the redundant cell unit 6 of performs the replacement with a corresponding redundant cell, the one to the column decoder regarding defective bit address have been, may be stored in the redundant cell address storage means 10 1 to the address data other than 2 bits to specify the units described above, and address data outputted from the address buffer 2, in the case where the redundant address data stored in said redundant cell address storage means 10 matches actuates the switch array controller, to the real cell unit 5 The switch means for supplying data is turned off, and the switch means for supplying data to the redundant cell unit 6 is turned on. Processing is carried out as.
[0027]
In this case, since the above-described redundancy processing is performed in units of 4-bit lines, if the defective cell exists across the units in units of 4-bit lines, processing by one system using the conventional method is performed. Is not possible.
Therefore, our Itewa the present invention has a redundant unit storage unit 21 and the redundant cell address switching means 22 is provided as described above, in the redundancy unit storage unit 21, judging from the redundant address data, the determining whether a defective cell is contained in a predetermined same unit, redundant cell addresses you correspond to defective cells occur in the continuous, Tsu extend over two mutually adjacent different units If it is determined that there Te is the data, for example the lower address to view your Keru unit to the address selecting said column decoder activates the said redundant cell address switching means 22, the redundant cell addresses By switching the redundant address data in the storage means 10 and sending it out to the comparison circuit 23, the redundancy processing can be performed by one system.
[0028]
That is, a specific example of the present invention will be described with reference to FIGS. 2 and 3. Now, the addresses (A0, A1, A2, A3, A4) of two consecutively generated defective cells are (11110). In the case where the data exists over the first unit and the second unit as (00001), the redundant cell address storage means 10 stores the first data of the address data (A2, A3, A4) in the redundant cell address storage means 10. there (110) can be stored, in said redundant unit storage unit 21 is the first data, for example, the address data A1 (1) Contact Ku by storing.
[0029]
Then, have you the address data output from the address buffer 2, in the case the value of the address data A1 is 1 (A1 = 1), the address data of the redundant cell address storage unit 10 (A2, A3 , A4) = (110) is output to the comparison circuit 23 as it is, and when the value of the address data A1 is 0 (A1 = 0), the address data of the redundant cell address storage means 10 is converted to (A2, A3). , A4) = (001), and outputs the result to the comparison circuit 23. By such processing, the combination of the bit lines on the redundant side constituting the unit is changed. redundancy processing defective cell existing straddling redundant units, it will thus be performed in one sequence process.
[0030]
【The invention's effect】
Since the semiconductor memory device according to the present invention has the above-described technical configuration, it is possible to increase the number of ROMs without complicating the redundant cell selection control circuit in the conventional semiconductor memory device. And a semiconductor memory device capable of executing redundancy processing by one system even when a defect such as a defective cell exists across two units without increasing the number of processing systems. Is what you do.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a specific example of a semiconductor memory device according to the present invention.
Figure 2 is a block diagram showing an example of the configuration of a redundant cell address switching means used to your Keru semiconductor memory device of the present invention.
Figure 3 is a diagram showing an example of a combination of a side of the bit line redundancy constitutes your Keru units present invention.
Figure 4 is a block diagram showing a configuration example of our Keru semiconductor memory device in the prior art.
FIG. 5 is a diagram for explaining a problem of redundant address processing by a multi-bit line batch switching method;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device 2 ... Address buffer 3 ... Row decoder 4 ... Column decoder 5 ... Real cell part 6 ... Redundant cell part 7 ... Sense amplifier part 8 ... Switch column 9 ... Output buffer 10 ... Redundant cell address storage means 11, 23 ... Comparison circuit 20 switch row control means 21 redundant unit storage means 22 redundant cell address switching means

Claims (3)

Address buffer, a row decoder, column decoder, real cell unit, redundant cell unit, a sense amplifier section, the real cell unit also properly switch array for connecting the redundant cell unit to your stomach selected bit line pair to the sense amplifier unit, said sense amplifier connected to the output buffer in the unit, the real cell unit to your Keru redundant cell address storage means for storing a redundant cell address corresponding to the defective cell, and stored as an address input to the redundant cell address storage means comparing the redundant cell addresses, Oite a semiconductor memory device having a switch array controller that will be configured to selectively actuate the contact Keru switch means to each of said switch array,
The redundant cell section includes a plurality of redundant bit line pairs each having a plurality of bit line pairs as one unit, and a plurality of redundant bit line pairs arranged such that a switching operation is performed for each unit. Switching control is executed,
The address buffer is configured to output an address including information designating a redundant unit to redundant address information output from the address buffer,
The redundant cell address storage means is configured to store the redundant address information of the redundant address information excluding information specifying the redundant unit,
The switch array control means is connected to the redundancy unit storage means for storing information designating the redundancy unit, the address buffer, the redundancy cell address storage means and the redundancy unit storage means, A redundant cell address switching means for switching the redundant cell address based on output information from the redundant cell address storage means; and a comparison for comparing an output of the redundant cell address switching means with an output from the address buffer. the semiconductor memory device characterized by comprising a means. A portion of each of the respective unit a plurality of redundancy bit line pairs constituting the, to include a portion of the plurality of redundancy bit line pair Contact Keru to adjacent the unit, Keru Contact to the respective unit the the semiconductor memory device according to claim 1, wherein the combination of the redundancy bit line pair of a plurality of are configured to be changed. Each unit is adjacent to a first combination composed of a plurality of predetermined redundant bit line pairs or a part of the redundant bit line pair in the first combination. the semiconductor according to claim 1, characterized in that it is configured so as to selectively adopt one of the other units part of a redundant bit line pairs constituting the the consisting of the second combination of Memory device.

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