JP3568791B2 - Sampling clock recovery circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an apparatus for reproducing a transmitted signal by multiplexing an encoded signal such as audio with data by converting an analog image signal into a digital signal, thereby stabilizing a sampling clock synchronized with a sampling clock on a transmission side. The present invention relates to a sampling clock recovery circuit that recovers data with high accuracy.
[0002]
[Prior art]
A synchronizing circuit or device that transmits a sampling frequency on the transmission side as frequency information and reproduces the information on the reception side is disclosed in, for example, "Sampling Frequency Synchronization Device" in Japanese Patent Application Laid-Open No. 54-51305.
[0003]
In this prior art, the number of sampling clocks in a cycle obtained by dividing the transmission line clock by a 1 / N divider is counted by a counter, and the frequency information ΔS is sent to a receiving device.
[0004]
On the other hand, the receiving apparatus counts the number of reproduced sampling clocks in a cycle obtained by dividing the reproduced transmission path clock by a 1 / N cycle, and obtains the frequency information ΔR.
[0005]
The difference between these two pieces of frequency information 両 S and △ R (△ S- △ R) is integrated by an integrator and converted into an analog signal by a D / A converter to control a VCO that generates a sampling clock. In this way, the sampling clock of the receiving device is the same as the sampling clock of the transmitting device.
[0006]
In this conventional device, the frequencies can be the same. However, the jitter of the sampling clock is not defined. That is, jitter of a frequency higher than the cycle of transmitting the frequency information can be suppressed, but jitter of a lower frequency occurs. When multiple stages are connected, jitter is accumulated and becomes large.
[0007]
As a means for solving this problem, Japanese Patent Application Laid-Open No. 6-338880 proposes a "sampled clock recovery method".
In this reproduction method, the difference signal of the frequency information is obtained not by 1 / N of the transmission line clock but by 1 / MN which is further divided to 1 / M (M is an integer of 1 or more). Control is performed so that the difference becomes zero. When the value of the difference signal is large, M is set to 1 or a small value in the next cycle, and when the difference signal is small, the value of M is set to a large value. Container.
[0008]
In this reproduction method, in order to reduce the frequency jitter, a program frequency divider that further divides the frequency information generation cycle by an arbitrary frequency division ratio is used. The frequency information △ R on the receiving side is integrated to obtain ΣS and ΣR, and the reproduction sampling frequency is controlled using the difference value Σ = ΣS−ΣR. As a result, when the frequency difference between the color subcarriers (subcarriers) of the input video signal is small, Σ is stabilized at a small value, so that the reproduction frequency is controlled in a long cycle, and the cycle in which jitter occurs is extended. Can be
[0009]
[Problems to be solved by the invention]
In the above-mentioned conventional reproducing method, when the dividing ratio M is increased, the control cycle (1 / NM) becomes longer, and the jitter below the frequency becomes smaller, but the jitter in the control cycle remains. Was. When the frequency division ratio M is increased, the characteristic of the low-pass filter (LPF) after D / A conversion has a period (1 / N) when M = 1, so that the value of M is Even if the period becomes longer due to the increase, the characteristic of the LPF is fixed and does not change, so that there is a drawback that jitter whose frequency changes locally also occurs. In addition, since the control is performed every 1 / M, if the frequency fluctuates suddenly at the beginning of the 1 / M cycle, the difference is calculated at the end of the cycle, and the control is performed. It takes a long time until the operation is performed, and there is a disadvantage that the frequency response is deteriorated. There is a disadvantage that it is difficult to obtain a true correction value because the frequency control is feedback-controlled with an analog value as the voltage of the VCO.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to provide a sampling clock recovery circuit that suppresses low-frequency jitter generated by transmission of a recovered sampling clock and improves tracking characteristics.
[0011]
It is another object of the present invention to provide a sampling clock reproducing circuit which can reduce the occurrence of jitter of a color burst constituting a reproduced video signal and have good tracking performance even when a transmitting / receiving apparatus is connected in multiple stages. It is in.
[0012]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, a sampling clock recovery circuit according to the present invention has the following characteristic configuration.
[0013]
(1) A sampling clock regeneration circuit for regenerating a sampling clock from frequency information from the transmission side and regenerating a reception sampling clock used for sampling on the reception side, wherein the sampling frequency information from the transmission side and the obtains the difference signal of the sampling frequency information of the receiving side to correct the angular velocity of the angular velocity generating circuit based on the said difference signal to generate a receiver-side sampling clock based on the corrected angular velocity, generated sampled A sampling clock recovery circuit forming a feedback loop for generating the sampling frequency information on the receiving side based on a clock.
[0014]
(2) The sampling clock reproducing circuit according to (1), wherein the angular velocity of the angular velocity generating circuit is corrected by integrating the angular velocity for each cycle of the transmission line clock to obtain a phase angle.
[0015]
(3) means for separating frequency information △ S and a clock from the transmission data on the transmission side, means for counting the frequency of the sampling clock on the reception side to obtain reception frequency information △ R, Means for obtaining a corrected angular velocity ΔW from the differential signal of ΔR to obtain a corrected angular velocity.
[0016]
(4) The method according to (1), (2) or (3), wherein the phase angle is divided into an upper digit and a lower digit of the angular velocity, and the angular velocity separately obtained is added to obtain a phase angle of the sampling clock. Sampling clock recovery circuit.
[0017]
(5) The sampling clock according to (1), (2), (3) or (4), further comprising an adaptive correction circuit for adaptively correcting angular velocity based on the transmission frequency information, the difference signal, and the angular velocity. Regeneration circuit.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of a sampling clock recovery circuit according to the present invention will be described in detail with reference to the drawings.
[0019]
FIG. 1 is a block diagram of a preferred embodiment of a sampling clock recovery circuit according to the present invention. FIGS. 2 and 3 are detailed block diagrams of main blocks in FIG.
[0020]
First, the configuration of a receiving apparatus including a sampling clock recovery circuit according to the present invention will be described with reference to FIG. This receiving apparatus includes a sampling clock recovery circuit 10, a digital / analog (D / A) converter 11, a separation circuit 12, a demodulator (DEM) 13, and a 1 / N divider (1 / N) 19. Transmission data is input to the DEM 13, and a signal is output from the D / A converter 11. The sampling clock recovery circuit 10 includes a counter 14, a subtraction circuit (-) 15, an angular velocity generation circuit 16, a phase angle generation circuit 17, and a clock generator 18.
[0021]
When receiving the transmission data via the DEM 13, the receiver extracts a transmission line clock from the transmission data, and separates the encoded video data and the transmission frequency information ΔS from the transmission line frame by the separation circuit 12 based on the clock. I do. The transmission frequency information ΔS is supplied to the subtraction circuit 15 of the sampling clock recovery circuit 10.
[0022]
The transmission line clock frequency f1 is frequency-divided by the frequency divider 19 into 1 / N. At this cycle φN, the counter 14 generates reception frequency information △ R from the reception sampling clock fr. The subtraction circuit 15 obtains a difference signal (△ = △ S− △ R) obtained by subtracting the reception frequency information △ R from the transmission frequency information △ S. When the difference signal △ is 0, the transmission sampling clock frequency fs and the reception sampling clock frequency fr match.
[0023]
The angular velocity generating circuit 16 obtains the angular velocity W = 360 degrees × fr / fl of the reception sampling clock frequency fr rotating at the time of the transmission line clock cycle every time the difference signal △ is given. This value is the angular velocity corrected by the value of the difference signal △. This correction is performed by feedback control so that the difference signal に な る becomes zero. The magnitude △ W of the angular velocity corrected by the difference signal に 対 し て with respect to the current angular velocity is 360 degrees × △ / N.
[0024]
On the other hand, the phase angle generation circuit 17 accumulates and integrates the angular velocity for each integration clock of the transmission line clock frequency, and obtains the phase angle θ of the sampling clock rotating at the angular velocity W. When the phase angle is corrected by ΔW, the correction value is multiplied by N after the next cycle of φN, so that the phase angle is additionally rotated by 360 degrees × △ / N × N. That is, the number of sampling clocks increases by △. If the transmission frequency information △ S is constant during this period, the difference signal △ can be set to 0 after the next cycle of φN. When the difference signal 収束 converges to 0, fs = fr. The clock generator 18 generates a PCM sine wave from the phase angle θ, converts it into an analog signal, and performs reception sampling (sampling).
Generates a clock fr.
[0025]
The D / A converter 11 obtains a PCM video signal from the video coded data separated by the separation circuit 12, performs D / A conversion, and outputs an analog video signal.
[0026]
Here, if the counting cycle is determined and the variation range of the sampling clock frequency is determined, the variation range of the frequency information is also determined. Even if it is sent to the receiving side, it can be determined at the receiving side, so that the number of transmitted bits can be reduced.
[0027]
For example, the transmission line clock is frequency-divided into 1 / 19,440 to obtain an 8K clock, which is further frequency-divided into 1/458. That is, N = 19,440 × 458 = 8,903,520 (87DB60h in hexadecimal). The cycle φN when the transmission path clock is divided by N is 57.25 ms, which is the count cycle (frequency fn) of the sampling frequency. If 14.31818 MHz, which is four times the color subcarrier of the input television signal, is used as the sampling clock, the count value for each count cycle is a value near fr × φ = 819,716. If the color subcarrier frequency variation of the television signal is in the range of ± 100 ppm, the number of clocks will vary by ± 82. 8 bits can represent 256 sections. That is, even if only the lower 8 bits are transmitted, the fluctuation frequency range is ± 82, so that the receiving side can determine the frequency information.
[0028]
Next, FIG. 2 shows a detailed block diagram of an example of the angular velocity generating circuit 16 and the phase angle generating circuit 17 of FIG. The angular velocity generation circuit 16 includes a correction circuit 21, an addition circuit 22, and a register 23. On the other hand, the phase angle generation circuit 17 includes an addition circuit 24 and a register 25.
[0029]
When the angular velocity is represented by a binary number, the required number of effective bits depends on the length of the period φN, in other words, the magnitude of N. Further, since the truncation error is multiplied by N, in order to make the error accumulated by N times negligible, for example, 1% or less, a number of bits that can represent a value of 100 × N is required. In the case of N = 8903520 (87DB60h in hexadecimal), about 30 bits are required.
[0030]
In the case of the transmission line clock and the sampling frequency described above, the central angular velocity W0 = 360 degrees × fs / fl = 33.1439935 degrees. The value when 360 degrees is normalized to 1.0 is 0.092066486. Assuming that the effective bits after the decimal point are a 32-bit hexadecimal number (h), 1.0 is 1.0000000000h and 0.092066486 is 0.1791AB53h. When initialized at power-on, this value is set in the register 23 as the angular velocity.
[0031]
The correction circuit 21 obtains a correction angular velocity △ W from the difference signal △. When the difference signal 差分 = 1, the correction angle is △ W = 360 degrees × △ / N = 360 degrees / 8903520 = 0.000040433 degrees (0.00001E2h in normalized hexadecimal notation). W = 0.000040443 degrees × △. The obtained corrected angular velocity △ W is supplied to the addition circuit 22 and is cumulatively added to the current angular velocity W supplied from the register 23 to obtain the corrected angular velocity W in the output of the addition circuit 23. It converges to a value of angular velocity W = 360 degrees × fs / fl.
[0032]
The corrected angular velocity W is supplied to a phase angle generation circuit 17 and is integrated by an integrator composed of a register 24 and an adder circuit 25 to integrate the angular velocity W for each cycle of the transmission line clock to generate a signal of the phase angle θ. obtain. The phase angle is subjected to a modulo operation at 360 degrees.
[0033]
Next, FIG. 3 shows a detailed block diagram of an example of the clock generator 18 of FIG. The clock generator 18 includes a sine wave generator 31, a D / A converter 32, and a rectangular wave circuit 33. The sine wave generator 31 generates a PCM sine wave from the input phase angle θ. This sine wave generator 31 can be converted by a ROM (read only memory). When a phase angle is input from the ROM, a PCM sine wave signal is output. If the number of effective bits of the phase angle is about the upper 8 bits, the magnitude of the error can be 0.4% or less. This is converted into an analog sine wave by the D / A converter 32, and the sine wave is amplitude-amplified and amplitude-clipped by the rectangular wave circuit 33 to be shaped into a rectangular wave to generate a reception sampling clock fr. .
[0034]
Next, another embodiment of the sampling clock recovery circuit of the present invention will be described with reference to FIGS. Components similar to those in FIGS. 1 to 3 are denoted by the same reference numerals.
[0035]
FIG. 4 is a block diagram showing a schematic configuration thereof. This receiving device includes a sampling clock recovery circuit 10a, a D / A converter 11a, a separation circuit 12a, a demodulator (DEM) 13a, and a 1 / N frequency divider 19a. The sampling clock recovery circuit 10a includes a 1 / K frequency divider 41 in addition to a counter 14a, a subtraction circuit 15a, an angular velocity generation circuit 16a, a phase angle generation circuit 17a, and a clock generator 18a. Contains.
[0036]
When the frequency of the transmission line clock fr is high, a high-speed operation IC (integrated circuit) is required if it is used as the clock for the integration operation of the phase angle generation circuit 17a that calculates the phase angle as it is. In order to avoid this, the 1/4 frequency divider 41 is configured to divide the transmission line clock into 1 / K and output it, and use this as the operation clock fk for integration. When the ISDN hierarchy ST1 is used as a transmission line, the frequency of the transmission line clock is fl = 155.52 MHz, and the sampling clock fs of the input video signal is fs = 14.3818 MHZ. In this case, as the operation clock for reproducing the sampling clock, an integration operation clock fk obtained by dividing the transmission line clock by K = 4 is used as a frequency that is twice or more the sampling clock frequency. Since the frequency is about 38.88 MHz, the phase angle generating circuit 17a and the clock generator 18a can be configured without using a high-speed element.
[0037]
The angular velocity generation circuit 16a generates an angular velocity corresponding to the integration operation clock fk obtained by dividing the transmission line clock, and the phase angle generation circuit 17a and the clock generator 18a are processed by the integration operation clock fk.
[0038]
The angular velocity W when using an integrated clock obtained by dividing the transmission line clock by 1 / K converges to 360 degrees × fs × k / fr. When the integration clock fk decreases and is set to nearly twice the sampling clock, the LPF characteristic of the D / A converter 11a is sharpened, and a tank circuit that resonates at the sampling clock frequency is provided to absorb jitter. With this configuration, the waveform jitter of the D / A output of the clock generator 18a can be reduced.
[0039]
FIG. 5 is a detailed block diagram of an example of the phase angle generation circuit 17a of FIG. The phase angle generation circuit 17a includes a separator 51, addition circuits 52, 54, 56, registers 53, 57, a quadruple circuit 55, and a 1/4 frequency divider 58. If the calculation of the phase angle is performed with the number of digits of the angular velocity W when the integration clock is high, a high-speed integration process is performed to prevent the number of digits from being too large to prevent the integral addition process from being performed within the cycle of the operation clock. Indicates a technique consisting of a small number of digits. The integration operation of the angular velocity W is equivalent to integrating W four times, that is, multiplying W by four, and adding the result of shifting W by 2 bits to the upper end once every four times.
[0040]
The process of integrating the upper value Wu of the angular velocity and the process of integrating the lower Wl are separately performed and added later. The integration of the upper Wu operates by the integration clock, and the integration of the lower Wl integrates the value of 4 × W1 by ｌ of the integration clock. These integration operations are performed by the above-described addition circuits 52 and 56, registers 53 and 57, quadruple circuit 55, and 1/4 frequency divider 58. The phase angle θ is obtained by adding the upper 8 bits of the upper integration value and the lower 8 integration values by the adder 54. The change of the phase angle of the lower digit Wl once every four times is a maximum of 3 for the 8 bits (360 degrees) of the phase angle of the upper digit Wu. The variation of the phase angle is 3/256 = 1.17%, and the influence on the variation of the sampling clock is negligible.
[0041]
The angular velocity W of which the effective digit is 32 bits is separated by the separator 51 into Wu of the upper 8 bits and Wl represented by 32 bits of a digit having a value of 9 bits or less. Therefore, W = Wu + Wl. The upper order of the angular velocity W is supplied to the adding circuit 52, and the higher-order phase angle Wu is integrated for each integration clock, supplied to the register 53, and supplied to the adding circuit 54. The lower angular velocity Wl is supplied to a quadruple (multiplying) circuit 55, and the quadrupled one is supplied to an adding circuit 56, and for each quarter integrated clock supplied from a quarter frequency divider 58. The lower angular velocity Wl is integrated, and a phase angle obtained by integrating the lower angular velocity Wl with the output of the register 57 is obtained. The upper 8 bits are supplied to the adding circuit 54. The output of the adding circuit 54 provides a phase angle θ obtained by adding the upper θu and the lower θl. It should be noted that the distribution of the number of bits and the division ratio of the low-speed integration process and the low-speed integration process are not limited to the above-described example.
[0042]
Next, a block diagram of a detailed configuration of the angular velocity generating circuit 16a of FIG. 4 will be described with reference to FIG. The angular velocity generation circuit 16a includes an adaptive correction circuit 21a, an addition circuit 22a, a register 23a, and a monitoring circuit 61.
[0043]
By adaptively setting the value of the corrected angular velocity, steady jitter can be reduced, and synchronization can be performed in a short time in a state where frequency synchronization is lost.
[0044]
When using a sampling clock synchronized with the color subcarrier of the television signal, the color subcarrier is very stable, and the sampling clock should be stable in a normal state.
[0045]
On the other hand, when the difference signal 4 is given, if the value is used as it is for correction, fluctuations occurring in the transmission system or the like are directly reflected on the sampling clock, so that inconvenience such as occurrence of color distortion occurs. . For this purpose, the rate of change of the angular velocity that fluctuates per unit time according to the state is controlled. Further, the angular velocity W is monitored so as not to exceed the fluctuation range of the angular velocity, and the frequency fluctuation range of the sampling clock is limited.
[0046]
The monitoring circuit 61 monitors the transmission frequency information {S or} for a long time, and supplies a state control signal to the adaptive correction circuit 21a. Further, the current angular velocity W is monitored, and the correction angular velocity ΔW is limited so as to fall within the allowable range of the angular velocity. The adaptive correction circuit 21a does not use the difference signal そ の ま ま as it is in a stable state with little fluctuation. By performing the control for generating the correction angular velocity ΔW by limiting the fluctuation width to a predetermined fluctuation width, it is possible to reduce jitter and long-term fluctuation.
[0047]
On the other hand, if the frequency difference between the sampling clock on the transmitting side and the clock on the receiving side becomes large due to switching or the like, it is necessary to synchronize the receiving side frequency with the transmitting side frequency in a short time. Enlarge. However, the correction angular velocity W is limited so that the variation of the sampling clock is limited so as to fall within the allowable range of the variation of the color subcarrier.
[0048]
In the case of an emergency in which the buffer memory or the like overflows to cause a failure in video reproduction, the correction is performed by outputting an unlimited correction angular velocity. If the corrected angular velocity △ W suddenly fluctuates every counting cycle of fn, a phase jump occurs suddenly and adversely affects the television signal. Therefore, the corrected angular velocity △ W starts from 0 based on the integration clock. Thus, the correction angle is gradually increased so that a predetermined correction angular velocity ΔW is obtained with a time constant. By controlling the timing and the value of the increasing correction angular velocity ΔW, the time constant of the frequency fluctuation of the sampling clock can be freely adjusted. This eliminates the need to switch the time constant of the clock generator 18a.
[0049]
The preferred embodiment of the sampling clock recovery circuit of the present invention has been described above. However, the present invention should not be limited to only such an example, and it is needless to say that various modifications can be made depending on the specific application.
[0050]
【The invention's effect】
As can be understood from the above description, according to the sampling clock recovery circuit of the present invention, the angular velocity of the digital signal is corrected according to the control frequency difference, and the phase angle of the digital sampling clock is obtained. , Accurate frequency feedback control is possible. Furthermore, since the variation of the angular velocity can be adaptively controlled, there is a practically remarkable effect that a sampling clock which can reduce the steady-state jitter and can be locked in a short time can be reproduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of a receiving apparatus including a preferred embodiment of a sampling clock recovery circuit according to the present invention.
FIG. 2 is a detailed block diagram of an angular velocity generation circuit and a phase angle generation circuit of the sampling clock recovery circuit of FIG.
FIG. 3 is a detailed block diagram of a clock generator of the sampling clock recovery circuit of FIG. 1;
FIG. 4 is a block diagram of a receiving apparatus including another embodiment of the sampling clock recovery circuit of the present invention.
5 is a detailed block diagram of a phase angle generation circuit of the sampling clock recovery circuit of FIG.
FIG. 6 is a detailed block diagram of an angular velocity generating circuit of the sampling clock recovery circuit of FIG. 4;
[Explanation of symbols]
10, 10a Sampling clock recovery circuit 16, 16a Angular velocity generation circuit 11, 11a D / A converter 12, 12a Separation circuit 13, 13a Demodulator 21a Adaptive correction circuit

Claims (5)

In a sampling clock recovery circuit that reproduces a sampling clock from the frequency information from the transmission side and reproduces a reception sampling clock used for sampling on the reception side, the sampling frequency information from the transmission side and the reception side obtains the difference signal of the sampling frequency information, and corrects the angular velocity of the angular velocity generating circuit based on the said difference signal to generate a receiver-side sampling clock based on the corrected angular velocity, based the generated sampling clock A sampling clock recovery circuit comprising a feedback loop for generating sampling frequency information on the receiving side . 2. The sampling clock recovery circuit according to claim 1, wherein the correction of the angular speed of the angular speed generation circuit is performed by integrating each cycle of a transmission line clock to obtain a phase angle. Means for separating frequency information △ S and a clock from the transmission data on the transmission side, means for counting the frequency of the sampling clock on the reception side to obtain reception frequency information △ R, 3. The sampling clock recovery circuit according to claim 1, further comprising means for obtaining a corrected angular velocity from the difference signal to obtain a corrected angular velocity. 4. The sample according to claim 1, wherein the phase angle is divided into a high-order digit and a low-order digit of the angular velocity, and the angular velocity separately obtained is added to obtain a phase angle of the sampling clock. Clock recovery circuit. 5. The sampling clock recovery circuit according to claim 1, further comprising an adaptive correction circuit that adaptively corrects an angular velocity based on the transmission frequency information, the difference signal, and the angular velocity.

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