JP3569151B2 - Exchanger and diagnostic method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an exchange, and more particularly to a method for diagnosing an ATM exchange suitable for increasing the capacity.
[0002]
[Prior art]
The conventional technique is described in, for example, "Speech path continuity test cell transmitting apparatus" in Japanese Patent Application Laid-Open No. 10-41945. Hereinafter, this conventional technique will be described. FIG. 10 shows a schematic configuration of a general ATM exchange. In the ATM communication method, communication data is decomposed into small-capacity packets of fixed length, and an ATM cell in which information necessary for exchange transmission such as routing information is added to each packet as a header is exchanged at high speed by hardware. Is the way. In the ATM switch shown in FIG. 10, ATM cells are input to the switch 1 simultaneously and in parallel from a plurality of lines (4-0, 4-1, 4-2,...) From # 0 to #n. The line interface 3 adjusts the processing timing for each line and transmits the data to the core switch 2 using the high-speed data transmission line 6. The core switch 2 performs a switching process based on each cell information, and sends a high-speed data transmission path to the interface 3 of the line (5-0, 5-1, 5-2...) Designated as each switching destination. 7 through. The line interface 3 sends out the ATM cells transmitted from the core switch 2 to each line. Conventionally, a test function unit 12 as shown in FIG. 2 is provided in common for each line in order to diagnose whether the high-speed data transmission lines 6, 7 and the core switch 2 in the exchange can exchange and transmit normally. ing. The test function unit 12 sends a test cell to any specified input line side 6 and fetches a test cell from any specified output line side 7 to perform a comparison judgment.
[0003]
FIG. 3 shows an outline of a test performed by the test function unit 12. In FIG. 3, a setting register 23 is a register file for setting data of a cell to be transmitted as a test cell from the control CPU. Prior to the test, test cell data is set in the setting register 23 from the control CPU 10 in advance. The test cell generation circuit 24 generates a test cell using the data of the setting register 23, and sends out the test cell 20 to an arbitrary specified line on the input side of the core switch. The core switch 2 performs an ATM cell switching process and transfers the cell to the corresponding line. In the line on the output side, the test cell is determined by the test cell determination circuit 25, and the data of the cell is stored in the collection register 26. The cell data stored in the collection register 26 is compared with the value of the setting register 23 by using the comparison circuit 27 or read out by the control CPU 10 to determine whether or not the normal exchange transmission processing has been performed. judge.
[0004]
With such a configuration, conventionally, the continuity test through all the line paths is performed by using the "return" function in each line interface. In FIG. 2, each line interface is shown separately for the input side and the output side of the core switch. However, actually, the line interfaces on the input side and the output side are often mounted on the same board or the same LSI. . Utilizing this, for example, it is instructed to output a cell received from the core switch 2 at the output line interface of the line # 0 from the input line # 0 interface to the line # 1 again. Can be set to "wrap". In this way, the "return" is set so that one cell sequentially passes through all the lines from the line # 0 to the line # 1 and further from the line # 1 to the line # 2. Is used to transmit a test cell from the input side of line #n to line # 0. The transmitted test cell returns from the line # 0 to the line # 1, further to the line # 2, and sequentially returns to the output interface of the line #n through all the lines. The test function unit 12 captures the returned test cells, and compares and determines the contents of the recovered test cells with the test cells transmitted by the function shown in FIG. 3, thereby testing the continuity of all lines and core switches. Can be.
[0005]
[Problems to be solved by the invention]
In the conventional example described above, data previously written in the setting register (register file) 23 from the CPU is used as the contents of the test cell. That is, since the rewriting of these register files is limited by the speed of the CPU, the test is performed using semi-fixed data at the time of the test, and the transmission when various data patterns are dynamically changed is tested. I can't. Every time one test cell is transmitted, it is impossible to rewrite the data with another data due to the writing speed from the CPU. In addition, since the transmission / recovery function of the test cell is shared in one place, there is a limit on the capacity of transmitting / recovering / determining the test cell. Even if the exchange capacity of the exchange itself is several tens of gigabits per second, the capacity of test cells that can be transmitted and recovered is only one-tenth or one-hundredth. In other words, since the test can only be performed in a state where the exchange capacity of the exchange has a margin, it is not possible to detect such an abnormality such as when an intermittent error occurs in the data transmission path or the core switch unit. Have difficulty. Furthermore, even in the continuity test using all the lines using the "return" function at the line interface, the test cells with the same data are reused, so the contents of the test cells transmitted between the lines are the same, Cannot be determined.
[0006]
In order to solve such a problem, there are inventions described in JP-A-4-291856 and JP-A-5-75639. In these conventional examples, the receiving side sets the initial value of the receiving side counter at the first octet of the test cell, and checks the test data by comparing whether or not the data is a continuous value. However, according to these methods, if the initial values are the same, the data of the payload are all the same, and it is not possible to determine a path error. Further, in these examples, since the payload data of the test cell is generated and inspected using the counter, there is a problem that the rate of change of the used data differs depending on the bit position of the payload data. This is because, for example, when an 8-bit counter is used, a pattern from 0 to 255 can be generated, but 0/1 is used alternately for bit 0 which is the least significant bit, and the pattern changes every time. In bit 7, which is the most significant bit, 0 data continues 128 times, then 1 data continues 128 times, and there is only one change of 0/1. In other words, when such counter data is used inside the exchange, despite high-speed data transmission, data that changes only at a very low cycle is used in the bit located at the most significant bit. Therefore, there is a problem that the high-speed transmission test is not performed. In these examples, only the payload is to be tested, and no means is provided for checking for transmission errors in header information.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide an exchange that enables generation, collection, and determination of test cells up to the maximum exchange capacity of the exchange, and a diagnostic method thereof.
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the present invention provides an exchange for performing a cell switching process between a plurality of communication lines, a transmission unit provided for each of the lines and transmitting a test cell for testing the switching process. And a test unit provided for each line, for receiving a test cell transmitted from the transmitting unit and performing a test on the test cell, wherein the transmitting unit includes, for each test cell to be transmitted, random data. As an initial value, data including the initial value and a result of a predetermined operation based on the initial value is output as payload data of a test cell, and the inspection unit outputs the initial value from the received test cell. And the result of the operation are extracted, and it is determined whether the result of the predetermined operation based on the extracted initial value matches the result of the extracted operation. Further, the transmitting unit further outputs a fixed value obtained by a predetermined operation from a value corresponding to the header information of the test cell, the inspection unit, the value corresponding to the header information from the received test cell and The fixed value may be extracted, and it may be further determined from the value corresponding to the extracted header information whether or not the result of the predetermined operation matches the extracted fixed value. The transmission unit may include an arithmetic circuit that performs the predetermined operation, and a holding circuit that holds a result of the operation of the arithmetic circuit. In addition, the inspection unit, the arithmetic circuit that performs the predetermined operation, a holding circuit that holds a result of the operation of the arithmetic circuit, a result of the operation that is held in the holding circuit, and a result of the extracted operation And a comparison circuit that determines whether or not the two match.
[0009]
According to the present invention, a test can be performed using random data for each line or each test cell, and a transmission unit and an inspection unit are provided for each line so that various test cells can be simultaneously and parallelly connected from a plurality of lines. By inputting, only the receiving side can autonomously judge the consistency of the contents of the test cell. In the present invention, since random data (for example, pseudo-random data) is used for the payload, there is no bias in the data change rate depending on the bit position. Further, in order to detect a transmission error in a header portion, the transmitting unit further outputs a fixed value obtained by a predetermined calculation from a value corresponding to the header information of the test cell, and the test unit receives the received test data. A value corresponding to the header information and the fixed value are extracted from the cell, and it is further determined from the value corresponding to the extracted header information whether a result of the predetermined operation matches the extracted fixed value. I do. Thereby, the transmitting side generates a fixed value (signature) based on the header information, stores the unique value (signature) and the random data in the payload and transmits the payload, and one of the receiving sides also generates the fixed value (signature) based on the received header information. By calculating and generating an eigenvalue (signature) using the above method, and comparing the signature value with the expected signature value received in the payload, a transmission error of the header information can be detected.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a first embodiment according to the present invention will be described with reference to the drawings.
[0011]
Conventionally, in order to determine whether a test cell has been normally received through an exchange process, test cell data set on the test cell transmitting side and test cell data collected on the receiving side are compared bit by bit one by one. Had been inspected. In such a determination method, as shown in FIG. 3, it is impossible to mount a circuit block for sending out a test cell and a circuit block for recovering a test cell completely independently from each other, so that the test function unit is not provided. Reference numeral 12 is shared by each line as a common circuit block, not for each line interface. For this reason, the capacity of the test cells that can be generated is limited by the processing capacity of the shared test function unit, and the test can be performed only under the exchange processing condition that is extremely small in comparison with the maximum exchange capacity of the exchange. Furthermore, even in the continuity test in which all the lines were driven, different test cells could not be used for each line.
[0012]
To solve the above problem, a test circuit is implemented for each individual line instead of sharing the test function among all the lines. In the present invention, as shown in FIG. 1, a test cell generation / transmission unit 101 and a test cell reception inspection unit 201 are provided for each line interface. As a result, as shown in FIG. 1, the test cell is transmitted from the line # 0 to the line #n, and at the same time, the test cell is transmitted from the line # 3 to the line # 0 and from the line #n to the line # 1 through a plurality of paths. Can be sent and received. At this time, since the line for transmitting the test cell and the line for receiving the test cell are completely independent, it is impossible to compare and determine the content of the transmitted test cell with the content of the received test cell. Therefore, in the present invention, the data to be put in the payload (communication data portion) of the test cell is generated by a specific arithmetic circuit, so that the payload pattern has a certain rule. As a result, on the line receiving the test cell, the same arithmetic circuit is used to check whether the payload pattern of the received test cell has a certain rule or not. It is possible to determine whether the transmission has been performed normally. In such a payload integrity check that enables the determination on the receiving side alone without referring to the data on the transmitting side, the initial value of the pattern is included in the payload pattern as in the test cell configuration shown in FIG. It is important that a relationship of Pn + 1 = f (Pn) be provided between P0 and a logically continuous pattern, and that the generation and inspection of the pattern be performed using the same arithmetic circuit on both the transmitting side and the receiving side of the test cell. This is a feature of the invention.
[0013]
Hereinafter, detailed embodiments will be described with reference to the drawings.
[0014]
FIG. 5 shows a test cell payload pattern generation circuit, which is used on the test cell generation side. The payload pattern generation circuit shown here mainly has a register 30 composed of a plurality of bits, and an operation circuit f (x) 31 that inputs the value of the register 30 and calculates the next value. The selector 33 is a circuit for controlling updating of the value of the register 30. In accordance with a control signal 36 input as a selection signal, data to be stored in the register 30 is selected from the initial value 34, the arithmetic circuit output 35, or the current value of the register 30 and output. The register 30 takes in and updates the value at the timing of the clock 37. The value 32 output from the register 30 is used as a payload pattern. The value currently stored in the register 30 is assumed to be P0. As the initial value, a different value for each test cell is specified in advance by the control CPU of the exchange. The operation circuit f (x) 31 performs an operation using P0 as an input, and outputs a subsequent value f (P0) = P1. The selector 33 selects the output 35 of the arithmetic circuit f (x) according to the control signal 36. The register 30 takes this in at the timing of the clock 37 and updates the value to P1. Hereinafter, by repeating the same operation, the register 30 outputs a series of patterns P0, P1, P2, P3, and P4 and a series value associated with Pn + 1 = f (Pn) by the function f (x). .
[0015]
FIG. 6 shows the correspondence between the series of patterns P0, P1, P2,... Shown above and the form of the test cell. The test cell is composed of a header portion 21 and a payload portion 22, as in a normal ATM cell. The header 21 contains information required for ATM cell exchange transmission, such as cell identification information, VCI, VPI, and priority. Here, information indicating that the cell is a test cell is included as cell identification information. One payload 22 is a part of the communication data itself. In the conventional method, data preset from the control CPU 10 to the setting register 23 of the exchange is used as the payload data of the test cell. In the present embodiment, a series of pattern sequences P0, P1, P2, P3, P4,... Generated by the arithmetic circuit shown in FIG. FIG. 6 shows an example in which data is simply arranged in the payload in the order of P0, P1, P2, P3,. Arranging data in such a pattern sequence is the simplest, and requires the least amount of hardware to generate and inspect on the receiving side. However, if the logical order of the pattern can be restored and inspected on the receiving side, it is not always necessary to insert the pattern in the payload in the order of the pattern sequence on the transmitting side. For example, the odd-numbered pattern of Pn + 1 and the even-numbered pattern of Pn may be exchanged and transmitted, and these may be exchanged on the receiving side to restore the logical order and then inspected. It is not out of the way.
[0016]
FIG. 7 shows details of a circuit for inspecting a payload pattern on the test cell receiving side. The inspection circuit mainly includes an arithmetic register 40, an arithmetic circuit f (x) 41 for calculating the next value based on the value of the arithmetic register 40, and a cell data (payload data) of the received test cell. And a circuit 27 (shown as a comparator in FIG. 7) for judging the consistency of the cell data taken into the register 49 based on the value 42 output from the arithmetic register 40 and the value of the register 49. The test cell discrimination control circuit 25 controls these components. The test cell determination control circuit 25 checks the header information of the ATM cell transferred from the core switch to the line interface, and determines whether the ATM cell is a test cell or a normal communication cell. When it is detected that this is a test cell, the cell data (payload data) is taken into the payload pattern inspection circuit 200, and the selection control signal 46 to the selector 43 and the comparison control signal 48 to the comparator are controlled. To check the data consistency. FIG. 7 shows how the test cell discrimination control circuit 25 performs control corresponding to each pattern sequence stored in the payload of the test cell, together with the circuit configuration. It is assumed that a series of pattern sequences are sequentially stored in the payload of the test cell by the pattern generation circuit shown in FIG. The test cell determination control circuit 25 instructs both the comparison register 49 and the operation register 40 to take in the initial value P0 of the pattern sequence included in the payload. In this state, the comparison register 49 and the operation register 40 have undefined values until the next clock is input, so that the comparator 27 is instructed to inhibit comparison. When the next clock is input, the initial value P0 is taken into the comparison register 49 and the operation register 40. In this state, the test cell determination control circuit 25 instructs the comparator 27 to perform the comparison. For the next pattern P1, the comparison register 49 is instructed to take in the data, while the operation register 40 is instructed to update to P1 as a result of performing an operation based on the previously taken in P0. . When the next clock is input in this state, the comparison register 49 takes in P1 from the payload of the test cell, and the operation register is updated to the pattern P1 independently calculated based on the previous pattern initial value P0. The comparator 27 compares these values. Here, if there is an error in either or both of P0 and P1 taken in from the test cell, the comparator 27 detects a mismatch. It is assumed that the captured P0 has an error and P1 is normal. In the operation register 40, the operation is performed based on the erroneous P0 and the value is updated, so that the value is updated to P1 different from the normal P1. Since the normal P1 is taken into one comparison register 49, the value does not match the value of the updated operation register 40. Conversely, if P0 is normal and P1 is erroneously input, the operation register 40 updates the value to normal P1 based on the normal P0, whereas the comparison register 49 takes in the wrong P1. , Again, a mismatch occurs and a transmission error is detected. Hereinafter, similarly, the comparison register 49 takes in the next pattern sequentially inputted, and the operation register 40 updates the value by the operation unit f (x) 41, thereby comparing the test pattern with the test cell in the comparator 27. Of the payload data can be determined.
[0017]
In the description so far, the specific bit width of the pattern sequence used for the operation register and the payload of the test cell is not referred to, but simply a plurality of bits. In addition, for simplicity, the description has been made on the assumption that the bit widths of the operation register and the comparison register and the bit width of one pattern forming the pattern sequence are the same. The value of this bit width is merely a matter of design, irrespective of the nature of the invention, but the invention can be implemented even when the bit width of the operation register and the comparison register is different from that of the pattern series. FIG. 8 shows an example of the control operation of the embodiment when the operation register and the comparison register are 24 bits and the payload pattern is received one byte (8 bits) at a time.
[0018]
As shown in FIG. 8, it is assumed that the payload test pattern operation register 30 used on the test cell generating side, the comparison register 49 and the operation register 40 used on the test cell receiving side each have 24 bits. On the other hand, it is assumed that the payload pattern of the test cell is transmitted and received with a width of 1 byte (8 bits). On the test cell generation side shown in FIG. 8, the value of the operation register is divided and transmitted three times, one byte at a time, from the lower side (cycles 1, 2, 3). In cycle 3, the most significant byte (bit 23 to bit 16) is transmitted, and the value of the operation register held so far is instructed to update the value of all bits by the next clock. Again, in cycle 4, transmission is sequentially repeated from the lower 8 bits (bit 7 to bit 0). On the other hand, on the receiving side of the test cell, the comparison register repeats taking in each received byte in order from the lower 8 bits (bit 7 to bit 0) of the register. The receiving-side operation register takes in the first 3 bytes as an initial value and sequentially takes in the lower 8 bits, and thereafter, updates the value by operation once every three cycles. The comparator compares these three new bytes each time they become available in the comparison register and the operation register. According to the above control, the present invention can be applied even if the bit width of the register for generating and checking the pattern sequence does not match the transfer width (in one clock) of the test cell data.
[0019]
FIG. 9 shows an overall configuration of a test cell generation / transmission / reception inspection unit using the payload pattern generation / inspection circuit described above. The test cell generation and transmission unit 101 mainly includes a test mode setting register 55 for setting a test mode from the control CPU 10 and a test cell generation for performing test cell generation and transmission control according to the test mode set here. A control circuit 54, a test information setting register 56 for setting information necessary for generating a test cell header such as a replacement destination of the test cell and test cell identification information from the control CPU 10 in advance, and a payload pattern generation circuit 100 described in FIG. , A selector 52 for switching and outputting between a normal communication ATM cell and a test cell. Depending on the test mode, there may be cases where all normal communication cells are discarded and test cells are forcibly inserted / transmitted.However, in order to test online while the exchange is operating, there is a function to replace only empty cells with test cells. Required. The empty cell detection circuit 53 is a circuit that determines whether the cell 4 input from the line is an empty cell. The delay circuit 51 delays a normal communication cell by the time required for the test cell generation control circuit 54 to start generation of a test cell after the empty cell detection circuit 53 detects an empty cell. This is a circuit for matching the replacement timing.
[0020]
An outline of the operation of generating and transmitting a test cell using the above circuit configuration will be described below. First, the control CPU 10 of the exchange sets, via the control bus 11, information necessary as header information of a test cell to be generated in the test information setting register 56 of the test cell generation / transmission unit 101 in the line interface. . Next, by setting a test mode (how and how to generate and transmit test cells) in the test mode setting register 55, the test cell generation control circuit 54 generates test cells. Instruct to start. The empty cell detection circuit 53 determines whether the cell input from the line is an empty cell, and notifies the test cell generation control circuit 54 if the cell is empty. The test cell generation control circuit 54 starts the generation of the header of the test cell based on the information set in the test information setting register 56, and instructs the selector 52 to switch to the test cell side and output. When the generation of the test cell header is completed, the test cell generation control circuit 54 supplies a control signal to the payload pattern generation circuit 100 to generate a series of pattern sequences having a certain rule. The selector 52 selects and outputs a pattern sequence from the payload pattern generation circuit 100 following the header of the test cell. If the test mode set in the test mode setting register 55 is the continuous transmission, the test cell generation control circuit 54 starts generating the header of the test cell continuously, but only when an empty cell is input, the test cell is generated. When the generation mode is set, the generation of the next test cell is started after waiting for the detection signal from the empty cell detection circuit 53 to come. Here, the replacement destination and the priority of the test cells to be generated and transmitted are generated based on information set in advance in the test information setting register 56, but may be dynamically changed using a counter or the like. . For example, the counter may be incremented every time a test cell is transmitted, and the line number of the test cell replacement destination may be changed sequentially. It is also conceivable that the number of test cells to be generated is set in the test information setting register 56 in advance.
[0021]
One test cell reception inspection unit 201 includes a test mode setting register 61, a test cell discrimination circuit 25-1, a test cell inspection control circuit 25-2, the payload pattern inspection circuit 200 described in FIG. And a holding register 60. The empty cell sending circuit 59 and the selector 58 are circuits for replacing the test cells used for testing the core switch and the line interface inside the exchange with empty cells so that the test cells do not flow outside and output the cells. The delay circuit 57 is a circuit for matching the delay of the empty cell sending circuit 59 with the delay of a normal communication cell so that the cell timing is matched even when switching is performed by the selector 58. Prior to the test, the control CPU 10 of the exchange sets the test mode to be tested in the test mode setting register 61 via the control bus 11 in advance, thereby notifying the test cell test control circuit 25-2 of the start of the test. I do. The test cell inspection control circuit 25-2 waits for a test cell detection signal from the test cell determination circuit 25-1. When the reception of the test cell is detected, the test cell inspection control circuit 25-2 inspects the header and controls the payload pattern inspection circuit 200 to execute the integrity inspection of the payload portion. When an error is detected in the payload by the payload pattern inspection circuit 200, or information during the test, the test result holding register 60 stores and holds the information. The information on the error of the test cell stored here can be read out to the control CPU 10 via the control bus 11. When the contents of the test mode setting register 61 indicate that a test cell is to be changed to an empty cell and output, the test cell inspection control circuit 25-2 outputs an empty cell transmission circuit 59 every time a test cell is detected. And the selector 58 is controlled to output an empty cell instead of the test cell.
[0022]
Next, FIG. 1 shows an exchange to which the test cell generation / transmission unit 101 and the test cell reception / inspection unit 201 are applied. All of the line interfaces include the test cell generation / transmission unit 101 and the test cell reception / inspection unit 201 described with reference to FIG. As described above, the test cell generation / inspection circuit uses a pattern sequence having a certain rule as the payload pattern (including the initial value P0 in the payload, and Pn + 1 = f (Pn) holds for the pattern in the payload. ), So that the inspection of the payload can be performed by the inspection circuit independent of the generation circuit. For this reason, in the present embodiment, as shown in FIG. 1, in parallel with transmitting and testing a test cell from line # 0 to line #n, the test cell is transmitted from line # 3 to line # 0, and also from line #n. It is possible to perform a test on line # 1 simultaneously through a plurality of switching paths. In addition, by using an individual value as a payload initial value in each test path, a test using different payload data for each test path is possible.
[0023]
As described above, in the embodiment described above, the pseudo-random pattern is used as the payload data, so that the rate of change in each bit of the payload of the test cell is not biased. Thereby, it is possible to prevent the change rate from being biased due to the bit position, which is a problem in the payload data generated by using the conventional counter, and to realize a more accurate communication test.
[0024]
Next, in order to further improve the error detection capability of the communication test, a second embodiment that enables a test including header information will be described.
[0025]
FIG. 11 shows the format of a test cell in which an error can be detected, including the header. The feature of this embodiment resides in that a signature value generated based on header information is inserted into a payload. The signature value is a unique value generated based on the information of the cell header. If there is a transmission error in the header information, a mismatch occurs between the signature value generated based on the transmission error and the original signature value, and this can be detected. Further, in the present embodiment, a payload seed value (random data) is inserted into the payload following the header signature. This is because if the test cell header information is the same, the signature value will always be the same, so if the payload data is generated based on it, the test cells with the same pattern of payload data will always be used, and for each test cell This is because one of the objects of the present invention of applying a different payload data pattern cannot be realized. In order to change the data pattern of the payload for each test cell generated, a subsequent payload pattern is generated based on the signature value generated from the header information and the payload seed value as random data.
[0026]
11, the header signature value (HD_SIGN) inserted at the head of the payload is a value generated by using the signature generation circuit shown in FIG. 12 based on the information of the test cell header. The signature generation circuit shown in FIG. 12 is obtained by adding an exclusive OR function by parallel data input to a pseudo random pattern generation circuit based on a shift operation. FIG. 12 shows an example of 8 bits, and the signature generation circuit has eight flip-flops and 11 two-input exclusive ORs. There is an 8-bit parallel data input (D7 to D0) as header information, and a pseudo random number is generated by the current value and D input of each flip-flop Q. By using such a circuit, by inputting each byte of the test cell header sequentially from the head, a unique value based on the header information is generated. This is the header signature value, and in the present embodiment, this value is inserted at the head of the payload of the test cell. The receiving side receiving the test cell generates a header signature in the same manner based on the header information, and compares this value with the expected value of the header signature received at the beginning of the payload, thereby obtaining the header information of the received test cell. Can be determined whether or not there is an error. Further, a pattern of a subsequent payload can be generated from the value of the header signature and the received seed value, and an error of the payload can be tested. The method of generating the payload pattern below P2 in FIG. 11 is the same as the method already described with reference to FIG. However, here, P1 shown in FIG. 11 (P1 is a value obtained by executing the operation 2 from the header header signature and the seed value) is used instead of P0 described as the initial value in FIG. become. Alternatively, the payload seed value may be used as an initial value in place of P0 described as the initial value in FIG. In this case, without calculating P1, the payload seed value is set as an initial value and the subsequent payload data is obtained.
[0027]
FIG. 13 shows an example of a test cell payload pattern generation circuit that can cope with error detection of header information. This shows details of the payload pattern generation circuit 100 shown in FIG. Since the payload according to the present embodiment includes a header signature generated based on the header data, the test cell header data 20 is input to the payload pattern generation circuit. The header signature is generated using the main register 30-1 and the arithmetic circuit 62 of the present circuit. The operation circuit 62 has two operation modes (operation 1 and operation 2) as shown in FIG. 13, and one of the modes is selected by the operation control signal FUNC. The operation 1 is used for generating a random pattern using the main register 30-1 alone, and corresponds to f (x) in FIG. On the other hand, the operation 2 is performed by using two inputs of the main register 30-1 and the input test cell header data 20, and is used for generating a header signature by realizing the operation shown in FIG. The auxiliary register 30-2 holds and outputs a payload seed value that is random data. When the generation of the payload data of one test cell is completed, the value generated by the last main register is fetched and the next test is performed. The cell is held until it is generated, output as a new payload seed, and used for subsequent payload pattern generation. Therefore, the payload seed value is random data. The selection control signals 1, 2, 3, the operation control signal, and the LOAD / HOLD signal are instructed from the control CPU 10 shown in FIG. 1 via the control bus, or the test cell generation control circuit 54 shown in FIG. Instructed by
[0028]
In order to generate the payload data of the test cell using this circuit, first, it is necessary to input the header data used in the test cell and obtain the header signature. In the example shown here, the case where the main / complementary registers and the arithmetic units are all 8 bits wide is taken as an example. As shown in FIG. 13, the header signature takes the first byte of the test cell header into the main register 30-1 and thereafter performs “operation 2” one after another with the bytes of the test cell header. Therefore, the selector 2 (33-2) selects the input B only at the time of the header first byte, and thereafter selects the input A. As a result, only the header first byte is taken into the main register as it is, and thereafter, the operation result is taken. The operation is performed while inputting each header byte, and the value of the main register 30-1 when the operation result with the last byte of the header is taken into the main register 30-1 is the header signature value. Subsequently, a payload pattern is generated and output. First, the selector 3 (33-3) outputs the value of the main register 30-1 as it is by selecting the B input. As a result, as shown in FIG. 13, the first byte of the payload pattern 32 indicates the header signature. At this time, a HOLD control signal is given to the main register 30-1, and the value is continuously held. Next, the selector 3 (33-3) selects the input A and outputs the random data held in the auxiliary register 30-2. Thus, the second byte of the payload represents the payload seed value. At the same time, the selector 1 (33-1) selects the output of the auxiliary register 30-2 instead of the header data input, and in the arithmetic circuit 62, selects the main register 30-1 holding the header signature value with the payload seed. A signature operation (operation 2) is performed with the complementary register 30-2 holding the value, P1 is obtained, and an initial value of the payload random data is generated. The main register 30-1 is supplied with a LOAD control signal. With the next clock input, the main register takes in the previous operation result. At the same time, the selector 3 selects the input B again and outputs the value fetched by the main register. Thereafter, the arithmetic circuit generates a pseudo-random pattern as the remaining payload data using the value of the main register so as to select "operation 1" as the operation control signal FUNC. The capture register is supplied with a LOAD control signal at the time of outputting the last byte of the payload, and holds it as a payload seed used in the next test cell generation.
[0029]
As described above, by the above-described functional operation, it is possible to generate a test cell that can be inspected not only for the payload but also for the transmission error of the header data.
[0030]
In the following, a description will be given of means for performing a test on the test cell receiving side.
[0031]
FIG. 14 shows the internal configuration of the payload pattern inspection circuit. This circuit is obtained by adding a header inspection function to the payload pattern inspection circuit 200 shown in FIGS. 7 and 9. Although there is no significant difference in the hardware configuration from the circuit shown in FIG. 7, the function of the arithmetic unit 62 shown in FIG. 14 is such that two types of operations, “operation 1” and “operation 2”, as shown in FIG. It is possible. This computing unit 62 has the same computing function as that shown in FIG. Each control signal in FIG. 14 is provided from the test cell determination control circuit 25 shown in FIG. When the test cell discrimination control circuit 25 discriminates the test cell, it inputs the cell data 44 to the payload pattern inspection circuit shown in FIG. 14, selects the B input in the selector 46, and takes the first byte of the test cell header into the register 40. Let Thereafter, between the value of the register 40 and the subsequent cell header byte, the arithmetic circuit 62 is used to perform the "arithmetic operation 2" and sequentially load the register 40. When the final byte of the header is input and the operation result is fetched into the register 40, the register 40 holds the header signature generated from the header data of the received test cell. Since the expected value of the header signature is stored at the head of the subsequently input payload, the header signature is compared with the expected value while holding the value of the register 40. Here, if the comparison results match, there is no transmission error in the received header information of the test cell. Conversely, if the value of the header signature does not match the expected value, it can be determined that either the header data or the expected signature value has an error. Next, since the payload seed value of the test cell is input, “operation 2” is performed with the previously generated header signature to generate an initial value of the payload random data. Thereafter, the arithmetic circuit 62 performs “operation 1”, sequentially updates the value of the register 40, and makes the comparator 27 compare and determine the remaining payload pattern.
[0032]
As described above, if the second embodiment shown in FIGS. 12, 13 and 14 is used, it is possible to inspect errors in payload data including transmission errors in header data of test cells.
[0033]
【The invention's effect】
As described above, according to the present invention, it is possible to perform a test of an exchange using different data for each line or each test cell. Further, by inputting various test cells from a plurality of lines simultaneously and in parallel, it becomes possible to generate, collect, and determine test cells having a capacity up to the maximum exchange capacity of the exchange.
[Brief description of the drawings]
FIG. 1 is a diagram showing the configuration of an ATM switch to which the present invention is applied and the form of a test cell used in the present invention.
FIG. 2 is a configuration diagram showing the positioning of a diagnostic circuit in a conventional ATM exchange.
FIG. 3 is a diagram showing a hardware configuration for realizing a conventional diagnostic method for an ATM exchange.
FIG. 4 is a diagram showing different test cell transmission modes in a plurality of exchange paths, which is one of the objects of the present invention.
FIG. 5 is a configuration diagram of a payload pattern generation circuit according to the embodiment of the present invention.
FIG. 6 is a diagram showing a data format constituting a test cell according to the embodiment of the present invention.
FIG. 7 is a configuration diagram of a payload pattern inspection circuit according to the embodiment of the present invention.
FIG. 8 is a diagram showing a correspondence relationship between register bits and payload bytes related to generation and inspection of a payload pattern of a test cell according to the present invention.
FIG. 9 is a hardware configuration diagram for realizing a test cell generation / inspection function according to the embodiment of the present invention.
FIG. 10 is a configuration diagram of a general ATM exchange.
FIG. 11 is an explanatory diagram showing a test cell format capable of detecting a header error.
FIG. 12 is an explanatory diagram showing a configuration of a signature generating circuit for parallel data.
FIG. 13 is an explanatory diagram showing a configuration and operation of a test cell payload pattern generation circuit corresponding to header error detection.
FIG. 14 is an explanatory diagram showing a configuration and operation of a payload pattern inspection circuit corresponding to header error detection.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 ATM switch 2 Core switch 3 Line interface 4 Line input 5 Line output 6 High-speed data transmission path 7 High-speed data transmission path 10 Control CPU 11 Control bus , 20 ... test cell, 21 ... header, 22 ... payload, 23 ... setting register, 24 ... test cell generating circuit, 25 ... test cell discriminating circuit, 26 ... collection register, 27 ... comparing circuit, 30 ... operation register, 31 ... Arithmetic circuit, 32 arithmetic register output, 33 selector, 40 arithmetic register, 41 arithmetic circuit, 42 arithmetic register output, 43 selector, 49 comparison register, 51 delay circuit, 52 selector 53: empty cell detection circuit, 54: test cell generation control circuit, 55: test mode setting register (generation side), 56: test information setting register, 57: delay circuit, 58: selection 59, empty cell transmission circuit, 60, test result holding register, 61, test mode setting register (reception side), 100, payload pattern generation circuit, 101, test cell generation transmission unit, 200, payload pattern inspection circuit, 201 Test cell reception inspection unit.

Claims (4)

In an exchange for exchanging cells between a plurality of communication lines,
A transmission unit that is provided for each line and transmits a test cell for testing the switching process.
An inspection unit provided for each line, receiving a test cell transmitted from the transmission unit, and inspecting the test cell,
The transmission unit has one transmission unit operation circuit,
For each test cell to be transmitted,
A fixed value calculated by a predetermined first operation performed using the transmission unit operation circuit from the header information of the test cell, an initial value that is random data, and the transmission unit based on the fixed value and the initial value. A data including a payload pattern generated according to a second predetermined operation performed by using an arithmetic circuit is output as payload data of the test cell,
The inspection unit has one inspection unit operation circuit having the same operation function as the transmission unit operation circuit,
The header information, the fixed value, the initial value, and the payload pattern are extracted from the received test cell, and the result calculated by the first calculation performed using the inspection unit calculation circuit from the extracted header information. And whether or not the extracted fixed value matches, and according to the first and second calculations performed using the inspection unit calculation circuit from the result calculated by the first calculation and the extracted initial value. An exchange for generating a second payload pattern and determining whether or not the generated second payload pattern matches the extracted payload pattern . The exchange according to claim 1,
The transmitting unit includes:
A test cell generation control circuit for generating a test cell;
It further comprises an empty cell detection circuit that determines whether or not the cell input from the communication line is an empty cell, and when the cell is empty, instructs the test cell generation control circuit to start generation of a test cell.
The exchange characterized by the above . The exchange according to claim 1 or 2 ,
The transmitting unit includes:
Further comprising a holding circuit for holding a calculation result by the transmission unit calculation circuit,
The transmission unit operation circuit,
According to the instruction of the operation control signal, the first operation and the second operation, respectively,
The first operation is performed using the header information and the value held in the holding circuit as inputs,
The exchange, wherein the second operation is performed by using a value held in the holding circuit as an input . The exchange according to claim 1 , 2 or 3 ,
The inspection unit,
A holding circuit for holding a result of the operation in the operation unit operation circuit,
A comparison circuit that determines whether the result of the operation held in the holding circuit matches the extracted fixed value or the extracted payload pattern,
The inspection unit arithmetic circuit,
Follow the instructions on the operation control signal, and said first operation and said second operation, have each row,
The first operation is performed using the header information and the value held in the holding circuit as inputs,
The exchange, wherein the second operation is performed by using a value held in the holding circuit as an input .

Images