JP3570661B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device.
[0002]
[Prior art]
The HEMT is required to have a short gate length in order to increase the cutoff frequency and reduce the noise figure. However, simply shortening the gate length increases the gate resistance and degrades the device characteristics. In order to avoid this problem, a low-resistance gate electrode in which only a portion of the gate electrode in contact with the channel is shortened and a low-resistance portion is provided above the gate electrode is used. Such a gate electrode has a T-shaped cross section and is therefore called a T gate or a mushroom gate.
[0003]
To fabricate a T-gate, first, a low-sensitivity, high-sensitivity, medium-level electron beam resist is sequentially laminated on a substrate as a lower layer, a middle layer, and an upper layer resist. By developing, the lower resist in contact with the substrate is formed with a small line width that defines the gate length, and the middle resist is formed with a large line width pattern. The upper resist is a pattern having a smaller line width than that of the middle resist, but is formed with a large line width suitable for forming a low-resistance portion provided above the gate electrode. In general, a method of forming an undercut resist pattern that is advantageous for lift-off with the upper layer resist and finally depositing a metal to be a gate electrode and performing a lift-off is common. IEDM Tech.Dig., P613-616 (1983)).
[0004]
Japanese Patent Application Laid-Open No. 02-275958 discloses a method of forming a low-resistance portion above a gate electrode and shortening a gate length by forming only a two-stage development process in a step of forming a three-layer resist. Proposed. Japanese Patent Application Laid-Open No. 06-168870 discloses that two layers of resist are laminated to form an insoluble layer on an upper resist so that an overhang shape is formed to define a low-resistance layer portion of a T-gate and a gate length. There has been proposed a method of shortening the time.
[0005]
[Problems to be solved by the invention]
However, the above-described conventional method has a problem that controllability and stability of each opening cannot be sufficiently secured. For example, in the method disclosed in Japanese Patent Application Laid-Open No. 02-275958, the primary purpose is to define the aperture of the lower layer resist as the beam diameter of the electron beam. There is almost no sensitivity contrast between the upper and middle resists that define the low resistance layer portion. Therefore, there is a problem that the controllability of the dimensions of the low resistance layer portion and the controllability of the overhang shape are not sufficient.
[0006]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device in which the opening dimensions of three layers of resist can be precisely controlled and the opening dimensions of each layer can be controlled independently.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, a first positive electron beam resist, a second positive electron beam resist, and a third positive electron beam resist are sequentially formed on a semiconductor substrate. a first step of laminating, after the first step, a first region of the electron beam resist consisting of three layers and a second step of exposing using an electron beam, after the second step, the first A third step of exposing a second area smaller than the first area using an electron beam in the area of the first step, and after the third step , developing the first area of the third electron beam resist a fourth step of forming a first opening and, after the fourth step, a fifth step of forming a second opening by developing the second electron beam resist, the fifth after the step, a sixth step of the first electron beam resist is developed to the second region to form a third opening, after the sixth step, A seventh step of forming a recess groove in the semiconductor substrate through the three openings, an eighth step of depositing a metal wiring layer for a gate electrode over the entire surface of the semiconductor substrate after the seventh step , After the step, a ninth step of removing the first and second electron beam resists and unnecessary metal wiring layers thereon by a lift-off method while leaving the metal wiring layers deposited in the recess grooves among the metal wiring layers . And a process.
[0008]
According to a second aspect of the present invention, in the method for manufacturing a semiconductor device according to the first aspect, a third resist having higher sensitivity than the first resist is used, and It is characterized by using a resist having a higher resolution than the three resists.
[0009]
According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, an organic developer is used for developing the first and third electron beam resists, and an organic developer is used for developing the second electron beam resist. Is characterized by using an alkali developing solution.
[0010]
According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, a highly soluble developer is used for developing the third electron beam resist, and the first electron beam resist is used for developing the first electron beam resist. Is characterized by using a developer having low solubility.
[0011]
According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to fourth aspects, the first and third electron beam resists include alpha-methylstyrene and alpha-chloroform. It is characterized by using a copolymer resist of acrylic acid and using polymethylglutarimide as the second electron beam resist.
[0012]
According to a sixth aspect of the present invention, in the method for manufacturing a semiconductor device according to the first aspect, one end of the second region is exposed to the first region when the three-layer electron beam resist is exposed to the electron beam. The exposure is performed so as to coincide with one of the ends.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A to 1D and 2E to 2H are views showing an example of steps of a method for manufacturing a semiconductor device according to the present invention. In this process example, a first positive electron beam resist 4, a second positive electron beam resist 5, and a third positive electron beam resist 6 are sequentially laminated on the semiconductor substrate 21 (FIG. 1). (A)) exposing the first regions of the three-layer electron beam resists 4, 5, and 6 using an electron beam 7 (FIG. 1 (b)); Exposing a second area smaller than one area by using an electron beam 8 (FIG. 1B), developing the first area with respect to a third electron beam resist 6 to form a first opening A step of forming the portion 9 (FIG. 1C), and a step of developing the second region of the second electron beam resist 5 to form the second opening 10 (FIG. 1D). Developing the second region of the first electron beam resist 4 to form a third opening 11 (FIG. 2E); Forming a recess groove 12 in the semiconductor substrate 21 through the openings 9, 10, 11 of the semiconductor substrate 21 (FIG. 2F), and depositing metal wiring layers 13, 14 for the gate electrode over the entire surface of the semiconductor substrate 21. (FIG. 2 (g)), the first and second resists 4, 5 and unnecessary metal wiring layers thereon are left except for the metal wiring layers 13 deposited in the recess grooves among the metal wiring layers 13, 14. 14 by a lift-off method (FIG. 2H).
[0014]
Here, the third resist 6 has a higher sensitivity than the first resist 4, and the first resist 4 has a higher resolution than the third resist 6.
[0015]
More specifically, a copolymer resist of alpha methyl styrene and alpha chloroacrylic acid is used for the first and third resists 4 and 6, and polymethyl glutarimide is used for the second resist 5. Can be
[0016]
In the developing step, an organic developer is used for developing the first and third resists 4 and 6, and an alkali developing solution is used for developing the second resist 5. A highly soluble developer is used for developing the third resist 6, and a low soluble developer is used for developing the first resist 4.
[0017]
In the exposure area, in the step of performing two exposures of the electron beam to the first area and the second area, the second area having a large exposure amount is placed at an arbitrary position in the first area having a small exposure amount. An area can be drawn (exposure drawing).
[0018]
In particular, the exposure can be performed such that one end of the second region with a large amount of exposure coincides with one end of the first region with a small amount of exposure.
[0019]
As described above, in the present invention, the first regions of the three-layered electron beam resists 4, 5, and 6 are exposed using the electron beam 7, and the first regions are narrower than the first regions. The second region is exposed using an electron beam 8, the first region is developed for a third electron beam resist 6 to form a first opening 9, and the second opening 5 is formed for the second electron beam resist 5. The second region is developed to form a second opening 10, the second region is developed for the first electron beam resist 4 to form a third opening 11, and the three openings 9 are formed. , 10, and 11, a recess groove 12 is formed in the semiconductor substrate 21, and metal wiring layers 13 and 14 for a gate electrode are deposited on the entire surface of the semiconductor substrate 21. Among the metal wiring layers 13 and 14, a recess groove 12 is deposited. The first and second resists 4 and 5 and the Since removing the unnecessary metal wiring layer 14 by a lift-off method, it is precisely controlled resist opening dimension of three layers, and can be independently controlled opening size of each layer. As a result, an opening having a desired shape can be easily formed in the three-layer resist, and a gate electrode having a desired shape can be formed. Thus, the controllability of the size of the low-resistance layer portion of the semiconductor device and the control of the overhang shape It is possible to remarkably enhance the performance. In particular, when used in the process of forming a low-resistance gate electrode of a HEMT, the controllability of the size of the low-resistance layer portion and the controllability of the overhang shape can be improved, and a gate electrode having a desired shape can be manufactured. it can.
[0020]
Further, by aligning one end of the second region with a large amount of exposure with one end of the first region with a small amount of exposure, the gate electrode in contact with the semiconductor substrate can be brought closer to the source electrode. In addition, the parasitic resistance between the gate and the source can be reduced, and the noise characteristics of the semiconductor device can be improved.
[0021]
【Example】
Example 1
3 (a) to 3 (d) and 4 (e) to 4 (h) are views showing the steps of Embodiment 1 of the method for manufacturing a semiconductor device of the present invention. In the first embodiment, in two exposures of the electron beam, one end of the second region having a large amount of exposure is not matched with one end of the first region having a small amount of exposure. Exposure was performed.
[0022]
Specifically, in the first embodiment, a HEMT in which a GaAs layer serving as a channel layer, an AlGaAs layer serving as a secondary electron supply layer, and a high-concentration GaAs layer 3 serving as source / drain ohmic contact layers are sequentially formed. A high-resolution electron beam resist 4, for example, ZEP520-12 (manufactured by Zeon Corporation) is applied on the substrate 21 to a film thickness of about 2000 °, and baked at a temperature of 200 ° C. for 30 minutes in a nitrogen atmosphere. Next, PMGI SF8 (manufactured by MCC) is applied as an electron beam resist 5 to a film thickness of about 4600 ° and baked at a temperature of 200 ° C. for 30 minutes in a nitrogen atmosphere. Next, as a highly sensitive electron beam resist 6, for example, ZEP7000B (manufactured by Zeon Corporation) is applied to a film thickness of about 2000 ° and baked at a temperature of 200 ° C. for 30 minutes in a nitrogen atmosphere. In this way, as shown in FIG. 3A, three layers of electron beam resists 4, 5, and 6 are sequentially laminated on the HEMT substrate 21.
[0023]
Next, as shown in FIG. 3B, an electron beam pattern is drawn on the three layers of resists 4, 5, and 6 on the substrate 21 using an electron beam drawing apparatus. As shown in FIG. 3B, the electron beam pattern to be drawn is such that a wide 0.8 μm pattern 7 corresponding to the first region and a narrow 0.1 μm pattern 8 corresponding to the second region overlap. To The drawing conditions are as follows: an acceleration voltage of 20 kV, an irradiation current value of 0.1 nA, and a beam diameter of 0.025 μm. A wide pattern has a line irradiation amount of 100 nC / cm, and a narrow pattern has a line irradiation amount of 200 nC / cm. Draw with conditions.
[0024]
Next, as shown in FIG. 3 (c), the upper resist 6 is developed at room temperature for 2 minutes using ZED500 (manufactured by Nippon Zeon), which is a highly soluble organic developer, and then isopropyl alcohol is used. The first opening 9 is formed by rinsing at room temperature for 1 minute. Next, as shown in FIG. 3D, development of the resist 5 in the middle layer is performed at room temperature for 45 seconds using NMDW (manufactured by Tokyo Ohka), which is an alkali developer, and a pure and rinsing treatment is performed for 1 minute at room temperature. Then, a second opening 10 is formed. Next, as shown in FIG. 4E, the lower resist 4 is developed with a low solubility organic developer ZED50N (manufactured by Zeon Corporation) at room temperature for 3 minutes, and further with isopropyl alcohol at room temperature for 1 minute. Is performed to form a third opening 11.
[0025]
Thereafter, as shown in FIG. 4F, etching for recess formation is performed with a citric acid-based etchant using the resist patterns 4, 5, and 6 as a mask to expose the AlGaAs layer 12 on the surface of the substrate 21. Next, as shown in FIG. 4G, a metal, that is, Ti / Au 13, 14 is deposited on the entire surface to a thickness of 5000 °. Thereafter, as shown in FIG. 4H, lift-off is performed while leaving only the metal 13 deposited on the bottom surface 12 of the opening 11.
[0026]
According to the first embodiment, the pattern to be drawn is divided into the upper part and the lower part of the T gate, and the resists 4, 5, and 6 laminated in three layers can be separately developed, so that the opening 9 of each layer can be developed. , 10, and 11 can be controlled independently, and a gate electrode having a desired shape can be easily manufactured. The remaining metal 13 serves as a gate electrode.
[0027]
Example 2
FIGS. 5A to 5D and FIGS. 6E to 6H are views showing the steps of Embodiment 2 of the method for manufacturing a semiconductor device according to the present invention. In the second embodiment, in two electron beam exposures, one end of the second region with a large amount of exposure is made to coincide with one end of the first region with a small amount of exposure. Exposure was performed.
[0028]
More specifically, in the second embodiment, similarly to the first embodiment, the resists 4, 5, and 6 are applied to the HEMT substrate 21, and after baking, the electron beam patterns 7, 8 are drawn using an electron beam drawing apparatus. (FIGS. 5A and 5B) At this time, in Example 2, the pattern to be drawn is a 0.8 μm wide pattern 7 of the first region and a second pattern as shown in FIG. 5B. The narrow pattern 8 having a width of 0.1 μm in the second region is overlapped, and the end of the narrow pattern 8 coincides with the end of the wide pattern 7.
[0029]
Next, as shown in FIGS. 5 (c), 5 (d), and 6 (e), development processing of three layers of resists 4, 5, and 6 is performed in the same manner as in the first embodiment. In FIG. 6B, since the exposure is performed so that the end of the narrow pattern 8 coincides with the end of the wide pattern 7, the third opening 11 is not located at the center of the wide pattern, as shown in FIG. , Can be formed in one side. Next, as shown in FIG. 6F, the AlGaAs layer 12 is exposed on the surface of the substrate 21. Next, as shown in FIG. 6G, a metal, that is, Ti / Au 13, 14 is deposited on the entire surface to a thickness of 5000 °. Thereafter, as shown in FIG. 6H, lift-off is performed while leaving only the metal 13 deposited on the bottom surface 12 of the opening 11. The remaining metal 13 serves as a gate electrode.
[0030]
According to the second embodiment, since the gate electrode in contact with the semiconductor substrate 21 can be made closer to the source electrode, the parasitic resistance between the gate and the source can be reduced, and a HEMT with low noise characteristics can be manufactured. .
[0031]
【The invention's effect】
As described above, according to the first to fifth aspects of the present invention, a first positive electron beam resist, a second positive electron beam resist, and a third positive electron beam resist are formed on a semiconductor substrate. a first step of laminating a line resist sequentially, after the first step, a first region of the electron beam resist consisting of three layers and a second step of exposing using an electron beam, a second step after, in the first region, a third step of the narrow second region than the first region is exposed using an electron beam, after the third step, a third electron beam resist the A fourth step of developing one region to form a first opening, and a fifth step of developing the second electron beam resist to form a second opening after the fourth step If, after the fifth step, a sixth step of the first electron beam resist is developed to the second region to form a third opening, the After step, a seventh step of forming a recess groove in the semiconductor substrate through the three openings, after the seventh step, an eighth step of depositing a metal interconnect layer for the gate electrode on the entire surface of the semiconductor substrate After the eighth step , the first and second electron beam resists and the unnecessary metal wiring layers thereon are lifted off by a lift-off method while leaving the metal wiring layers deposited in the recess grooves among the metal wiring layers. And the ninth step of removing the resist, the opening dimensions of the three layers of resist can be precisely controlled, and the opening dimensions of each layer can be controlled independently. As a result, an opening having a desired shape can be easily formed in the three-layer resist, a gate electrode having a desired shape can be manufactured, and the controllability of the size of the low-resistance layer portion of the semiconductor device and the control of the overhang shape can be achieved. It is possible to remarkably enhance the performance. In particular, when used in the process of forming a low-resistance gate electrode of a HEMT, the controllability of the size of the low-resistance layer portion and the controllability of the overhang shape can be improved, and a gate electrode having a desired shape can be manufactured. it can.
[0032]
According to the sixth aspect, by aligning one end of the second region with a large amount of exposure with one end of the first region with a small amount of exposure, the gate electrode in contact with the semiconductor substrate is formed. Since it can be close to the source electrode, the parasitic resistance between the gate and the source can be reduced, and the noise characteristics of the semiconductor device can be improved.
[Brief description of the drawings]
FIG. 1 is a view showing one example of a process of a method of manufacturing a semiconductor device according to the present invention.
FIG. 2 is a view showing one example of a process of a method of manufacturing a semiconductor device according to the present invention.
FIG. 3 is a diagram showing a manufacturing process of the first embodiment.
FIG. 4 is a view showing a manufacturing process of the first embodiment.
FIG. 5 is a view showing a manufacturing process of the second embodiment.
FIG. 6 is a view showing a manufacturing process of the second embodiment.
[Explanation of symbols]
Reference Signs List 1 GaAs layer 2 AlGaAs layer for supplying secondary electrons 3 High-concentration GaAs layer 4 First electron beam resist 5 Second electron beam resist 6 Third electron beam resist 7 Wide electron beam pattern 8 Thin electron beam pattern 9 first opening 10 second opening 11 third opening 12 recess grooves 13, 14 metal wiring layer 21 semiconductor substrate

Claims (6)

A first step of sequentially laminating a first positive-type electron beam resist, a second positive-type electron beam resist, and a third positive-type electron beam resist on a semiconductor substrate; and after the first step, A second step of exposing the first region of the three-layer electron beam resist using an electron beam, and after the second step, a second region smaller than the first region in the first region. third a step, after the third step, a fourth step of forming a first opening and developing the first region for a third electron beam resist is exposed using an electron beam area When, after the fourth step, a fifth step of forming a second opening by developing the second electron beam resist, after the fifth step, the for the first electron beam resist second a sixth step of forming a third opening and developing the region, after the sixth step, the semiconductor substrate through the three openings A seventh step of forming a Seth groove, after the seventh step, an eighth step of depositing a metal interconnect layer for the gate electrode on the entire surface of the semiconductor substrate, after the eighth step, the metal wiring layer And a ninth step of removing the first and second electron beam resists and unnecessary metal wiring layers thereon by a lift-off method while leaving the metal wiring layers deposited in the recess grooves. A method for manufacturing a semiconductor device, comprising: 2. The method for manufacturing a semiconductor device according to claim 1, wherein the third resist has a higher sensitivity than the first resist, and the first resist has a higher resolution than the third resist. A method for manufacturing a semiconductor device, which is used. 2. The method for manufacturing a semiconductor device according to claim 1, wherein an organic developer is used for developing the first and third electron beam resists, and an alkali developer is used for developing the second electron beam resist. Semiconductor device manufacturing method. 4. The method for manufacturing a semiconductor device according to claim 3, wherein a highly soluble developer is used for developing the third electron beam resist, and a low soluble developer is used for developing the first electron beam resist. A method for manufacturing a semiconductor device, comprising: 5. The method for manufacturing a semiconductor device according to claim 1, wherein the first and third electron beam resists use a copolymer resist of alpha methyl styrene and alpha chloroacrylic acid, A method for manufacturing a semiconductor device, wherein polymethyl glutarimide is used for the second electron beam resist. 2. The method for manufacturing a semiconductor device according to claim 1, wherein one end of the second region coincides with one end of the first region when the three-layer electron beam resist is exposed to an electron beam. And a method of manufacturing a semiconductor device.

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