JP3570944B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having a test circuit for performing a test for inspecting a manufacturing defect.
[0002]
[Prior art]
Even if the semiconductor integrated circuit is correctly designed, if a defect occurs during manufacturing, the semiconductor integrated circuit does not operate. To prevent this, a test is required to confirm that the manufactured semiconductor integrated circuit operates properly. The test in this case is to check whether or not there is a defect not in the design but in the manufacture of the semiconductor integrated circuit. In order to perform such a test, a semiconductor integrated circuit is designed to include a test circuit therein.
[0003]
As the scale and complexity of semiconductor integrated circuits increase, it has become more difficult to design not only semiconductor integrated circuits but also test circuits. Design innovation to simplify test design is referred to as test facilitation design. In general, design for testability requires some change in the circuit structure. However, it is required that the operation speed is not reduced and that the number of input / output terminals and the amount of hardware are minimized.
[0004]
There is a scan design as a typical method of design for testability. In the scan design, all the storage elements (flip-flops) inside the semiconductor integrated circuit are operated as shift registers at the time of testing, so that the state setting and state observation of the shift register can be performed via the input / output terminals at the time of testing. The circuit can be regarded as a combinational circuit. Therefore, a test with a high fault detection rate can be performed by applying the function test sequence generation method for combinational circuits.
[0005]
The scan design includes a scan path and an LSSD (Level Sensitive Scan Design), but the present invention relates to a semiconductor integrated circuit having a scan path type test circuit.
[0006]
FIG. 10 is a circuit diagram showing a configuration of such a conventional semiconductor integrated circuit. As shown in FIG. 10, a plurality of scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn are provided inside the semiconductor integrated circuit. FIG. 11 is a circuit diagram showing a configuration of a scan path test flip-flop in a semiconductor integrated circuit. As shown in FIG. 11, the selector 10 is connected to the data input terminal D of the flip-flop circuit 11 for all of the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn in the semiconductor integrated circuit. .
[0007]
The selector 10 selects one of the two data input terminals D and SI according to the switching control signal input from the scan path test mode switching terminal M, and selects the data supplied from the selected terminal. Is output to the flip-flop circuit 11. The flip-flop circuit 11 fetches data supplied from the data input terminal D or the data input terminal SI via the selector 10 in synchronization with the clock pulse of the clock signal supplied from the clock input terminal C, and outputs the fetched data. Is output from the data output terminal Q.
[0008]
As shown in FIG. 10, the scan path test flip-flops X1 to Xn each have a data input terminal D connected to the data input terminal 1 and a scan path test mode switching terminal M connected to the switching control signal input terminal 3. The clock input terminal C is connected to the clock input terminal 4 and the data output terminal Q is connected to the combination circuit 7.
[0009]
Each of the scan path test flip-flops Y1 to Yn has a data input terminal D connected to the combinational circuit 7, a scan path test mode switching terminal M connected to the switching control signal input terminal 3, and a clock input terminal C Are connected to the clock input terminal 4, and the data output terminal Q is connected to the combinational circuit 8.
[0010]
Each of the scan path test flip-flops Z1 to Zn has a data input terminal D connected to the combinational circuit 8, a scan path test mode switching terminal M connected to the switching control signal input terminal 3, and a clock input terminal C Are connected to the clock input terminal 4 and the data output terminal Q is connected to the data output terminal 5.
[0011]
Further, the data input terminal SI of the scan path test flip-flop X1 is connected to the scan data input terminal 2, and the data input terminals SI of the scan path test flip-flops X2 to Xn, Y1 to Yn and Z1 to Zn are respectively connected to The data output terminal Q of the preceding scan path test flip-flop Zn is connected to the scan data output terminal 6. Therefore, for the data supplied from the scan data input terminal 2 (scan data used for the scan path test), all the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn It will work as.
[0012]
The plurality of data input terminals 1 are terminals for inputting data (normal data) during normal operation of the semiconductor integrated circuit, and the scan data input terminal 2 is a terminal for inputting scan data used for a scan path test. The switching control signal input terminal 3 is a terminal for inputting a switching control signal for switching the selector 10 in the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn.
[0013]
The clock input terminal 4 is a terminal for inputting a clock signal for operating the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn. The plurality of data output terminals 5 are terminals for outputting normal data during normal operation of the semiconductor integrated circuit, and the scan data output terminals 6 are terminals for outputting scan data used for a scan path test.
[0014]
Each of the combinational circuits 7 and 8 is a circuit to be tested in the scan path test, and includes a plurality of gates and the like. The combinational circuit 7 inputs data (normal data or scan data) from each of the scan path test flip-flops X1 to Xn connected to the input side, and inputs the input data via a gate in the circuit to the output side. To each of the scan path test flip-flops Y1 to Yn connected to the scan path test circuit. Further, the combinational circuit 8 inputs data from the scan path test flip-flops Y1 to Yn connected to the input side, and transfers the input data to the respective output side connected to the output side via a gate in the circuit. Output to the scan path test flip-flops Z1 to Zn.
[0015]
Next, the operation of the scan path test will be described.
FIG. 12 is a timing chart for explaining a scan path test operation of a conventional semiconductor integrated circuit. Here, for example, it is assumed that the scan path test flip-flop Xn-m and the scan path test flip-flop Y1 are connected via a gate in the combinational circuit 7 (that is, the scan path test flip-flop Xn). -M is output to the scan path test flip-flop Y1 via the gate in the combinational circuit 7), and the failure detection of the gate in the combinational circuit 7 is performed as an example. The operation of the scan path test will be described.
[0016]
(1) Scan data capture (shift mode)
First, all the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn shift the scan data input from the data input terminal SI based on the switching control signal output from the switching control signal input terminal 3. The selector 10 is switched to the mode.
[0017]
Next, the scan data (A1, A2,...) Is serially input to the scan data input terminal 2. The scan path test flip-flop X1 captures the scan data output from the scan data input terminal 2 in synchronization with the clock pulse of the clock signal output from the clock input terminal 4, and transfers the captured scan data to the next stage. Shift to the scan path test flip-flop X2. Similarly to the scan path test flip-flop X1, the scan path test flip-flops X2 to Xn-m also fetch the scan data output from the preceding stage scan path test flip-flop and transfer the fetched scan data to the next stage. Shift to the scan path test flip-flop. The scan data is shifted to the scan path test flip-flop Xn.
[0018]
As described above, in the shift mode, the scan path test flip-flops X to Xn operate as shift registers, sequentially shift the scan data, and set the scan data in the combinational circuit 7. Here, the scan data A2 is set in the scan path test flip-flop Xn-m.
[0019]
(2) Testing of combinational circuits 7 and 8 (normal mode)
Next, all the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn input normal data from the data input terminal D based on the switching control signal output from the switching control signal input terminal 3. The selector 10 is switched to the normal mode.
[0020]
When the mode is switched to the normal mode, the scan data set in the combinational circuit 7 is taken into the scan path test flip-flops Y1 to Yn via the gate in the combinational circuit 7. Here, the scan data set in the scan path test flip-flop Xn-m is output to and taken in by the scan path test flip-flop Y1 via the gate in the combinational circuit 7, as described above.
[0021]
(3) Output of scan data (shift mode)
Next, again, all the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn scan data from the data input terminal SI based on the switching control signal output from the switching control signal input terminal 3. The selector 10 is switched to the input shift mode.
[0022]
The scan data taken in by the scan path test flip-flops Y1 to Yn is shifted to the scan path test flip-flop Zn in synchronization with the clock pulse of the clock signal output from the clock input terminal 4, and is used for the scan path test. The data is output from the scan data output terminal 6 connected to the data output terminal Q of the flip-flop Zn.
[0023]
By inspecting the scan data output from the scan data output terminal 6, a failure in the gates in the combinational circuits 7, 8 can be detected. The above operation is repeated to improve the accuracy of the failure detection of the semiconductor integrated circuit.
[0024]
[Problems to be solved by the invention]
However, in the above-described conventional semiconductor integrated circuit, at least several flip-flops of the clock signal are required for one scan path test. Therefore, when the scan path test is performed n times in order to obtain a high failure detection rate of the semiconductor integrated circuit, a test pattern of scan data dedicated to the scan test requires the number of flip-flops × 2 × n patterns.
[0025]
Therefore, first, when a scan path test of a large-scale semiconductor integrated circuit is performed, only one gate of the combinational circuits 7 and 8 is tested. Clock pulses are required by the number of flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn for scan path test (that is, all scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn). The number of clock pulses required to shift the scan data becomes larger), and the pattern length of the test pattern of the scan data becomes longer (because the data amount of the scan data becomes larger), so that the test efficiency becomes worse and the test time becomes longer. There was a problem that would be.
[0026]
Second, as the size of the semiconductor integrated circuit increases, the pattern length of the test pattern of the scan data increases, so that a large amount of test pattern memory of the tester (test apparatus) must be used. When testing the semiconductor integrated circuit described above, there is a problem that the permissible amount of the test pattern memory increases accordingly and the cost required for the test increases.
[0027]
Third, as the size of the semiconductor integrated circuit increases, the overhead required for executing the scan path test (the circuit required for the scan path test) increases, and the test pattern of the scan path data having a longer pattern length. Therefore, there is a problem that power consumption for switching the selectors 10 of all the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn increases.
[0028]
The present invention has been made to solve the above-described problems, and can reduce the time required for a scan path test and reduce the amount of scan data used for the scan path test. It is an object of the present invention to obtain a semiconductor integrated circuit capable of reducing the overhead and power consumption for a scan path test.
[0029]
[Means for Solving the Problems]
The semiconductor integrated circuit according to the first aspect of the present invention, Normal mode A high-speed clock signal circuit that generates a high-speed clock signal with a half cycle of the clock signal at the time, and random data based on scan data used for a scan path test, and a high-speed clock signal generated by the high-speed clock signal circuit A high-speed data generation circuit for generating high-speed scan data in which scan data and random data alternately appear at a period of, and performing a scan path test using the high-speed scan data generated by the high-speed data generation circuit. .
[0030]
The semiconductor integrated circuit according to the invention of claim 2 is: Normal mode A high-speed clock signal circuit that generates a high-speed clock signal with a half cycle of the clock signal at the time, and random data based on scan data used for a scan path test, and a high-speed clock signal generated by the high-speed clock signal circuit A high-speed data generation circuit that generates high-speed scan data in which scan data and random data alternately appear in a cycle of: a semiconductor integrated circuit is divided into a plurality of functional module circuits for each functional module, The scan path test is performed independently of each other in parallel with the high-speed scan data generated by the high-speed data generation circuit.
[0031]
According to a third aspect of the present invention, in the semiconductor integrated circuit, the high-speed data generation circuit shifts the scan data by one bit, and generates an exclusive OR of the data shifted by one bit and the scan data to generate random data. A random data generation circuit, Input to clock input terminal A selector circuit that alternately selects scan data and random data based on the high / low of the clock signal to generate high-speed scan data may be used.
[0032]
A semiconductor integrated circuit according to a fourth aspect of the present invention is a high-speed data generation circuit. To High-speed clock generator for high-speed scan data By Generate Is Flip-flop circuit synchronized with the high-speed clock signal May be included .
[0037]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described.
Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to Embodiment 1 of the present invention. As shown in FIG. 1, each of the scan path test flip-flops X1 to Xn has a data input terminal D connected to the data input terminal 1 and a scan path test mode switching terminal M connected to the switching control signal input terminal 3A. The clock input terminal C is connected to the high-speed clock generation circuit 21, and the data output terminal Q is connected to the combination circuit 7.
[0038]
The scan path test flip-flops Y1 to Yn-m each have a data input terminal D connected to the combinational circuit 7, a scan path test mode switching terminal M connected to the switching control signal input terminal 3A, and a clock input. The terminal C is connected to the high-speed clock generation circuit 21, and the data output terminal Q is connected to the combination circuit 8.
[0039]
The scan path test flip-flop Yn has a data input terminal D connected to the combinational circuit 7, a scan path test mode switching terminal M connected to the switching control signal input terminal 3B, and a clock input terminal C connected to a high-speed clock generation terminal. The data output terminal Q is connected to the combination circuit 8.
[0040]
Each of the scan path test flip-flops Z1 to Zn has a data input terminal D connected to the combinational circuit 8, a scan path test mode switching terminal M connected to the switching control signal input terminal 3B, and a clock input terminal C Are connected to the high-speed clock generation circuit 21, and the data output terminal Q is connected to the data output terminal 5.
[0041]
Further, the data input terminals SI of the scan path test flip-flops X1 and Yn are connected to the high-speed data generation circuit 22, and the data input terminals of the scan path test flip-flops X2 to Xn, Y1 to Yn-m and Z1 to Zn. SI is connected to the data output terminal Q of the preceding scan path test flip-flop. The data output terminal Q of the scan path test flip-flop Yn-m is connected to the scan data output terminal 6A, and the data output terminal Q of the scan path test flip-flop Zn is connected to the scan data output terminal 6B.
[0042]
Accordingly, the scan path test flip-flops X1 to Xn and Y1 to Yn-m and the scan path test flip-flops Yn and Z1 to Zn are used as shift registers for the data supplied from the high-speed data generation circuit 22. It will work.
[0043]
The plurality of data input terminals 1 are terminals for inputting data (normal data) during normal operation of the semiconductor integrated circuit, and the scan data input terminal 2 is a terminal for inputting scan data used for a scan path test. The switching control signal input terminal 3A is a terminal for inputting a switching control signal for switching the selector 10 in the scan path test flip-flops X1 to Xn and Y1 to Yn-m, and the switching control signal input terminal 3B is connected to the scan path test flip-flop. Terminal for inputting a switching control signal for switching the selector 10 in the flip-flops Yn, Z1 to Zn for use.
[0044]
The clock input terminal 4 is a terminal for inputting a clock signal, and the plurality of data output terminals 5 are terminals for outputting normal data during normal operation of the semiconductor integrated circuit. The scan data output terminal 6A is a terminal for outputting high-speed scan data output from the scan path test flip-flop Yn-m, and the scan data output terminal 6B is a high-speed scan output from the scan path test flip-flop Zn. Terminal for outputting data.
[0045]
Each of the combinational circuits 7 and 8 is a circuit to be tested in the scan path test, and includes a plurality of gates and the like.
[0046]
As shown in FIG. 1, the scan path test flip-flops X1 to Xn, Y1 to Yn, Z1 to Zn and the combinational circuits 7 and 8 in the semiconductor integrated circuit are divided for each functional module. The function module circuit 12 includes scan path test flip-flops X1 to Xn and Y1 to Yn-m and a combination circuit 7. The function module circuit 13 includes scan path test flip-flops Yn and Z1 to Zn and a combination circuit 8. It is composed of
[0047]
The high-speed clock generation circuit 21 is provided between the clock input terminal 4 and the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn, and includes a delay circuit 14 and an EX-OR circuit (exclusive OR circuit). ) 15. The delay circuit 14 is connected to the clock input terminal 4 and delays the clock signal output from the clock input terminal 4 by １ ／ cycle and outputs the delayed clock signal. The EX-OR circuit 15 performs an exclusive OR operation on the clock signal output from the clock input terminal 4 and the clock signal delayed by 周期 cycle output from the delay circuit 14 to obtain an exclusive OR of a half cycle of the clock signal. It generates a high-speed clock signal and outputs the high-speed clock signal.
[0048]
The high-speed data generation circuit 22 is provided between the scan data input terminal 2 and the clock input terminal 4 and the scan path test flip-flops X1 and Yn, and includes the flip-flop circuits 16, 17, 20 and an EX-OR circuit (exclusively). (OR circuit) 18 and a selector circuit 19.
[0049]
The flip-flop circuit 16 shifts the scan data output from the scan data input terminal 2 in synchronization with the rise of the clock pulse of the clock signal output from the clock input terminal 4. The scan data output from the flip-flop circuit 16 is shifted in synchronization with the fall of the clock pulse of the clock signal output from the clock input terminal 4.
[0050]
The EX-OR circuit 18 outputs random data obtained by performing an exclusive OR operation on the scan data output from the scan data input terminal 2 and the 1-bit shifted scan data output from the flip-flop circuit 17. is there.
[0051]
The selector circuit 19 selects the scan data output from the scan data input terminal 2 when the clock signal output from the clock input terminal 4 is at a low level, and selects the scan signal output from the clock input terminal 4 at a high level. In this case, by selecting random data output from the EX-OR circuit 18, high-speed scan data having a half cycle (double the data amount) of the scan data is generated, and the high-speed scan data is output to the flip-flop circuit 20. Is output to
[0052]
The flip-flop circuit 20 outputs high-speed scan data to the scan path test flip-flops X1 and Yn in synchronization with the clock pulse of the high-speed clock signal output from the high-speed clock generation circuit 21.
[0053]
Next, the operation will be described.
FIG. 2 is a timing chart for explaining a scan path test operation of the semiconductor integrated circuit according to the first embodiment of the present invention.
[0054]
(A) Operation of high-speed clock generation circuit 21
First, the operation of the high-speed clock generation circuit 21 will be described. The delay circuit 14 delays the clock signal output from the clock input terminal 4 by １ ／ cycle and outputs the delayed clock signal to the EX-OR circuit 15. The EX-OR circuit 15 performs an exclusive OR operation on the clock signal output from the clock input terminal 4 and the clock signal delayed by 1/4 cycle output from the delay circuit 14 to obtain an exclusive OR of a half cycle of the clock signal. A high-speed clock signal is generated, and the high-speed clock signal is output.
[0055]
(B) Operation of high-speed data generation circuit 22
Next, the operation of the high-speed data generation circuit 22 will be described. The scan data (A, B, C...) Is output from the scan data input terminal 2 to the flip-flop circuit 16, the EX-OR circuit 18, and the selector circuit 19.
[0056]
The flip-flop circuit 16 shifts the scan data output from the scan data input terminal 2 in synchronization with the rise of the clock pulse of the clock signal, and the flip-flop circuit 17 synchronizes with the fall of the clock pulse of the clock signal. Then, the scan data output from the flip-flop circuit 16 is shifted. As a result, the scan data output from the scan data input terminal 2 is shifted by one clock (one bit) by the flip-flop circuits 16 and 17.
[0057]
The EX-OR circuit 18 calculates the exclusive OR of the scan data output from the scan data input terminal 2 and the 1-bit shifted scan data output from the flip-flop circuit 17 to generate random data (a, b, c) and outputs the random data to the selector circuit 19.
[0058]
The selector circuit 19 selects the scan data output from the scan data input terminal 2 when the clock signal is at a low level, and selects the random data output from the EX-OR circuit 18 when the clock signal is at a high level. By doing so, the scan data and the random data alternately appear in a half cycle of the scan data. As a result, high-speed scan data (A, a, B, b...) Having a half cycle (double data amount) of the scan data is generated. The selector circuit 19 outputs the generated high-speed scan data to the flip-flop circuit 20.
[0059]
The flip-flop circuit 20 synchronizes with the clock pulse of the high-speed clock signal output from the high-speed clock generation circuit 21 (coincides the changing point of the high-speed scan data with the falling edge of the clock pulse of the high-speed clock signal), The high-speed scan data is output to the scan path test flip-flops X1 and Yn. As described above, by synchronizing the high-speed clock signal and the high-speed scan data, the racing between the high-speed clock signal and the high-speed scan data during the scan path test is prevented.
[0060]
(C) Scan path test operation
Next, the operation of the scan path test will be described. Here, for example, the scan path test flip-flop Xn-m and the scan path test flip-flop Y1 are connected via a gate in the combinational circuit 7, and the scan path test flip-flop Yn and the scan path test flip-flop Yn are connected to each other. Assuming that the flip-flop for use Z1 is connected via the gate in the combinational circuit 8, the operation of the scan path test will be described by taking as an example the case of detecting the failure of the gate in the combinational circuits 7, 8. .
[0061]
(1) High-speed scan data capture (shift mode)
First, the scan path test flip-flops X1 to Xn and Y1 to Yn-m are based on the switching control signal output from the switching control signal input terminal 3A, and the scan path test flip-flops Yn and Z1 to Zn are Based on the switching control signal output from the switching control signal input terminal 3B, the selector 10 switches to the shift mode in which high-speed scan data is input from the data input terminal SI.
[0062]
Next, the high-speed scan data (A, a, B, b,...) Is output from the high-speed data generation circuit 22 to the scan path test flip-flops X1, Yn. The scan path test flip-flops X1 to Xn-m respectively shift high-speed scan data to the next-stage scan path test flip-flop in synchronization with the clock pulse of the high-speed clock signal output from the high-speed clock generation circuit 21. I will do it. The scan data is shifted to the scan path test flip-flop Xn.
[0063]
In the circuit example of FIG. 1, since the scan path test flip-flops other than the scan path test flip-flop Yn do not exist on the input side of the combinational circuit 8 in the functional module circuit 13, the scan path test flip-flop Yn is There is no need to shift high-speed scan data.
[0064]
Here, high-speed scan data a is set in the scan path test flip-flop Xn-m, and high-speed scan data A is set in the scan path test flip-flop Yn.
[0065]
(2) Testing of combinational circuits 7 and 8 (normal mode)
Next, the scan path test flip-flops X1 to Xn and Y1 to Yn-m are based on the switching control signal output from the switching control signal input terminal 3A, and the scan path test flip-flops Yn and Z1 to Zn are The selector 10 is switched to the normal mode in which normal data is input from the data input terminal D based on the switching control signal output from the switching control signal input terminal 3B.
[0066]
When the mode is switched to the normal mode, the high-speed scan data set in the combination circuit 7 is taken into the scan path test flip-flops Y1 to Yn via the gate in the combination circuit 7. The high-speed scan data set in the combinational circuit 8 is taken into the scan path test flip-flops Z1 to Zn via gates in the combinational circuit 8.
[0067]
Here, the high-speed scan data set in the scan path test flip-flop Xn-m is output to and captured by the scan path test flip-flop Y1 via the gate in the combinational circuit 7, as described above. Also, the high-speed scan data set in the scan path test flip-flop Yn is output to the scan path test flip-flop Z1 via the gate in the combinational circuit 8 and taken in, as described above.
[0068]
(3) Output of high-speed scan data (shift mode)
Next, again, the scan path test flip-flops X1 to Xn and Y1 to Yn-m are based on the switching control signal output from the switching control signal input terminal 3A, and are also used for the scan path test flip-flops Yn and Z1 to Yn. Zn switches the selector 10 to the shift mode in which high-speed scan data is input from the data input terminal SI based on the switching control signal output from the switching control signal input terminal 3B.
[0069]
The high-speed scan data captured by the scan path test flip-flops Y1 to Yn-m is synchronized with the clock pulse of the high-speed clock signal output from the high-speed clock generation circuit 21 to the scan path test flip-flops Yn-m. The data is shifted and output from the scan data output terminal 6A connected to the data output terminal Q of the scan path test flip-flop Yn-m. The high-speed scan data taken into the scan path test flip-flops Z1 to Zn is shifted to the scan path test flip-flop Zn in synchronization with the clock pulse of the high-speed clock signal output from the high-speed clock generation circuit 21. Are output from the scan data output terminal 6B connected to the data output terminal Q of the scan path test flip-flop Zn.
[0070]
By inspecting the high-speed scan data output from the scan data output terminals 6A and 6B, it is possible to detect a gate failure in the combinational circuits 7 and 8 for each of the functional module circuits 12 and 13, respectively.
[0071]
As described above, according to the first embodiment, the high-speed clock generation circuit 21 generates a high-speed clock signal having a half cycle of the clock signal, and the high-speed data generation circuit 22 generates a high-speed scan signal having a half cycle of the scan data. Since the scan path test is executed by generating the data and using the high-speed clock signal and the high-speed scan data, the scan path test can be performed in half the time as compared with the conventional scan path test.
[0072]
Further, since the high-speed data generation circuit 22 is configured to generate high-speed scan data having a half cycle (double the data amount) of the scan data from the scan data, the pattern length of the test pattern of the scan data may be reduced. Can be. Therefore, the capacity of the test pattern memory of the tester (test apparatus) can be reduced, and as a result, the cost required for the test can be reduced.
[0073]
In addition, the semiconductor integrated circuit is divided into functional module circuits 12 and 13 for each functional module, and the functional module circuits 12 and 13 are configured so that they can be tested independently in parallel. Can be shortened.
[0074]
For example, assuming that there are 100 scan path test flip-flops in a semiconductor integrated circuit and the scan path test of the semiconductor integrated circuit is executed 100 times, the test pattern of the scan data is 100 in the conventional semiconductor integrated circuit. × 2 × 100 = 20000 patterns are required, but in the first embodiment, the test pattern of the scan data is 50 × 2 × 100 = 10000 by dividing into 50 functional modules of the scan path test flip-flop. A scan path test can be performed on the pattern.
[0075]
Therefore, the time required for the test can be further reduced, and the cost required for the test can be reduced. Further, since the pattern length of the test pattern of the scan data can be shortened, the number of times of switching the selector 10 of the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn can be reduced as a whole. As a result, power consumption for the scan path test can be reduced.
[0076]
Embodiment 2 FIG.
FIG. 3 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 3, an EX-OR circuit 23 is a circuit that performs an exclusive OR operation on each data output from the combination circuit 7 to the scan path test flip-flops Y1 to Yn, and an EX-OR circuit 24 is a combination circuit. 8 is a circuit for performing an exclusive OR operation on each data output to the scan path test flip-flops Z1 to Zn. The output terminal 25A is a terminal that outputs output data of the EX-OR circuit 23, and the output terminal 25B is a terminal that outputs output data of the EX-OR circuit 24.
[0077]
Since the other configuration is the same as that shown in FIG. 1, the same components are denoted by the same reference numerals, and redundant description will be omitted.
[0078]
Next, the operation will be described.
The operation of the configuration other than the EX-OR circuits 23 and 24 is the same as that described in the first embodiment, and a duplicate description will be omitted.
[0079]
In the test operation of the combinational circuits 7 and 8 (operation (2) of the first embodiment), when the selector 10 of the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn is switched to the normal mode. As described in the first embodiment, the high-speed scan data set in the combinational circuit 7 is taken into the scan path test flip-flops Y1 to Yn via the gate in the combinational circuit 7, and The high-speed scan data set to 8 is taken into the scan path test flip-flops Z1 to Zn via the gate in the combinational circuit 8.
[0080]
Here, the high-speed scan data output from the combinational circuit 7 is output not only to the scan path test flip-flops Y1 to Yn but also to the EX-OR circuit 23, and the high-speed scan data output from the combinational circuit 8 is output. Are output not only to the scan path test flip-flops Z1 to Zn but also to the EX-OR circuit 24.
[0081]
The EX-OR circuits 23 and 24 take the exclusive OR of the high-speed scan data output from the combination circuits 7 and 8, and output the result to the output terminals 25A and 25B. At this time, if the number of “1” in all the high-speed scan data output from the combination circuits 7 and 8 is an even number, the value of the data output from the EX-OR circuits 23 and 24 is “0”. Become. On the other hand, when the number of “1” in all the high-speed scan data output from the combination circuits 7 and 8 is an odd number, the value of the data output from the EX-OR circuits 23 and 24 is “1”. .
[0082]
Therefore, when the data output from the output terminals 25A and 25B is different from the expected value obtained in advance, it can be determined that a failure has occurred in the odd number of gates in the combinational circuits 7 and 8.
[0083]
As described above, according to the second embodiment, the EX-OR circuits 23 and 24 are configured to take the exclusive OR of all the high-speed scan data output from the combination circuits 7 and 8. By inspecting the high-speed scan data output from the scan data output terminals 6A and 6B, the gates in the combinational circuits 7 and 8 (odd number gates) are detected before the gates in the combinational circuits 7 and 8 are detected as faulty. Therefore, the failure of the combinational circuits 7 and 8 can be detected at an early stage, and the failure detection rate of the scan path test can be further increased.
[0084]
Embodiment 3 FIG.
FIG. 4 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to Embodiment 3 of the present invention. The high-speed data generation circuit 30 according to the third embodiment includes an inverter circuit 26, a PN pattern generation circuit 27, a selector circuit 19, and a flip-flop circuit 20. The inverter circuit 26 is a circuit for inverting the clock signal output from the clock input terminal 4, and the PN pattern generation circuit 27 is based on the generated polynomial based on the inverted clock signal output from the inverter circuit 26. This is a circuit that generates pseudo-random data.
[0085]
The selector circuit 19 selects the scan data output from the scan data input terminal 2 when the clock signal output from the clock input terminal 4 is at a low level, and selects the scan signal output from the clock input terminal 4 at a high level. At this time, by selecting random data output from the PN pattern generation circuit 27, high-speed scan data having a half cycle (double the data amount) of the scan data is generated, and the high-speed scan data is output to the flip-flop circuit 20. Is output to
[0086]
The flip-flop circuit 20 outputs high-speed scan data to the scan path test flip-flops X1 and Yn in synchronization with the clock pulse of the high-speed clock signal output from the high-speed clock generation circuit 21.
[0087]
Since the other configuration is the same as that shown in FIG. 1, the same components are denoted by the same reference numerals, and redundant description will be omitted.
[0088]
FIG. 5 is a circuit diagram showing a configuration example of the PN pattern generation circuit. In FIG. 5, flip-flop circuits 32 m to 320 connected in m + 1 stages operate based on a clock signal input from input terminal 31. The EX-OR circuit 33 calculates the exclusive OR of the output data of the flip-flop circuit 321 and the output data of the flip-flop circuit 320, and outputs the output data to the flip-flop circuit 32m. Random data is output from the output terminal 34 connected to the output terminal D of the flip-flop circuit 320.
[0089]
Next, the operation will be described.
Note that the operation of the configuration other than the high-speed data generation circuit 30 is the same as that described in the first embodiment, and thus redundant description will be omitted.
[0090]
Inverter circuit 26 inverts the clock signal output from clock input terminal 4 and outputs the inverted signal to PN pattern generation circuit 27. In the PN pattern generation circuit 27, the flip-flop circuits 32m to 320 connected in (m + 1) stages operate in synchronization with the falling edge of the clock pulse of the clock signal output from the inverter circuit 26, thereby generating random data. The random data generated by the PN pattern generation circuit 27 becomes complicated data with high randomness as compared with the random data generated by the flip-flop circuits 16 and 17 and the EX-OR circuit 18 shown in FIG. ing.
[0091]
Thereafter, as described in the first embodiment, the selector circuit 19 generates high-speed scan data having a half cycle (double the data amount) of the scan data, and the flip-flop circuit 20 generates the high-speed clock generation circuit. The high-speed scan data is output to the scan path test flip-flops X1 and Yn in synchronization with the clock pulse of the high-speed clock signal output from 21.
[0092]
As described above, in the third embodiment, in the high-speed data generation circuit 30, random data is generated by the PN pattern generation circuit 27, so that complicated random data with high randomness can be generated. The high-speed scan data also has high randomness, so that the objectivity of the high-speed scan data can be improved. As a result, the failure detection rate of the scan path test can be increased.
[0093]
Embodiment 4 FIG.
FIG. 6 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to Embodiment 4 of the present invention. The semiconductor integrated circuit shown in FIG. 6 is different from the semiconductor integrated circuit shown in FIG. 1 in that scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn are connected to scan path test flip-flops XX1 to XX1. XXn, YY1 to YYn and ZZ1 to ZZn.
[0094]
FIG. 7 is a circuit diagram showing a configuration of the scan path test flip-flops XX1 to XXn, YY1 to YYn, and ZZ1 to ZZn. As shown in FIG. 7, the scan path test flip-flops XX1 to XXn, YY1 to YYn, and ZZ1 to ZZn are the same as the scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn shown in FIG. An EX-OR circuit 38 has been added. The EX-OR circuit 38 calculates the exclusive OR of the data output from the data input terminal D and the data output from the terminal TI and outputs the result from the terminal TO.
[0095]
The configuration other than the scan path test flip-flops XX1 to XXn, YY1 to YYn, and ZZ1 to ZZn is the same as that shown in FIG. 1 above. Description is omitted.
[0096]
Next, the operation will be described.
The operation other than the test operation of the combinational circuits 7 and 8 (the operation (2) of the first embodiment) is the same as that of the first embodiment, and therefore, the duplicated description will be omitted.
[0097]
When the selector 10 of the scan path test flip-flops XX1 to XXn, YY1 to YYn, and ZZ1 to ZZn is in the shift mode, a low level (Lo) is input to the terminal TI in the scan path test flip-flop XX1. Since no data is input to the data input terminal D, the EX-OR circuit 38 outputs data “0” from the terminal TO. Similarly, the scan path test flip-flops XX2 to XXn also output data “0” from the terminal TO.
[0098]
When the selector 10 of the scan path test flip-flops XX1 to XXn, YY1 to YYn, and ZZ1 to ZZn is switched to the normal mode, as described in the first embodiment, the high-speed scan data set in the combination circuit 7 The high-speed scan data set in the combination circuit 8 is taken in by the scan path test flip-flops YY1 to YYn via the gate in the combination circuit 7, The signals are taken into the flip-flops Z1 to Zn.
[0099]
Here, for example, when data of “0” is input to the scan path test flip-flop YY1 from the data input terminal D (that is, the combinational circuit 7), data of “0” is input to the terminal TI. The EX-OR circuit 38 in the scan path test flip-flop YY1 outputs data “0” from the terminal TO. When data of, for example, "1" is input to the scan path test flip-flop YY2 from the data input terminal D, data of "0" is input to the terminal TI. EX-OR circuit 38 outputs the data of “1” from the terminal TO.
[0100]
Similarly, the scan path test flip-flops YY3 to YYn-m take the exclusive OR of the data output from the terminal TO of the preceding scan path test flip-flop and the data input from the data input terminal D. From the terminal TO.
[0101]
Therefore, when the data output from the terminal TO of the scan path test flip-flop YYn-m is “0”, the number of “1” data output from the combinational circuit 7 is an even number. When the data output from the terminal TO of the campus test flip-flop YYn-m is “1”, the number of “1” data output from the combinational circuit 7 is an odd number. The same applies to the scan path test flip-flops ZZ1 to ZZn.
[0102]
Therefore, when the data output from the output terminals 37A and 37B differs from the expected value obtained in advance, it can be determined that a failure has occurred in the odd number of gates in the combinational circuits 7 and 8.
[0103]
As described above, according to the fourth embodiment, the EX-OR circuits 38 in the scan path test flip-flops XX1 to XXn, YY1 to YYn, and ZZ1 to ZZn output data from the EX-OR circuit 38 in the preceding stage. And the data output from the combinational circuits 7 and 8 are exclusive-ORed, so that the failure of the combinational circuits 7 and 8 can be detected early as in the second embodiment. Further, the failure detection rate of the scan path test can be increased.
[0104]
Embodiment 5 FIG.
FIG. 8 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to Embodiment 5 of the present invention. The semiconductor integrated circuit shown in FIG. 8 is different from the semiconductor integrated circuit shown in FIG. 1 in that scan path test flip-flops X1 to Xn, Y1 to Yn, and Z1 to Zn are connected to scan path test flip-flops AX1 to AX1. AXn, AY1 to AYn and AZ1 to AZn.
[0105]
Since the other configuration is the same as that shown in FIG. 1, the same components are denoted by the same reference numerals, and redundant description will be omitted.
[0106]
FIG. 9 is a circuit diagram showing a configuration of the scan path test flip-flops AX1 to AXn, AY1 to AYn, and AZ1 to AZn. As shown in FIG. 9, in the scan path test flip-flops AX1 to AXn, AY1 to AYn and AZ1 to AZn, one inverter circuit 41 and two transfer gates 42 are connected to the data input terminal D of the flip-flop circuit 44. , 43 are added.
[0107]
Next, the switching operation of the selector circuits of the scan path test flip-flops AX1 to AXn, AY1 to AYn and AZ1 to AZn will be described.
When the switching control signal input from the scan path test mode switching terminal M is in the shift mode (Hi), the selector circuit turns off the transfer gate 42 and turns on the transfer gate 43, so that the input from the data input terminal SI The selected high-speed scan data is selected, and the high-speed scan data is taken into the flip-flop circuit 44. On the other hand, when the switching control signal input from the scan path test mode switching terminal M is in the normal mode (Lo), the transfer gate 42 is turned on and the transfer gate 43 is turned off. Is selected, and the normal data is taken into the flip-flop circuit 44.
[0108]
As described above, in the fifth embodiment, the selector circuit of the scan path test flip-flops AX1 to AXn, AY1 to AYn, and AZ1 to AZn is formed by one inverter circuit 41 and two transfer gates 42 and 43. With the configuration, the circuit scale (overhead) and power consumption of the scan path test flip-flops AX1 to AXn, AY1 to AYn, and AZ1 to AZn can be reduced.
[0109]
That is, in general, the selector circuit is composed of two AND circuits, one OR circuit, and one inverter circuit, and requires 14 transistors. However, the scan path test flip-flops AX1 to AXn, Each of the selector circuits AY1 to AYn and AZ1 to AZn is composed of one inverter circuit 41 and two transfer gates 42 and 43, and one transfer gate can be composed of two transistors. Transistors.
[0110]
【The invention's effect】
As described above, according to the first aspect of the present invention, Normal mode A high-speed clock signal circuit that generates a high-speed clock signal with a half cycle of the clock signal at the time, and random data based on scan data used for a scan path test, and a high-speed clock signal generated by the high-speed clock signal circuit A high-speed data generation circuit for generating high-speed scan data in which scan data and random data alternately appear at a period of, and configured to perform a scan path test using the high-speed scan data generated by the high-speed data generation circuit. Therefore, the scan path test can be performed in a short time, the length of the test pattern of the scan data can be shortened, and the cost required for the test can be reduced.
[0111]
According to the invention described in claim 2, Normal mode A high-speed clock signal circuit that generates a high-speed clock signal with a half cycle of the clock signal at the time, and a high-speed clock signal generated by the high-speed clock signal circuit while generating random data based on scan data used for a scan path test A high-speed data generation circuit that generates high-speed scan data in which scan data and random data alternately appear in a cycle of: a semiconductor integrated circuit is divided into a plurality of functional module circuits for each functional module; Are configured to perform a scan path test independently of each other in parallel with the high-speed scan data generated by the high-speed data generation circuit, so that the pattern length of the test pattern of the scan data can be shortened. Quick scan path test Ukoto it is, an effect that also reduces cost required for testing.
[0112]
According to the third aspect of the present invention, the high-speed data generation circuit shifts the scan data by one bit and generates an exclusive OR of the data shifted by one bit and the scan data to generate random data. Circuit and Input to clock input terminal It is composed of a selector circuit that alternately selects scan data and random data based on the high / low of the clock signal to generate high-speed scan data, so that high-speed scan data with high randomness can be generated. This has the effect of increasing the objectivity of high-speed scan data and increasing the failure detection rate of the scan path test.
[0113]
According to the fourth aspect of the present invention, a high-speed data generation circuit Is , High-speed clock generator for high-speed scan data By Generate Is Flip-flop circuit synchronized with the high-speed clock signal It is configured to include Therefore, it is possible to prevent the racing between the high-speed clock signal and the high-speed scan data during the scan path test.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining a scan path test operation of the semiconductor integrated circuit according to the first embodiment of the present invention;
FIG. 3 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention;
FIG. 4 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration example of a PN pattern generation circuit.
FIG. 6 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.
FIG. 7 is a circuit diagram showing a configuration of a scan path test flip-flop of a semiconductor integrated circuit according to a fourth embodiment of the present invention.
FIG. 8 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention.
FIG. 9 is a circuit diagram showing a configuration of a scan path test flip-flop of a semiconductor integrated circuit according to a fifth embodiment of the present invention.
FIG. 10 is a circuit diagram showing a configuration of a conventional semiconductor integrated circuit.
FIG. 11 is a circuit diagram showing a configuration of a scan path test flip-flop in a conventional semiconductor integrated circuit.
FIG. 12 is a timing chart for explaining a scan path test operation of a conventional semiconductor integrated circuit.
[Explanation of symbols]
X1 to Xn, Y1 to Yn, Z1 to Zn Scan path test flip-flop (scan path test storage element)
XX1 to XXn, YY1 to YYn, ZZ1 to ZZn Scan path test flip-flop (scan path test storage element)
AX1 to AXn, AY1 to AYn, AZ1 to AZn Scan path test flip-flops (scan path test storage elements)
7,8 combination circuit
12, 13, 35, 36, 39, 40 Function module circuit
16, 17 flip-flop circuit (random data generation circuit)
18 EX-OR circuit (random data generation circuit)
19 Selector circuit
20 flip-flop circuit
21 High-speed clock generation circuit
22,30 High-speed data generation circuit
23 EX-OR circuit (Exclusive OR circuit)
24 EX-OR circuit (Exclusive OR circuit)
27 PN pattern generation circuit (pseudo random data generation circuit)
38 EX-OR circuit (Exclusive OR circuit)
42, 43 transfer gate

Claims (4)

When performing a scan path test of a combinational circuit, in a semiconductor integrated circuit having a plurality of scan path test storage elements configured to operate as a flip-flop in a normal mode and to operate as a shift register in a shift mode,
A high-speed clock generation circuit that generates a high-speed clock signal having a half cycle of the clock signal in the normal mode ;
A high-speed scan that generates random data based on scan data used for the scan path test and causes the scan data and the random data to appear alternately at a cycle of the high-speed clock signal generated by the high-speed clock generation circuit. A high-speed data generation circuit for generating data;
A semiconductor integrated circuit, wherein the scan path test is performed using the high-speed scan data generated by the high-speed data generation circuit. When performing a scan path test of a combinational circuit, in a semiconductor integrated circuit having a plurality of scan path test storage elements configured to operate as a flip-flop in a normal mode and to operate as a shift register in a shift mode,
A high-speed clock generation circuit that generates a high-speed clock signal having a half cycle of the clock signal in the normal mode ;
A high-speed scan that generates random data based on scan data used for the scan path test and causes the scan data and the random data to appear alternately at a cycle of the high-speed clock signal generated by the high-speed clock generation circuit. A high-speed data generation circuit for generating data;
The semiconductor integrated circuit is divided into a plurality of functional module circuits for each functional module,
A semiconductor integrated circuit, wherein the scan path test is performed using the high-speed scan data generated by the high-speed data generation circuit independently of each of the functional module circuits in parallel. A high-speed data generation circuit that shifts the scan data by one bit and generates an exclusive OR of the data shifted by one bit and the scan data to generate random data;
3. The selector circuit according to claim 1, further comprising a selector circuit that alternately selects scan data and random data based on a high / low of a clock signal input to a clock input terminal to generate high-speed scan data. Semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 3, wherein the high-speed data generation circuit includes a flip-flop circuit for synchronizing the high-speed scan data with the high-speed clock signal generated by the high-speed clock generation circuit.

Images