JP3575677B2 - Video signal processing device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a video signal processing device in an image display device (for example, a liquid crystal display, a plasma display, or the like) using fixed display pixels, and more specifically, to two-phase processing of a video signal input to the image display device. The present invention relates to a video signal processing device that performs A / D conversion on the video signal.
[0002]
[Prior art]
In recent years, as the resolution of a computer serving as an image signal source increases, the corresponding clock frequency of an image display device tends to increase significantly. However, in order to make the image display device compatible with the increased clock frequency, a digital signal processing device that performs processing after A / D conversion of an input video signal operates in response to a high-speed clock. There is a need. Therefore, problems such as an increase in power consumption of the image display device and an increase in cost arise.
[0003]
Therefore, the conventional image display device reduces the clock frequency by half by performing two-phase processing in the A / D converter. With this configuration, the digital signal processing device provided downstream of the A / D converter does not need to perform an operation corresponding to a high-speed clock. Of course, the same effect can be obtained whether the two-phase processing performed in the A / D converter is a four-phase processing or a six-phase processing.
[0004]
There are various types of A / D converters that perform two-phase processing. For example, there are products of model numbers such as CXA3026AQ (manufactured by Sony) and AD9054BST (manufactured by Analog Devices).
[0005]
FIG. 17 is a block diagram showing a configuration of a conventional video signal processing device that performs two-phase processing in an A / D converter. 17, the video signal processing apparatus receives a reference signal 9 and a video signal 24 from an image signal source, performs two-phase processing, and outputs first-phase data 10 and second-phase data 11. A / D converter 3. The operation of the video signal processing device as described above will be described below with reference to FIGS.
[0006]
FIG. 18 is an operation explanatory diagram of the A / D converter 3 in FIG. In FIG. 18, a to e represent video data included in the video signal 24 within the effective video period. Each of the circles, diamonds, rectangles, and triangles with the inside filled therein represents pedestal level data in the back porch, specifically, black data. Further, t1 to t10 represent a certain time. Note that the arrows schematically represent the two-phase processing of the A / D converter 3.
[0007]
In FIG. 18, the video signal 24 includes a back porch and video data. The back porch is included from time t1 (or earlier) to time t5, and the video signal data is included after time t5. Therefore, the video signal 24 is configured such that the leading edge of the signal including the video data is located at the end of the back porch.
[0008]
Here, the digital data output from the A / D converter 3 is determined by the phase relationship with the video signal 24 at that time, starting from the pulse of the reference signal 9 input to the A / D converter 3. . Normally, a horizontal synchronization signal of an image signal source is used as the reference signal 9.
[0009]
First, the A / D converter 3 starts two-phase processing from time t1 with the first-phase data 10 as a starting point for a pulse of the reference signal 9. As shown in FIG. 18, at time t3, the black data represented by a circle whose inside is painted out is output from the A / D converter 3 as the first phase data 10. At the same time, the black data represented by the diamond is output from the A / D converter 3 as the second phase data 11. Thereafter, similarly at time t5, black data represented by squares and triangles is output.
[0010]
Therefore, when the number of data in the back porch from the leading edge of the pulse of the reference signal 9 to immediately before the leading data a of the video signal 24 is an even number, the leading data a is transmitted from the A / D converter 3 to the first phase. Output as data 10. When the number of data in the back porch is odd, the leading data a is output from the A / D converter 3 as the second phase data 11.
[0011]
[Problems to be solved by the invention]
However, a display having a fixed display pixel, such as a liquid crystal display or a plasma display using the above-described conventional configuration, may have a missing dot of one dot when displaying video data. Such a problem will be described with reference to FIGS. 19 and 20.
[0012]
FIG. 19 is a schematic diagram illustrating the arrangement of output data and the display on the display when the video data a shown in FIG. 18 is output as first-phase data from the A / D converter. FIG. 20A is a schematic diagram illustrating the arrangement of output data and the display on the display when the video data a shown in FIG. 18 is output from the A / D converter as second-phase data. FIG. 20B is a schematic diagram illustrating display on a display different from that of FIG. 20A when the data arrangement is the same as that of FIG.
[0013]
In FIGS. 19 and 20, a to t represent data included in a video signal of an image signal source existing on an arbitrary scanning line during an effective video period. The data in the square frame indicates that the data is displayed on the display, and the data outside the frame indicates that the data is not displayed on the display.
[0014]
As shown in FIG. 19, when the first data a of the video signal (data displayed on the left end on the display) a is present in the first phase data 10 of the A / D converter, the display is performed on a display having fixed display pixels. Displays all video data from a to t. On the other hand, as shown in FIGS. 20A and 20B, when the first data a exists in the second phase data 11, either the rightmost video data t or the leftmost video data a is displayed on the display. The problem of not being displayed arises. Such a problem is caused by the fact that a digital signal processing device provided at the subsequent stage of the A / D converter 3 performs processing at a half frequency with respect to the dot clock frequency of the image signal source. This is caused by being able to move only in pixel units.
[0015]
As described above, in the conventional video signal processing device, when the first data a is present in the second phase data 11, the video data is deleted in a state where one dot is missing as shown in FIG. Is displayed, the video data a to t cannot be displayed simultaneously as shown in FIG.
[0016]
Therefore, an object of the present invention is to display all pixels on a display even when the first phase of output data does not include the head of video data while using an A / D converter that performs two-phase processing. An object of the present invention is to provide a video signal processing device capable of causing the video signal processing device to perform the processing.
[0017]
Means for Solving the Problems and Effects of the Invention
A first invention is a video signal processing apparatus for displaying pixels included in a video signal input from an image signal source on a display without missing,
A clock delay circuit to which a reference signal is input, the reference signal being delayed by an odd clock and output;
A multiplexer that selects and outputs one of a reference signal and an output signal from a clock delay circuit;
An A / D converter that converts a video signal into a digital signal based on an output signal from the multiplexer and outputs two phases as first phase data and second phase data;
A first leading edge detection circuit that detects a leading edge of the effective video signal area in the first phase data and outputs a corresponding detection signal;
A second leading edge detection circuit that detects a leading edge of the effective video signal area in the second phase data and outputs a corresponding detection signal;
A first back porch detection circuit for detecting a first back porch period using an output signal from the multiplexer as a start point and a detection signal output from the first leading edge detection circuit as an end point;
A second back porch detection circuit for detecting a second back porch period using the output signal from the multiplexer as a starting point and the detection signal output from the second leading edge detection circuit as an end point;
Comparing the first back porch period and the second back porch period, if the first back porch period is longer than the second back porch period, the head data of the effective video signal area in the video signal is A comparator that outputs a signal that controls the multiplexer to select and output a signal that is determined not to be included in the first phase data.
[0018]
As described above, according to the first aspect, even when the head of the video data does not normally exist in the output data of the first phase, by using the signal shifted by one clock phase as a reference, All pixels can be displayed on the display.
[0019]
The second invention is an invention dependent on the first invention,
The first back porch detection circuit detects the first back porch period using the number of clocks in the video signal,
The second back porch detection circuit detects the second back porch period using the number of clocks in the video signal.
[0020]
As described above, according to the second aspect, accurate counting can be performed by using the number of dot clocks included in the image signal source.
[0021]
A third invention is an invention dependent on the first invention,
A first minimum value holding circuit for newly inputting the minimum value of the first back porch period output from the first back porch detection circuit to the comparator as the first back porch period;
A second minimum value holding circuit that newly inputs a minimum value of the second back porch period output from the second back porch detection circuit to the comparator as a second back porch period.
[0022]
As described above, according to the third aspect, it is possible to easily cope with a case where the video signal of the image signal source is a moving image in which the back porch period constantly changes, and the entire image is reliably displayed on the display. A signal can be displayed.
[0023]
A fourth invention is a video signal processing device for displaying pixels included in a video signal input from an image signal source on a display without missing,
A clock delay circuit to which a reference signal is input, the reference signal being delayed by an odd clock and output;
A multiplexer that selects and outputs one of a reference signal and an output signal from a clock delay circuit;
An A / D converter that converts a video signal into a digital signal based on an output signal from the multiplexer and outputs two phases as first phase data and second phase data;
A leading edge detection circuit that detects a leading edge of an effective video signal area in one of predetermined first-phase data or second-phase data, and outputs a corresponding detection signal;
A back porch detection circuit for detecting a back porch period with an output signal from the multiplexer as a start point and a detection signal output from the leading edge detection circuit as an end point;
A storage unit to which a back porch period is input and which stores and outputs the reference signal and the output signal from the clock delay circuit which are selected and output by the multiplexer, respectively;
A control signal is output from the storage unit to control the switching of the signal selected and output by the multiplexer so that the back porch periods corresponding to the signals selected and output by the multiplexer are output from the storage unit. Respectively When the corresponding back porch period is output, each is compared, and if the back porch period corresponding to the reference signal is equal to or smaller than the back porch period corresponding to the output signal from the clock delay circuit, the image is displayed. A comparator that determines that the first data of the effective video signal area in the signal is included in the first phase data and outputs the control signal again.
[0024]
As described above, according to the fourth aspect, the output back porch period is stored and output in each state, and the comparator performs the discriminating operation based on the output data. All video signals can be displayed on the display.
[0025]
According to the fourth aspect, only one of the first-phase data and the second-phase data output from the A / D converter is used as a detection signal, and neither of them is used as a detection signal. It is possible to further reduce the substrate wiring area and the like in the video signal processing device.
[0026]
A fifth invention is an invention according to the fourth invention, wherein the back porch detection circuit detects the back porch period using the number of clocks in the video signal.
[0027]
As described above, according to the fifth aspect, accurate counting can be performed by using the number of dot clocks included in the image signal source.
[0028]
A sixth invention is a video signal processing device for displaying pixels included in a video signal input from an image signal source on a display without missing,
A clock delay circuit to which a reference signal is input, the reference signal being delayed by an odd clock and output;
A multiplexer that selects and outputs one of a reference signal and an output signal from a clock delay circuit;
An A / D converter that converts a video signal into a digital signal based on an output signal from the multiplexer and outputs two phases as first phase data and second phase data;
A leading edge detection circuit that detects a leading edge of the effective video signal area in the first phase data and outputs a corresponding detection signal;
A trailing edge detection circuit that detects the trailing edge of the effective video signal area in the second phase data and outputs a corresponding detection signal;
The effective image period is defined by using the detection signal output from the leading edge detection circuit as a start point and the detection signal output from the trailing edge detection circuit as an end point. Pixels included in An effective video period detection circuit for detecting
1/2 value of input horizontal resolution and effective video period Number of pixels detected by the detection circuit And the value of 1/2 of the number of horizontal resolutions is the effective video period Number of pixels detected by the detection circuit If it is larger than the threshold value, it is determined that the first data of the effective video signal area in the video signal is not included in the first phase data, and a signal for controlling the multiplexer to select and output the output signal is output. And a comparator.
[0029]
As described above, according to the sixth aspect, the number of pixels detected by the effective video period detection circuit to which the detection pulses detected by the leading edge detection circuit and the rear edge detection circuit are input, and the present video signal processing device １ ／ of the number of horizontal resolutions of the image signal sources connected to the comparators are input to the comparators to perform the discriminating operation, whereby all video signals can be reliably displayed on the display.
[0030]
A seventh invention is the invention according to the sixth invention, wherein the effective video period detection circuit detects an effective video period using the number of clocks in a video signal.
[0031]
As described above, according to the seventh aspect, accurate counting can be performed by using the number of dot clocks included in the image signal source.
[0032]
An eighth invention is a video signal processing device for displaying pixels included in a video signal input from an image signal source on a display without missing,
A clock delay circuit to which a reference signal is input, the reference signal being delayed by an odd clock and output;
A multiplexer that selects and outputs one of a reference signal and an output signal from a clock delay circuit;
An A / D converter that converts a video signal into a digital signal based on an output signal from the multiplexer and outputs two phases as first phase data and second phase data;
A leading edge detection circuit that detects a leading edge of the effective video signal area in the second phase data and outputs a corresponding detection signal;
A trailing edge detection circuit that detects the trailing edge of the effective video signal area in the first phase data and outputs a corresponding detection signal;
The effective image period is defined by using the detection signal output from the leading edge detection circuit as a start point and the detection signal output from the trailing edge detection circuit as an end point. Pixels included in An effective video period detection circuit for detecting
1/2 value of input horizontal resolution and effective video period Number of pixels detected by the detection circuit And the value of 1/2 of the number of horizontal resolutions is the effective video period Number of pixels detected by the detection circuit If it is smaller than the first phase data, it is determined that the first data of the effective video signal area in the video signal is not included in the first phase data, and a signal for controlling the multiplexer to switch the output signal is output. And a comparator.
[0033]
As described above, according to the eighth aspect, the detection pulses detected by the leading edge detection circuit and the trailing edge detection circuit are input regardless of which of the data included in the video signal is ON or OFF. The configuration in which the number of pixels detected by the effective video period detection circuit and 1/2 of the number of horizontal resolutions of the image signal source connected to the video signal processing device are input to the comparator and the discriminating operation is performed, so that the display can be reliably performed. All video signals can be displayed on top.
[0034]
A ninth invention is the invention according to the eighth invention, wherein the effective video period detection circuit detects the effective video period using the number of clocks in the video signal.
[0035]
As described above, according to the ninth aspect, accurate counting can be performed by using the number of dot clocks included in the image signal source.
[0036]
A tenth invention is a video signal processing device for displaying pixels included in a video signal input from an image signal source on a display without missing,
A clock delay circuit to which a reference signal is input, the reference signal being delayed by an odd clock and output;
A multiplexer that selects and outputs one of a reference signal and an output signal from a clock delay circuit;
An A / D converter that converts a video signal into a digital signal based on an output signal from the multiplexer and outputs two phases as first phase data and second phase data;
A first leading edge detection circuit that detects a leading edge of the effective video signal area in the first phase data and outputs a corresponding detection signal;
A second leading edge detection circuit that detects a leading edge of the effective video signal area in the second phase data and outputs a corresponding detection signal;
A first trailing edge detection circuit that detects the trailing edge of the effective video signal area in the second phase data and outputs a corresponding detection signal;
A second trailing edge detection circuit that detects the trailing edge of the effective video signal area in the first phase data and outputs a corresponding detection signal;
First effective video period detection for detecting a first effective video period using a detection signal output from a first leading edge detection circuit as a starting point and a detection signal output from the first trailing edge detection circuit as an end point Circuit and
A second effective image period detection for detecting a second effective image period using the detection signal output from the second leading edge detection circuit as a start point and the detection signal output from the second trailing edge detection circuit as an end point Circuit and
Comparing the first valid video period and the second valid video period, if the second valid video period is longer than the first valid video period, the first data of the valid video signal area in the video signal is A comparator that outputs a signal that controls the multiplexer to select and output a signal that is determined not to be included in the first phase data.
[0037]
As described above, according to the tenth aspect, it is possible to reliably display all video signals on a display without detecting the number of horizontal resolutions of an image signal source while using a configuration for detecting an effective video period. Becomes possible.
[0038]
An eleventh invention is an invention dependent on the tenth invention,
The first effective video period detection circuit detects the first effective video period using the number of clocks in the video signal,
The second effective video period detection circuit detects the second effective video period using the number of clocks in the video signal.
[0039]
As described above, according to the eleventh aspect, accurate counting can be performed by using the number of dot clocks included in the image signal source.
[0040]
A twelfth invention is a video signal processing device for displaying pixels included in a video signal input from an image signal source on a display without dropping,
An A / D converter that converts a video signal into a digital signal based on an input reference signal and outputs two phases as first phase data and second phase data;
A clock delay circuit to which the second-phase data is input and which delays and outputs the second-phase data by an odd clock;
A first multiplexer that selects and outputs one of the first phase data and the output signal from the clock delay circuit;
A second multiplexer that selects and outputs one of the second-phase data and the first-phase data;
A first leading edge detection circuit that detects a leading edge of the effective video signal area in the first phase data and outputs a corresponding detection signal;
A second leading edge detection circuit that detects a leading edge of the effective video signal area in the second phase data and outputs a corresponding detection signal;
A first back porch detection circuit for detecting a first back porch period with a reference signal as a starting point and a detection signal output from the first leading edge detection circuit as an end point;
A second back porch detection circuit for detecting a second back porch period using the reference signal as a starting point and the detection signal output from the second leading edge detection circuit as an end point;
Comparing the first back porch period and the second back porch period, if the first back porch period is longer than the second back porch period, the head data of the effective video signal area in the video signal is A comparator that outputs a signal that determines that the signal is not included in the first-phase data and controls the first and second multiplexers to simultaneously switch signals that are selected and output;
At the beginning of activation, the first multiplexer selects and outputs the first phase data, and the second multiplexer selects and outputs the second phase data.
[0041]
As described above, according to the twelfth aspect, it is possible to easily cope with an increase in the resolution of an image signal source, and it is possible to reliably display all video signals on a display.
[0042]
A thirteenth invention is an invention according to the twelfth invention,
The first back porch detection circuit detects the first back porch period using the number of clocks in the video signal,
The second back porch detection circuit detects the second back porch period using the number of clocks in the video signal.
[0043]
As described above, according to the thirteenth aspect, accurate counting can be performed by using the number of dot clocks included in the image signal source.
[0044]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
FIG. 1 is a block diagram showing the configuration of the video signal processing device according to the first embodiment of the present invention. In FIG. 1, the present video signal processing apparatus receives a one-clock delay circuit 1 that receives a reference signal 9 and outputs a signal delayed by one clock, and receives an output signal from the one-clock delay circuit 1 and the reference signal 9. A multiplexer 2, an A / D converter 3 to which the output signal from the multiplexer 2 and the video signal 24 are input and perform two-phase processing, and a first and a second detector for detecting the leading edge of the output signal from the A / D converter 3. First and second back porches to which second leading edge detection circuits 4 and 5 and signals from corresponding first and second leading edge detection circuits 4 and 5 and an output signal from multiplexer 2 are input. Detection circuits 6 and 7 and a comparator 8 which receives signals from the first and second back porch detection circuits 6 and 7, respectively, and outputs a control signal 12 to the multiplexer 2 are provided. The operation of the video signal processing device configured as described above will be described below.
[0045]
In FIG. 1, a reference signal 9 of an image signal source connected to the video signal processing apparatus is input to a multiplexer 2 and also to a one-clock delay circuit 1. As the reference signal 9, a horizontal synchronizing signal of an image signal source is generally used, but is not necessarily limited to this.
[0046]
The one-clock delay circuit 1 delays the input reference signal 9 by one clock and inputs the same to the multiplexer 2. Specifically, the one-clock delay circuit 1 delays the reference signal 9 by the number of dot clocks of the image signal source, that is, by one pixel.
[0047]
The multiplexer 2 selects and outputs one of the input reference signal 9 and the output signal from the one-clock delay circuit 1. Here, when the control signal 12 is input from the comparator 8, the multiplexer 2 performs an operation of switching the output signal from one input signal selected so far to the other input signal. For example, it is assumed that the multiplexer 2 selects and outputs the reference signal 9 from the input reference signal 9 and the output signal from the one-clock delay circuit 1. Thereafter, when the control signal 12 is input from the comparator 8, the multiplexer 2 stops outputting the reference signal 9 selected so far and newly selects the output signal from the one-clock delay circuit 1. An operation to switch to output is performed. It is assumed that the multiplexer 2 selects and outputs the reference signal 9 when the present video signal processing device is started. The output signal from the multiplexer 2 is input to the A / D converter 3.
[0048]
The A / D converter 3 receives the video signal 24 and the output signal from the multiplexer 2 and performs two-phase processing. Specifically, the A / D converter 3 performs A / D conversion on the video signal 24 based on the signal output from the multiplexer 2 and then performs two-phase conversion to perform the first-phase data 10 and the second-phase data. 11 are output simultaneously. These digital data are transmitted to a digital signal processing device (not shown) provided at the subsequent stage of the A / D converter 3, where they are subjected to signal processing and then projected on a display.
[0049]
Also, the digital data output from the A / D converter 3, that is, the first phase data 10 and the second phase data 11, are input to the corresponding first and second leading edge detection circuits 4 and 5. In the corresponding input first-phase data 10 and second-phase data 11, first and second leading edge detection circuits 4 and 5 determine the effective video signal of video signal 24 input to A / D converter 3. Detect the leading edge of the region. The detection of the leading edge position of the effective video signal area utilizes the fact that the black level is used during the blanking period from the reference signal 9 to the effective video area in a normal image signal source. In other words, the leading edge position of the effective video signal area can be easily detected by detecting a period during which the video signal first rises from the reference signal 9 as a starting point.
[0050]
Here, if the leading data of the effective video signal area is at the pedestal level, the leading edge of the effective video signal area cannot be detected accurately. However, in such a case, the head data of the effective video signal area always lacks one or more pixels. For this reason, the above-described problem that all the data of the image signal source connected to the video signal processing device cannot be displayed on the display having the fixed display pixels does not occur.
[0051]
When the leading edge is detected in this manner, the first and second leading edge detecting circuits 4 and 5 input the leading edge to the corresponding first and second back porch detecting circuits 6 and 7 in the form of a pulse signal. I do. The first and second back porch detection circuits 6 and 7 form a signal between the signal output from the multiplexer 2 and the leading edge of the effective video signal area detected by the first and second leading edge detection circuits 4 and 5. The intervening back porch period is detected. Typically, the first and second leading edge detection circuits 4 and 5 include a counter circuit and count how many times the back porch period is the number of dot clocks of the image signal source. In this way, the first and second leading edge detection circuits 4 and 5 can accurately count by using the number of dot clocks of the image signal source.
[0052]
Here, as described above, when the leading data of the effective video signal area is at the pedestal level, the leading edge of the effective video signal area detected by the first and second leading edge detection circuits 4 and 5 is: It does not always coincide with the leading edge of the effective video signal area. Therefore, the back porch period is defined as a period starting from the leading edge of the signal output from the multiplexer 2 and ending at the leading data position other than the black level in the effective video signal area.
[0053]
The back porch periods detected by the first and second back porch detection circuits 6 and 7 are input to the comparator 8, respectively. The comparator 8 outputs a control signal 12 based on the result obtained according to the discrimination logic described later. When the control signal 12 is input, the multiplexer 2 performs an operation of switching the output signal from one of the output signal from the one-clock delay circuit 1 and the reference signal 9 to the other. Of course, when the comparator 8 does not output the control signal 12 based on the result obtained according to the discrimination logic described later, the multiplexer 2 does not perform the switching operation.
[0054]
Next, the determination operation in the comparator 8 will be described in detail with reference to FIG. FIG. 2 is a time chart showing a relationship between reference signal 9 and output signals from first and second leading edge detection circuits 4 and 5. Further, FIG. 2A shows a case where the leading data (the leftmost data on the display) in the effective video signal area is output from the first phase of the A / D converter 3. FIG. 2B shows a case where the head data is output from the second phase of the A / D converter 3.
[0055]
Here, as described above, the back porch period is detected from the pulse position of the signal output from the multiplexer 2 to the start data in the effective video signal area. The number of back porches is a value obtained by counting the number of dots (the number of clocks) in the back porch period. In FIG. 2, the number of back porches in the output signal from the leading edge detection circuit 4 is represented as BP1, and the number of back porches in the output signal from the leading edge detection circuit 5 is represented as BP2.
[0056]
In FIG. 2A, the first data is included in the first phase data 10 as described above. Therefore, in the output signal from the leading edge detection circuit 4 to which the first-phase data 10 is input, the back porch number BP1 always has the relationship shown in the following equation (1) with the back porch number BP2.
BP1 ≦ BP2 (1)
[0057]
This is because BP1 and BP2 match if the video signal data next to the head data, that is, the first data in the second phase data 11 is not black level data, and BP2 is BP1 if the data is black level data. Because it will always be larger than
[0058]
The comparator 8 does not output the control signal 12 to the multiplexer 2 when the above equation (1) is satisfied. Therefore, the multiplexer 2 outputs the reference signal 9 without performing the switching operation. When the reference signal 9 is input, the A / D converter 3 can maintain a state where the leading data in the effective video signal area is always output from the first phase data. Therefore, once the present video signal processing circuit can maintain the state in which the first data is always output from the first phase data, there is basically no need to operate thereafter.
[0059]
On the other hand, in FIG. 2B, the first data in the effective video signal area is included in the second phase data 11. Therefore, in the output signal from the leading edge detection circuit 5 to which the second-phase data 11 is input, the back porch number BP2 always has the relationship of the following equation (2) with the back porch number BP1.
BP1> BP2 (2)
[0060]
This is because the first data is included in the second-phase data 11, so that the first-phase data 10 having the same phase is naturally black data, and the back porch number BP2 is always smaller than the back porch number BP1.
[0061]
The comparator 8 outputs the control signal 12 to the multiplexer 2 so that the multiplexer 2 selects the signal from the one-clock delay circuit 1 when the above-mentioned equation (2) is satisfied. The multiplexer 2 receives the control signal 12 and switches the output signal. Specifically, the multiplexer 2 selects a signal from the one-clock delay circuit 1 and outputs the signal to the A / D converter 3. When the signal from the one-clock delay circuit 1 is selected, the A / D converter 3 uses the signal shifted by one clock phase as a reference. The state in which the leading data is output can be held. Because, as described above, when the first data in the effective video signal area is output from the first phase data, the comparator 8 does not output the control signal 12 to the multiplexer 2 and the multiplexer 2 This is because the output signal is not switched. Therefore, as described above, the present video signal processing circuit basically does not need to be operated after the first data can be maintained in a state where the first data is always output.
[0062]
However, even if the head data in the effective video signal area is output from the second phase data while the video signal processing circuit is operated, the effective video signal area always starts from the first phase data. Can be held in a state in which the first data of is output. This is because the comparator 8 performs the above-described determination operation and outputs the control signal 12 to the multiplexer 2, so that the multiplexer 2 newly switches the output signal to the reference signal 9.
[0063]
As described above, the video signal processing apparatus according to the present embodiment normally uses a signal shifted by one clock phase as a reference even when the first phase output data does not include the head of video data. Thus, all the pixels can be displayed on the display.
[0064]
Note that the video signal processing device according to the present embodiment can be configured by replacing the first and second leading edge detection circuits 4 and 5 with first and second trailing edge detection circuits, respectively. In the case of such a configuration, the first and second back porch detection circuits 6 and 7 operate to detect a period obtained by adding an effective video signal period to the back porch period. With such a configuration, the video signal processing device according to the present embodiment can perform the same operation.
[0065]
Further, the one-clock delay circuit 1 in the present video signal processing device may be a three-clock delay circuit or a five-clock delay circuit. That is, the one-clock delay circuit 1 may be any circuit that delays the reference signal 9 by an odd clock. Further, in the present embodiment, the case where the A / D converter performing the two-phase processing is used has been described, but the same operation is performed even if the A / D converter performing the four-phase processing or the six-phase processing is used. Can be easily performed.
[0066]
(Second embodiment)
FIG. 3 is a block diagram showing the configuration of the video signal processing device according to the second embodiment of the present invention. In FIG. 3, the present video signal processing device has substantially the same configuration as the video signal processing device according to the first embodiment described above. However, in the present video signal processing device, the second leading edge detection circuit 5 and the second back porch detection circuit 7 in FIG. 1 are omitted, and the first leading edge detection circuit 4 in FIG. The second embodiment differs from the video signal processing apparatus according to the first embodiment in that the first back porch detection circuit 6 is replaced with a back porch detection circuit 60 and a storage unit 13 is provided. Therefore, in the present video signal processing device, the same components as those of the video signal processing device according to the first embodiment are denoted by the same reference numerals and description thereof is omitted. It should be noted that the comparator 15 has a different signal from that of the comparator 8, and thus is given a different symbol.
[0067]
In FIG. 3, in an initial state, the multiplexer 2 selects the reference signal 9 and inputs it to the A / D converter 3 as it is. As described above, the A / D converter 3 performs A / D conversion on the video signal 24 based on the signal output from the multiplexer 2, performs two-phase conversion, and performs first-phase data 10 and second-phase data. 11 respectively. The first phase data 10 is input to the leading edge detection circuit 40. The leading edge detection circuit 40 detects the leading edge of the effective video signal area in the video signal 24. The detection result is input to the back porch detection circuit 60. The back porch detection circuit 60 is a back porch period between the leading edge of the signal output from the multiplexer 2 (here, the reference signal 9) and the leading edge of the effective video signal area output from the leading edge detection circuit 40. Is detected. The detected back porch period is input to the storage unit 13. The storage unit 13 stores the period, and continuously outputs the period to the comparator 15 at a certain timing.
[0068]
When the comparator 15 detects that only the period is input, the comparator 15 outputs the control signal 12 to the multiplexer 2 so as to switch to the output signal from the one-clock delay circuit 1. The reason why the comparator 15 performs such an operation is that after storing the back porch period starting from the leading edge of the reference signal 9 in the storage unit 13, the leading edge of the output signal from the one-clock delay circuit 1 is further stored. This is for inputting the back porch period as the starting point to the storage unit 13.
[0069]
The multiplexer 2 switches to an output signal from the one-clock delay circuit 1 according to the control signal 12 from the comparator 15 and outputs the signal to the A / D converter 3. The A / D converter 3 performs two-phase conversion after A / D converting the video signal 24 with reference to the input signal. The leading edge detection circuit 40 detects the leading edge of the effective video signal area in the video signal 24 as described above. Further, the back porch detection circuit 60 detects the back porch period as described above. The detected back porch period is input to the storage unit 13. The storage unit 13 inputs the input back porch period and the stored back porch period to the comparator 15. The input back porch period may be temporarily stored by the storage unit 13.
[0070]
Comparator Fifteen Detects that the above two back porch periods have been input, determines whether or not to output the control signal 12 based on the result obtained according to the determination logic described later. When the control signal 12 is input, the multiplexer 2 switches the output signal from one of the output signal from the one-clock delay circuit 1 and the reference signal 9 to the other.
[0071]
Next, the comparator described above Fifteen Will be described in detail with reference to FIGS. FIG. 4 is a time chart showing the relationship between the reference signal 9 and the output signal from the storage unit 13. FIG. 4A shows a case where the head data (the leftmost data on the display) in the effective video signal area is output from the first phase of the A / D converter 3. FIG. 4B shows a case where the head data is output from the second phase of the A / D converter 3.
[0072]
FIG. 5 is a time chart showing a data flow when the leading data in the effective video signal area is output from the first phase of the A / D converter 3. FIG. 5A shows a case where the reference signal 9 is directly input to the A / D converter 3 without being delayed. FIG. 5B shows a case where the reference signal 9 is input to the A / D converter 3 after being delayed by one clock.
[0073]
FIG. 6 is a time chart showing the flow of data when head data is output from the second phase of A / D converter 3. FIG. 6A shows a case where the reference signal 9 is directly input to the A / D converter 3 without being delayed. FIG. 6B shows a case where the reference signal 9 is delayed by one clock and input to the A / D converter 3.
[0074]
Here, as in the first embodiment, in this embodiment, the back porch number is a value obtained by counting the number of dots (the number of clocks) in the back porch period. 4 to 6, when the reference signal 9 is directly input to the A / D converter 3 without delay, the number of back porches in the output signal from the storage unit 13 is represented as M1. When the reference signal 9 is input to the A / D converter 3 after being delayed by one clock, the number of back porches in the output signal from the storage unit 13 is represented as M2.
[0075]
In FIG. 4A, the leading edge of the output signal from the leading edge detection circuit 40 is one clock more than the reference signal 9 is input to the A / D converter 3 without being delayed. When the signal is input to the A / D converter 3 after being delayed only by one clock, it is delayed by one clock or more. More specifically, as described later, when the data following the head data in the video signal is data other than the black level (ON data), the leading edge detection when the reference signal 9 is delayed by one clock is performed. The leading edge of the output signal from circuit 40 is delayed by exactly one clock, and if the data is of a black level, further delayed. However, since the output signal from the multiplexer 2 is also delayed by one clock, the relationship between the number of back porches M1 and the number of back porches M2 can be expressed by the following equation (3).
M1 ≦ M2 (3)
[0076]
The establishment of the relationship as in the above equation (3) will be described in detail with reference to FIGS. 5 (a) and 5 (b). 5A and 5B, t1 to t7 represent time, and arrows schematically represent two-phase processing in the A / D converter 3. The filled circles and squares represent black level data in the back porch, and a to d represent video data in the effective video signal area. Further, the video data a arranged immediately after the leading edge of the video signal 24 is data other than the black level. This is because the problem that all the data cannot be displayed on the display to be solved by the present video signal processing apparatus does not occur as long as the data is of the black level.
[0077]
In FIG. 5A, the timing of the leading edge of the output signal from the multiplexer 2 matches the time t1. Therefore, the A / D converter 3 receives the video signal 24 from time t1 and starts two-phase processing. Specifically, after two data are input, the A / D converter 3 outputs two input data simultaneously in two phases until the next two data are input. Therefore, at time t3, A / D converter 3 outputs data represented by solid circles and rectangles, and outputs video data a and b at time t5. In the video signal processing device according to the present embodiment, since only the first-phase data 10 is input to the leading edge detection circuit 40, the timing of the leading edge of the output signal from the leading edge detection circuit 40 matches the time t5. I do. Therefore, M1 is the number of back porches from time t1 to time t5, that is, four. Since the video data a is not black level data, M1 is determined without depending on the arrangement of the video data.
[0078]
In FIG. 5B, since the reference signal 9 is delayed by one clock, the timing of the leading edge of the output signal from the multiplexer 2 matches the time t2. Therefore, the A / D converter 3 receives the video signal 24 from the time t2 and starts two-phase processing. At the time t4, the A / D converter 3 outputs the data represented by the filled rectangle and the video data a. At t6, video data b and c are output. In the video signal processing device according to the present embodiment, since only the first phase data 10 is input to the leading edge detection circuit 40, the timing of the leading edge of the output signal from the leading edge detection circuit 40 matches the time t6. I do. Therefore, M2 is the number of back porches from time t2 to t6, that is, four. However, it is conceivable that the video data b or subsequent data is black level data. In that case, the timing of the leading edge of the output signal from the leading edge detection circuit 40 is further after time t6. Therefore, since M2 is 4 or more, M2 is always equal to M1 or a numerical value larger than M1. As described above, it can be seen that the relationship as expressed by the above equation (3) is established.
[0079]
Next, in FIG. 4B, the leading edge of the output signal from the leading edge detection circuit 40 is smaller in the reference signal 9 than in the case where the reference signal 9 is directly input to the A / D converter 3 without being delayed. Is delayed by one clock and input to the A / D converter 3 without fail. Because, as will be described in detail later, when the first data of the video signal included in the second phase data 11 is subjected to two phase processing by a signal delayed by one clock, the first phase data 10 This is because it will be included. Therefore, the relationship between the number of back porches M1 and the number of back porches M2 can be expressed as the following equation (4).
M1> M2 (4)
[0080]
The establishment of the relationship as in the above equation (4) will be described in further detail with reference to FIGS. 6 (a) and 6 (b). 6 (a) and 6 (b), t1 to t8 represent time, and arrows schematically represent two-phase processing in the A / D converter 3. The filled circles, squares, and triangles represent black level data in the back porch, and a to d represent video data in the effective video signal area. Further, as described above, the video data a disposed immediately after the leading edge of the video signal 24 is data other than the black level.
[0081]
In FIG. 6A, the timing of the leading edge of the output signal from the multiplexer 2 coincides with the time t1. Therefore, the A / D converter 3 receives the video signal 24 from time t1 and starts two-phase processing. At time t3, the A / D converter 3 outputs data represented by solid circles and squares, and at time t5. , And outputs video data a represented by a filled triangle and video data b and c at time t7. In the video signal processing device according to the present embodiment, since only the first phase data 10 is input to the leading edge detection circuit 40, the timing of the leading edge of the output signal from the leading edge detection circuit 40 matches the time t7. I do. Therefore, M1 is the number of back porches from time t1 to t7, that is, 6. However, it is conceivable that the video data b or subsequent data is black level data. In that case, the timing of the leading edge of the output signal from the leading edge detection circuit 40 is further after time t7.
[0082]
In FIG. 6B, since the reference signal 9 is delayed by one clock, the timing of the leading edge of the output signal from the multiplexer 2 matches the time t2. Therefore, A / D converter 3 receives video signal 24 from time t2, starts two-phase processing, outputs data represented by filled rectangles and triangles at time t4, and outputs data represented by filled squares and triangles at time t6. , And outputs video data a and b. In the video signal processing device according to the present embodiment, since only the first phase data 10 is input to the leading edge detection circuit 40, the timing of the leading edge of the output signal from the leading edge detection circuit 40 matches the time t6. I do. Therefore, M2 is the number of back porches from time t2 to t6, that is, four. Therefore, M2 always becomes a numerical value smaller than M1. As described above, it can be seen that the relationship such as the above equation (4) is established.
[0083]
Next, the comparator Fifteen Outputs the control signal 12 to the multiplexer 2 when the above equation (3) is satisfied. Therefore, the multiplexer 2 further performs a switching operation and outputs the reference signal 9. When the reference signal 9 is input, the A / D converter 3 can maintain a state where the leading data in the effective video signal area is always output from the first phase data. Therefore, as in the first embodiment, if the present video signal processing circuit can hold a state in which the first data is always output from the first phase data, basically, There is no need to operate after that.
[0084]
Also the comparator Fifteen Does not output the control signal 12 to the multiplexer 2 since the multiplexer 2 only needs to select the signal from the one-clock delay circuit 1 when the above equation (4) holds. Since the control signal 12 is not input to the multiplexer 2, the multiplexer 2 subsequently selects the signal from the one-clock delay circuit 1 and outputs the signal to the A / D converter 3. If the signal from the one-clock delay circuit 1 is selected, the A / D converter 3 uses the signal shifted by one clock phase as a reference, so that the first data in the effective video signal area always starts from the first-phase data. The output state can be held. Therefore, as in the first embodiment, if the present video signal processing circuit can hold a state in which the first data is always output from the first phase data, basically, There is no need to operate after that.
[0085]
However, even when the head signal in the effective video signal area is output from the second phase data while the video signal processing circuit is operated, the same as in the first embodiment, It is possible to maintain a state in which the first data in the effective video signal area is always output from the first phase data.
[0086]
As described above, according to the video signal processing device of the present embodiment, the back porch period output from the back porch detection circuit 60 is stored and output in the storage unit 13 in each state, and the output data is output. , The comparator 15 performs the discriminating operation, whereby all video signals can be reliably displayed on the display.
[0087]
The configuration of the video signal processing device according to the present embodiment is different from the configuration of the video signal processing device according to the above-described first embodiment and each embodiment described later in that the output from the A / D converter 3 is 2. The phase data 11 is not used as a detection signal. Therefore, in the present video signal processing device, the substrate wiring area and the like can be further reduced.
[0088]
In the present embodiment, the first-phase data 10 is used as the detection signal, but it goes without saying that the second-phase data 11 may be used. Further, the video signal processing device according to the present embodiment can be configured by replacing the leading edge detection circuit 40 with a trailing edge detection circuit. In the case of such a configuration, the back porch detection circuit 60 operates to detect a period obtained by further adding the effective video signal period to the back porch period. With such a configuration, the video signal processing device according to the present embodiment can perform the same operation.
[0089]
Further, as in the case of the first embodiment, the one-clock delay circuit 1 may be any circuit that delays the reference signal 9 by an odd clock. Further, even if the A / D converter 3 is an A / D converter that performs four-phase processing, six-phase processing, or the like, the same operation can be easily performed.
[0090]
(Third embodiment)
FIG. 7 is a block diagram showing a configuration of a video signal processing device according to the third embodiment of the present invention. 7, the present video signal processing apparatus has substantially the same configuration as the video signal processing apparatus according to the second embodiment described above with reference to FIG. However, this video signal processing apparatus is different from the second embodiment in that the back porch detection circuit 60 and the storage unit 13 in FIG. 3 are omitted, and the trailing edge detection circuit 16 and the effective video period detection circuit 17 are provided. The video signal processing device according to Therefore, in the present video signal processing device, the same components as those of the video signal processing device according to the second embodiment are denoted by the same reference numerals, and description thereof is omitted. Note that the comparator 18 has a different signal from that of the comparator 15, and thus is given a different symbol. The operation of the present video signal processing device configured as described above will be described below with reference to FIGS.
[0091]
First, when the first-phase data 10 is input from the A / D converter 3, the leading-edge detection circuit 40 determines a position where the first-phase data 10 first rises starting from the pulse position of the output signal from the multiplexer 2. Is detected. The detection result is output in the form of a pulse signal as shown in FIG.
[0092]
On the other hand, when the second-phase data 11 is input from the A / D converter 3, the trailing-edge detection circuit 16 lastly falls from the pulse position of the output signal from the multiplexer 2 as a starting point. Detect the position. The detection result is output in the form of a pulse signal as shown in FIG.
[0093]
The signals output from the leading edge detection circuit 40 and the trailing edge detection circuit 16 are input to the effective video period detection circuit 17. The effective video period detection circuit 17 generates an effective video period detection signal as shown in FIG. 8 from these signals inside the circuit. Further, the effective video period detection circuit 17 includes a counter circuit, and counts how many times the pulse width of the above-mentioned effective video period detection signal is the number of dot clocks of the image signal source. Is detected. As described above, the effective video period detection circuit 17 can accurately count by using the number of dot clocks of the image signal source. Note that the number of pixels is の of the number of pixels in the effective video period of the original video signal 24 by the A / D converter 3 performing the two-phase processing.
[0094]
The number of pixels included in the valid video signal period detected by the valid video period detection circuit 17 is input to the comparator 18. Further, the comparator 18 receives a value of 部 of the horizontal resolution of the image signal source connected to the video signal processing device from a numerical output unit (not shown). Here, the horizontal resolution number of the image signal source can be easily calculated from the unique horizontal synchronization signal frequency and vertical signal frequency of the image signal source. The comparator 18 outputs the control signal 12 to the multiplexer 2 based on the result obtained from each of the numerical values input as described above according to a predetermined discrimination logic. When the control signal 12 is input, the multiplexer 2 performs an operation of switching the output signal from one of the output signal from the one-clock delay circuit 1 and the reference signal 9 to the other. Of course, the comparator 18 Does not output the control signal 12 based on the result obtained according to the determination logic described later, the multiplexer 2 does not perform the switching operation.
[0095]
Next, the comparator described above 18 Will be described in detail with reference to FIG. FIG. 9 is a time chart illustrating a relationship between the detection signal generated in the effective video period detection circuit 17 and the first phase data 10 and the second phase data 11. FIG. 9A shows a case where the head data (the leftmost data on the display) in the effective video signal area is output from the first phase of the A / D converter 3. FIG. 9B shows a case where the head data is output from the second phase of the A / D converter 3.
[0096]
In FIG. 9, a to t are data included in the video signal 24 input to the A / D converter 3. Further, for convenience of explanation, it is assumed that all of a to t are ON. Of course, in the present embodiment, it goes without saying that the data included in the video signal 24 may be black level data.
[0097]
First, as shown in FIG. 9A, the first data (left end data on the display) a in the effective video signal area is included in the first-phase data 10, so the second data b from the top is Are included in the second-phase data 11 at positions in the same phase as the first-phase data a. In this way, the A / D converter 3 performs the two-phase processing on the 20 data from the data a to the data t.
[0098]
Further, the leading edge and trailing edge of the detection signal generated in the effective video period detecting circuit 17 coincide with the leading edge of the first phase data 10 and the trailing edge of the second phase data 11, respectively. Therefore, data a to data t fall within the range of the pulse width of the detection signal generated in the effective video period detection circuit 17. Then the figure 9 As shown in (a), the relationship represented by the following equation (5) is established between the number of pixels detected by the effective video period detection circuit 17 and the number of horizontal resolutions.
Number of detected pixels = number of horizontal resolutions / 2 (5)
[0099]
Comparator 18 Does not output the control signal 12 to the multiplexer 2 when the above equation (5) is satisfied. Therefore, the multiplexer 2 outputs the reference signal 9 without performing the switching operation. When the reference signal 9 is input, the A / D converter 3 can maintain a state where the leading data in the effective video signal area is always output from the first phase data. Therefore, as in the first embodiment, if the present video signal processing circuit can hold a state in which the first data is always output from the first phase data, basically, There is no need to operate after that.
[0100]
Next, as shown in FIG. 9B, the first data (left end data on the display) a in the effective video signal area is included in the second-phase data 11, so that the second data b Is included in the second phase data 11 at a position having a phase relationship delayed by one clock from the position of the first phase data a. In this way, the A / D converter 3 performs the two-phase processing on the 20 data from the data a to the data t.
[0101]
Further, the leading edge and trailing edge of the detection signal generated in the effective video period detecting circuit 17 coincide with the leading edge of the first phase data 10 and the trailing edge of the second phase data 11, respectively. Therefore, the data a which is the first data in the second phase data 11 has a phase relationship delayed by one clock from the leading edge of the first phase data 10, and the data t which is the last data in the first phase data 10 is Since the phase relationship is delayed by one clock from the trailing edge of the second phase data 11, the pulse width of the detection signal generated in the effective video period detection circuit 17 does not fall within the range. Then the figure 9 (b) As shown in the following, a relationship such as the following equation (6) is established between the number of pixels detected by the effective video period detection circuit 17 and the number of horizontal resolutions.
Number of detected pixels = (number of horizontal resolution / 2) −1 (6)
[0102]
Also the comparator 18 Outputs the control signal 12 to the multiplexer 2 so that the multiplexer 2 selects the signal from the one-clock delay circuit 1 when the above equation (6) is satisfied. The multiplexer 2 receives the control signal 12 and switches the output signal. Specifically, the multiplexer 2 selects a signal from the one-clock delay circuit 1 and outputs the signal to the A / D converter 3. When the signal from the one-clock delay circuit 1 is selected, the A / D converter 3 uses the signal shifted by one clock phase as a reference. The state in which the leading data is output can be held. Therefore, as in the first embodiment, if the present video signal processing circuit can hold a state in which the first data is always output from the first phase data, basically, There is no need to operate after that.
[0103]
However, even when the head signal in the effective video signal area is output from the second phase data while the video signal processing circuit is operated, the same as in the first embodiment, It is possible to maintain a state in which the first data in the effective video signal area is always output from the first phase data.
[0104]
As described above, according to the video signal processing device according to the present embodiment, the effective video period detection circuit 17 to which the pulses detected by the leading edge detection circuit 40 and the rear edge detection circuit 16 are respectively input is used within the effective video period. Is detected, and the number of pixels and a value of の of the horizontal resolution number are input to the comparator 18 and compared with each other, so that all video data can be reliably displayed on the display.
[0105]
In the present embodiment, the description has been made assuming that all the video data a to t in the effective video signal area of the video signal 24 are ON. If so, the same operation as described above is performed. In the present embodiment, as in the first embodiment, the one-clock delay circuit 1 may be any circuit as long as the circuit delays the reference signal 9 by an odd clock. Furthermore, even if the A / D converter 3 is an A / D converter that performs four-phase processing, six-phase processing, or the like, the same operation can be easily performed.
[0106]
(Fourth embodiment)
FIG. 10 is a block diagram showing a configuration of a video signal processing device according to the fourth embodiment of the present invention. 10, the present video signal processing apparatus has substantially the same configuration as the video signal processing apparatus according to the third embodiment described above with reference to FIG. Therefore, the components of the present video signal processing device are the same as those of the video signal processing device according to the third embodiment, and the description thereof will be omitted using the same reference numerals. However, while the first phase data 10 is input to the leading edge detection circuit 40 and the second phase data 11 is input to the trailing edge detection circuit 16 in FIG. The difference is that the second phase data 11 is input to the leading edge detection circuit 40 and the first phase data 10 is input to the trailing edge detection circuit 16. Therefore, the reason why such a difference is provided will be described below.
[0107]
As described above, in the video signal processing device according to the third embodiment, both ends of the effective video signal included in the video signal 24 input to the A / D converter 3 always rise (that is, data is ON). ) Needed. For example, in FIG. 9A, when the head data a is OFF (that is, black level data), the detection signal generated in the effective video period detection circuit 17 is one of the horizontal resolution number of the image signal source. / 2. Therefore, the comparator 18 outputs the control signal 12 so as to switch the output of the multiplexer 2.
[0108]
However, even if the output of the multiplexer 2 is switched, the detection signal generated in the effective video period detection circuit 17 is still less than half the number of horizontal resolutions of the image signal source. Therefore, the comparator 18 outputs the control signal 12 so as to further switch the output of the multiplexer 2. Thus, the comparator 18 falls into an operation state of an infinite loop as a result.
[0109]
As described above, in a configuration such as the video signal processing device according to the third embodiment, it is necessary to provide a constraint that both ends of the video signal 24 are always ON as described above. If no constraint condition is provided, it is necessary to further add a component for detecting whether or not the above-described infinite loop has occurred to the video signal processing device, which complicates the circuit and increases the cost.
[0110]
Therefore, the video signal processing device according to the present embodiment uses the above-described configuration as shown in FIG. 10 to fall into an infinite loop state in the configuration like the video signal processing device according to the third embodiment. This problem can be easily solved. Hereinafter, the operation of the video signal processing device will be described with reference to FIG.
[0111]
FIG. 11 is a time chart showing the relationship between the detection signal generated in the effective video period detection circuit 17 and the first phase data 10 and the second phase data 11. FIG. 11A shows a case where the first data (the leftmost data on the display) in the effective video signal area is included in the first phase data 10 of the A / D converter 3. FIG. 11B shows a case where the first data is included in the second phase data 11 of the A / D converter 3.
[0112]
In FIG. 11, a to t are data included in the video signal 24 input to the A / D converter 3. Here, for convenience of explanation, it is assumed that all of the data a to t are ON. In the present embodiment, a case where the data included in the video signal 24 includes black level data will be described later.
[0113]
First, in the case shown in FIG. 11A, the first data (left end data on the display) a in the effective video signal area is included in the first-phase data 10, so that b is included in the second phase data 11 at the same phase as the first phase data a. In this way, the A / D converter 3 performs the two-phase processing on the 20 data from the data a to the data t.
[0114]
Further, the leading edge and trailing edge of the detection signal generated in the effective video period detecting circuit 17 coincide with the leading edge of the second phase data 11 and the trailing edge of the first phase data 10, respectively. Therefore, data a to data t fall within the range of the pulse width of the detection signal generated in the effective video period detection circuit 17. Then, as shown in FIG. 11A, the following equation (7) is established between the number of pixels detected by the effective video period detection circuit 17 and the number of horizontal resolutions.
Number of detected pixels = number of horizontal resolutions / 2 (7)
[0115]
Comparator 18 Outputs the control signal 12 to the multiplexer 2 so that the multiplexer 2 selects the reference signal 9 when the above equation (7) holds. The multiplexer 2 receives the control signal 12, selects the reference signal 9 corresponding to the control signal, and outputs it to the A / D converter 3. When the reference signal 9 is selected in this way, the A / D converter 3 can maintain a state where the first data in the effective video signal area is always output from the first phase data. Therefore, as in the case of the first embodiment, the present video signal processing circuit basically becomes basically capable of maintaining the state in which the first data is always output from the first phase data. There is no need to operate after that.
[0116]
Next, in the case as shown in FIG. 11B, the first data (left end data on the display) a in the effective video signal area is included in the second phase data 11, so that Is included in the second-phase data 11 at a position having a phase relationship delayed by one clock from the position of the first-phase data a. In this way, the A / D converter 3 performs the two-phase processing on the 20 data from the data a to the data t.
[0117]
Further, the leading edge and trailing edge of the detection signal generated in the effective video period detecting circuit 17 coincide with the leading edge of the second phase data 11 and the trailing edge of the first phase data 10, respectively. Therefore, the data a which is the first data in the second phase data 11 and the data t which is the last data in the first phase data 10 are each a pulse of the detection signal generated in the effective video period detection circuit 17. It will fall within the range of the width. Then, as shown in FIG. 11B, a relationship represented by the following equation (8) is established between the number of pixels detected by the effective video period detection circuit 17 and the number of horizontal resolutions.
Number of detected pixels = (number of horizontal resolution / 2) +1 (8)
[0118]
Since a relationship like the above equation (8) is established, if the above equation (8) is transformed into an inequality in relation to the above equation (7), the pixel detected by the effective video period detection circuit 17 is obtained. The following equation (9) holds between the number and the horizontal resolution number.
Number of detected pixels> number of horizontal resolution / 2 (9)
[0119]
Comparator 18 Outputs the control signal 12 to the multiplexer 2 so that the multiplexer 2 selects the signal from the one-clock delay circuit 1 when the above equation (9) is satisfied. The multiplexer 2 receives the control signal 12 and switches the output signal. Specifically, the multiplexer 2 selects a signal from the one-clock delay circuit 1 and outputs the signal to the A / D converter 3. When the signal from the one-clock delay circuit 1 is selected, the A / D converter 3 uses the signal shifted by one clock phase as a reference. The state in which the leading data is output can be held. Therefore, as in the first embodiment, if the present video signal processing circuit can hold a state in which the first data is always output from the first phase data, basically, There is no need to operate after that.
[0120]
However, even when the head signal in the effective video signal area is output from the second phase data while the video signal processing circuit is operated, the same as in the first embodiment, It is possible to maintain a state in which the first data in the effective video signal area is always output from the first phase data.
[0121]
Next, a case where an arbitrary pixel is OFF in FIG. 11 will be described. The state in which the video signal 24 is always missing one pixel on the display occurs only when the above-mentioned expression (9) is satisfied. This is because such a missing pixel does not occur when the head or the tail of the video data is black data. However, both ends of the video data must be ON in order to satisfy the equation (9). It is.
[0122]
Therefore, if the following equation (10) holds, the comparator 18 Holds the output state of the multiplexer 2 and inputs the output state to the A / D converter 3 as it is.
Number of detected pixels ≦ number of horizontal resolutions / 2 (10)
[0123]
When the above-mentioned expression (9) is satisfied, the comparator 18 Outputs the control signal 12 to switch the output of the multiplexer 2. Such a comparator 18 By this operation, the present video signal processing apparatus can always display an image without any pixel omission on the display.
[0124]
As described above, the present video signal processing device includes the number of pixels detected by the effective video period detection circuit 17 to which the detection pulses detected by the leading edge detection circuit 40 and the rear edge detection circuit 16 are input, respectively, With the configuration in which the value of 水平 of the horizontal resolution number of the image signal source connected to the processing device is input to the comparator 18 and the discriminating operation is performed, all video signals can be reliably displayed on the display.
[0125]
In the present embodiment, as in the first embodiment, the one-clock delay circuit 1 may be any circuit as long as the circuit delays the reference signal 9 by an odd clock. Furthermore, even if the A / D converter 3 is an A / D converter that performs four-phase processing, six-phase processing, or the like, the same operation can be easily performed.
[0126]
(Fifth embodiment)
FIG. 12 is a block diagram showing a configuration of a video signal processing device according to the fifth embodiment of the present invention. 12, the present video signal processing device has substantially the same configuration as the video signal processing device according to the third embodiment described above with reference to FIG. However, this video signal processing device is different from the leading edge detecting circuit 40 and the trailing edge detecting circuit shown in FIG. 16 And the effective video period detecting circuit 17 are respectively a first leading edge detecting circuit 4 and a first trailing edge detecting circuit in the present video signal processing device. 16 And a first effective video period detection circuit 20, and a second leading edge detection circuit 5, a second trailing edge detection circuit 21, and a second effective video period detection circuit 22 are provided. This is different from the video signal processing device according to the third embodiment described above. Therefore, in the present video signal processing device, the same components as those of the video signal processing device according to the third embodiment are denoted by the same reference numerals, and description thereof is omitted. The comparator 23 is a comparator 18 Since the input signal is different from, different reference numerals are used.
[0127]
The video signal processing apparatus according to the third embodiment described above with reference to FIG. 7 focuses on signals input to each leading edge detection circuit, each trailing edge detection circuit, and each effective video period detection circuit. It can be said that the configuration is a combination of the signal processing device and the video signal processing device according to the fourth embodiment described above with reference to FIG. Details will be described below.
[0128]
The video signal processing devices according to the third and fourth embodiments need to detect the horizontal resolution number of the image signal source as described above. In general, the horizontal resolution number of the image signal source can be predicted by detecting the horizontal synchronization signal frequency and the vertical synchronization signal frequency of each image signal source. However, in the current market, there are image signal sources whose horizontal resolution number cannot be predicted from the horizontal synchronization signal frequency and the vertical synchronization signal frequency of each image signal source.
[0129]
Therefore, if the display is adapted to such an image signal source, a new device configuration for recognizing such an image signal source is required. In addition, when the types of image signal sources to be dealt with increase, the scale of the above-described new device configuration increases correspondingly, and as a result, the circuit scale of the entire device increases.
[0130]
Thus, the video signal processing device according to the present embodiment can easily solve the above-described problem with the configuration as shown in FIG. Hereinafter, the operation of the video signal processing device will be described with reference to FIG.
[0131]
FIG. 13 shows an effective video period detection circuit. 20 4 is a time chart showing a relationship between each detection signal generated in the first and second phase data 10 and the second phase data 11. FIG. 13A shows a case where the head data (the left end data on the display) in the effective video signal area is included in the first phase data 10 of the A / D converter 3. FIG. 13B illustrates a case where the first data is included in the second phase data 11 of the A / D converter 3.
[0132]
In FIG. 13, a to t are data included in the video signal 24 input to the A / D converter 3. Here, for convenience of explanation, it is assumed that all of the data a to t are ON.
[0133]
First, figure Thirteen As shown in (a), the first data (left end data on the display) a in the effective video signal area is included in the first-phase data 10, so the second data b from the first is the first-phase data. The position having the same phase as “a” is included in the second phase data 11. In this way, the A / D converter 3 performs the two-phase processing on the 20 data from the data a to the data t.
[0134]
Further, the leading edge and trailing edge of the detection signal generated in the effective video period detecting circuit 17 coincide with the leading edge of the first phase data 10 and the trailing edge of the second phase data 11, respectively. This is the same as the operation of the video signal processing circuit according to the third embodiment. That is, this is the same as the case of FIG. 9A described above. Further, the leading edge and the trailing edge of the detection signal generated in the effective video period detecting circuit 22 coincide with the leading edge of the second phase data 11 and the trailing edge of the first phase data 10, respectively. This is the same as the operation of the video signal processing circuit according to the fourth embodiment. That is, this is the same as the case of FIG. 11A described above.
[0135]
Then, as shown in FIG. 13A, the pulse width PW1 of the detection signal generated in the effective video period detection circuit 17 and the pulse width PW2 of the detection signal generated in the effective video period detection circuit 22 With The following equation (11) holds between them.
PW1 = PW2 (11)
[0136]
Comparator 23 Outputs the control signal 12 to the multiplexer 2 so that the multiplexer 2 selects the reference signal 9 when the above equation (11) is satisfied. The multiplexer 2 receives the control signal 12, selects the reference signal 9 corresponding to the control signal, and outputs it to the A / D converter 3. When the reference signal 9 is selected in this way, the A / D converter 3 can maintain a state where the first data in the effective video signal area is always output from the first phase data. Therefore, as in the case of the first embodiment, the present video signal processing circuit basically becomes basically capable of maintaining the state in which the first data is always output from the first phase data. There is no need to operate after that.
[0137]
Next, as shown in FIG. 13B, the first data (left end data on the display) a in the effective video signal area is included in the second phase data 11, so that the second data b Is included in the second phase data 11 at a position having a phase relationship delayed by one clock from the position of the first phase data a. In this way, the A / D converter 3 performs the two-phase processing on the 20 data from the data a to the data t.
[0138]
Further, the leading edge and trailing edge of the detection signal generated in the effective video period detecting circuit 17 coincide with the leading edge of the first phase data 10 and the trailing edge of the second phase data 11, respectively. This is the same as the operation of the video signal processing circuit according to the third embodiment. That is, it is the same as the case of FIG. 6-1 (b) described above. Further, the leading edge and the trailing edge of the detection signal generated in the effective video period detecting circuit 22 coincide with the leading edge of the second phase data 11 and the trailing edge of the first phase data 10, respectively. This is the same as the operation of the video signal processing circuit according to the fourth embodiment. In other words, 11 This is the same as the case (b).
[0139]
Then, FIG. 13 ( b ), The pulse width PW1 of the detection signal generated in the effective video period detection circuit 17 and the pulse width PW2 of the detection signal generated in the effective video period detection circuit 22 With The following equation (12) holds between them.
PW1 <PW2 (12)
[0140]
Comparator 23 Outputs the control signal 12 to the multiplexer 2 so that the multiplexer 2 selects the signal from the one-clock delay circuit 1 when the above equation (12) holds. The multiplexer 2 receives the control signal 12 and switches the output signal. Specifically, the multiplexer 2 selects a signal from the one-clock delay circuit 1 and outputs the signal to the A / D converter 3. When the signal from the one-clock delay circuit 1 is selected, the A / D converter 3 uses the signal shifted by one clock phase as a reference. The state in which the leading data is output can be held. Therefore, as in the first embodiment, if the present video signal processing circuit can hold a state in which the first data is always output from the first phase data, basically, There is no need to operate after that.
[0141]
However, even when the head signal in the effective video signal area is output from the second phase data while the video signal processing circuit is operated, the same as in the first embodiment, It is possible to maintain a state in which the first data in the effective video signal area is always output from the first phase data.
[0142]
Then figure Thirteen In (a), a case where only the video data a and t are OFF will be described. In such a case, the first phase data 10 does not include the first data and the second phase data 11 does not include the last data of the video data, that is, the state shown in FIG. It becomes the same as the state. Therefore, the above equation (12) is satisfied, and the comparator 23 Outputs a control signal 12 to the multiplexer 2 so that the multiplexer 2 selects a signal from the one-clock delay circuit 1. The multiplexer 2 receives the control signal 12 and switches the output signal. Specifically, the multiplexer 2 selects a signal from the one-clock delay circuit 1 and outputs the signal to the A / D converter 3. When the signal from the one-clock delay circuit 1 is selected, the A / D converter 3 uses the signal shifted by one clock phase as a reference. The state in which the leading data is output can be held.
[0143]
At this time, the leading data a in the video signal 24 is included in the second phase data 11. Therefore, it seems that the ideal state as described above cannot be obtained. However, since the video data a and t are black data, the pixels are originally missing, and the above-described problem does not occur even if the image data is displayed on the display as it is. Also, in FIG. 11B, a case where only the video data a and t are OFF can be similarly described.
[0144]
Furthermore, the figure Thirteen In (a), the case where any pixel other than the video data a and t is OFF will be described. At this time, when the video data b or s is black data, PW1 becomes larger than PW2. Therefore, if the following equation (13) holds, the comparator 23 Holds the output state of the multiplexer 2 and inputs the output state to the A / D converter 3 as it is.
PW1 ≧ PW2 (13)
[0145]
Also figure Thirteen In (b), when an arbitrary pixel other than the video data a and t is OFF, the processing is the same as the above equation (12).
[0146]
From the above, when the above-mentioned expression (13) is satisfied, the comparator 23 Does not output the control signal 12 to the multiplexer 2 and holds the state of the output signal from the multiplexer 2. When the above-mentioned expression (12) holds, the comparator 23 Outputs the control signal 12 to the multiplexer 2 and switches the signal output from the multiplexer 2. By such an operation, the present video signal processing apparatus can always display an image without any pixel omission on the display.
[0147]
In the present embodiment, as in the first embodiment, the one-clock delay circuit 1 may be any circuit as long as the circuit delays the reference signal 9 by an odd clock. Furthermore, even if the A / D converter 3 is an A / D converter that performs four-phase processing, six-phase processing, or the like, the same operation can be easily performed.
[0148]
As described above, according to the configuration of the video signal processing device according to the present embodiment, it is possible to reliably display all video signals on the display without detecting the horizontal resolution number of the image signal source.
[0149]
(Sixth embodiment)
FIG. 14 is a block diagram showing a configuration of a video signal processing device according to the sixth embodiment of the present invention. 14, the present video signal processing apparatus has substantially the same configuration as the video signal processing apparatus according to the first embodiment described above with reference to FIG. However, in the present video signal processing apparatus, the multiplexer 2 and the one-clock delay circuit 1 in FIG. 1 are omitted, and multiplexers 26 and 27 and a one-clock delay circuit 25 are newly provided. This is different from the video signal processing device according to the first embodiment described above. Therefore, in the present video signal processing device, the same components as those of the video signal processing device according to the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0150]
Further, the present video signal processing device has a feature in a position where the one-clock delay circuit 25 is provided, as compared with the video signal processing devices according to the first to fifth embodiments described above. Hereinafter, the reason why the feature is provided will be described.
[0151]
The video signal processing apparatus according to the first to fifth embodiments performs an operation of changing the phase of the pulse output from the multiplexer 2 with respect to the video signal 24, thereby reliably displaying all video signals on the display. Can be done. However, the one-clock delay circuit 1 included in these video signal processing devices is a circuit that delays the signal from the image signal source by one pixel. Therefore, especially in the case of trying to cope with an image signal source of an ultra-high resolution, the one-clock delay circuit 1 must be constituted by a very high-speed element, so that the cost is increased and the power consumption is increased. Such a problem arises.
[0152]
Therefore, the video signal processing device can easily solve the above-mentioned problem by using the configuration as shown in FIG. That is, in FIG. 14, the one-clock delay circuit 25 receives the second-phase data 11 and delays one clock in the two-phase processing (in other words, the original two clocks in the image signal source). Therefore, the one-clock delay circuit 25 can correspond to an ultra-high-resolution image signal source without being configured by a particularly high-speed element.
[0153]
Next, in the present video signal processing device, the multiplexer 26 outputs the signal output from the first clock delay circuit 25 to which the first-phase data 10 and the second-phase data 11 are input, that is, the second-phase data delayed by one clock. 11 is input. The multiplexer 27 receives the first-phase data 10 and the second-phase data 11. When the present video signal processing apparatus is started, the multiplexer 26 selects and outputs the first-phase data 10, 27 Selects and outputs the second phase data 11. Thereafter, when the control signal 12 is input from the comparator 8, the multiplexer 26 switches to select the second-phase data 11 delayed by one clock, and outputs the selected data. 27 Are switched to select the first phase data 10 and output.
[0154]
The operation of the video signal processing device according to the present embodiment configured as described above will be described below with reference to FIG. 15 while comparing with the video signal processing device according to the first embodiment.
[0155]
FIG. 15 is a schematic diagram showing the relationship between the first-phase data 10 and the second-phase data 11 and the output signal 28 from the multiplexer 26 and the output signal 29 from the multiplexer 27. In FIG. 15, a to t are data included in the video signal 24 input to the A / D converter 3. FIG. 15A shows a case where the first data (the leftmost data on the display) in the effective video signal area is included in the first phase data 10 of the A / D converter 3. FIG. 15B shows a case where the first data is included in the second phase data 11 of the A / D converter 3.
[0156]
First, in the case as shown in FIG. 15A, the comparator 8 operates in the same manner as the video signal processing device according to the first embodiment. That is, as described above, when the above equation (1) holds, the comparator 8 does not output the control signal 12 to the multiplexer. Therefore, the multiplexers 26 and 27 select and output the first-phase data 10 and the second-phase data 11 output from the A / D converter 3 without performing the switching operation, as described above. Then, the video signal processing apparatus can maintain a state in which the first data in the valid video signal area is always output from the first phase data. Therefore, once the present video signal processing circuit can maintain the state in which the first data is always output from the first phase data, there is basically no need to operate thereafter.
[0157]
Next, in a case as shown in FIG. 15B, the comparator 8 operates similarly to the video signal processing device according to the first embodiment. That is, as described above, when the above equation (2) holds, the comparator 8 outputs the control signal 12 to the multiplexer. Therefore, the multiplexer 26 and 27 Receives the control signal 12 and performs the switching operation as described above. That is, the multiplexer 27 Is switched to select the second-phase data 11 delayed by one clock, and the multiplexer 26 switches to select the first-phase data 10 and outputs. Then, the video signal processing apparatus can maintain a state in which the first data in the valid video signal area is always output from the first phase data. Therefore, once the present video signal processing circuit can maintain the state in which the first data is always output from the first phase data, there is basically no need to operate thereafter.
[0158]
However, even when the head signal in the effective video signal area is output from the second phase data while the video signal processing circuit is operated, the same as in the first embodiment, It is possible to maintain a state in which the first data in the effective video signal area is always output from the first phase data.
[0159]
As described above, the video signal processing device according to the present embodiment can easily cope with an increase in resolution of an image signal source, and can reliably display all video signals on a display.
[0160]
Note that the video signal processing device according to the present embodiment can be configured by replacing the first and second leading edge detection circuits 4 and 5 with first and second trailing edge detection circuits, respectively. In the case of such a configuration, the first and second back porch detection circuits 6 and 7 operate to detect a period obtained by adding an effective video signal period to the back porch period. With such a configuration, the video signal processing device according to the present embodiment can perform the same operation.
[0161]
Further, the video signal processing device according to the present embodiment is configured by modifying the video signal processing device according to the first embodiment for convenience of description. However, the video signal processing device according to the present embodiment may be configured by modifying the video signal processing devices according to the second to fifth embodiments. That is, the control signal 12 for controlling the multiplexer 2 included in the video signal processing devices according to the second to fifth embodiments described above may be used as a control signal for the multiplexers 26 and 27 included in the present video signal processing device. it can. With such a configuration, the video signal processing device according to the present embodiment can be easily realized by modifying the video signal processing devices according to the second to fifth embodiments.
[0162]
Furthermore, in the present embodiment, as in the above-described embodiments, the one-clock delay circuit 25 may be any circuit that delays the reference signal 9 by an odd clock. Similarly, even if the A / D converter 3 is an A / D converter that performs four-phase processing, six-phase processing, or the like, the same operation can be easily performed.
[0163]
(Seventh embodiment)
FIG. 16 is a block diagram showing a configuration of a video signal processing device according to the seventh embodiment of the present invention. 16, the present video signal processing device has substantially the same configuration as the video signal processing device according to the first embodiment described above with reference to FIG. However, the present video signal processing device is different from the video signal processing device according to the above-described first embodiment in that first and second minimum value holding circuits 30 and 31 are newly provided. Therefore, in the present video signal processing device, the same components as those of the video signal processing device according to the first embodiment are denoted by the same reference numerals and description thereof is omitted. Hereinafter, the reason why the first and second minimum value holding circuits 30 and 31 are newly provided will be described.
[0164]
The video signal processing apparatus according to the first embodiment is configured such that the back porch periods output from the first and second back porch detection circuits 6 and 7 are input to the comparator 8, so that the entire video is reliably displayed on the display. Display the signal. According to such a configuration, no problem occurs when an arbitrary line in the video signal 24 can be extracted and operated like a still image. However, when the video signal 24 is a moving image, the back porch period is constantly changing. Then, the phase of each line on the image is frequently shifted, and if attention is paid to that point, there arises a problem that the video signal processing device does not operate normally.
[0165]
Therefore, as shown in FIG. 16, the video signal processing device according to the present embodiment receives the back porch period detected by the first back porch detection circuit 6, and detects the minimum value of the back porch period. By using the minimum value holding circuit 30 and the second minimum value holding circuit 31 that receives the back porch period detected by the second back porch detection circuit 7 and detects the minimum value, the above-described operation is performed. Such a problem can be easily solved. Hereinafter, the operation of the video signal processing apparatus will be described with reference to FIG.
[0166]
In FIG. 16, first and second minimum value holding circuits 30 and 31 are circuits for detecting the minimum value of the back porch periods continuously output from the corresponding back porch detection circuits 6 and 7. The first and second minimum value holding circuits 30 and 31 typically store the minimum value and compare the input back porch period with the stored minimum value to update the minimum value. Operate.
[0167]
The first and second minimum value holding circuits 30 and 31 allow the video signal processing apparatus to fixedly recognize the back porch period of the video signal 24 by using the minimum value. As a result, the video signal processing apparatus can operate by performing stable detection even in a moving image. Further, since the back porch period can be detected in real time by the first and second minimum value holding circuits 30 and 31, the present video signal processing device can perform the processing regardless of the type of the video signal of the image signal source. All the pixels of the video signal 24 can be displayed on the display.
[0168]
As described above, the video signal processing device according to the present embodiment can easily cope with the case where the video signal of the image signal source is a moving image, and can reliably display all video signals on the display. it can.
[0169]
Note that, in the video signal processing device according to the present embodiment, first and second minimum value holding circuits 30 and 31 are provided in the video signal processing device according to the first embodiment for convenience of description. However, the video signal processing device according to the present embodiment includes the first and second minimum value holding circuits 30 and 31 as the first and second maximum value holding circuits, and the first and second leading edge detection circuits 4. And 5 may be replaced with first and second trailing edge detection circuits, respectively. In the case of such a configuration, the first and second back porch detection circuits 6 and 7 operate to detect a period obtained by adding an effective video signal period to the back porch period. With such a configuration, the video signal processing device according to the present embodiment can perform the same operation.
[0170]
Further, in the present embodiment, as in the above-described embodiments, the one-clock delay circuit 25 may be any circuit that delays the reference signal 9 by an odd clock. Furthermore, even if the A / D converter 3 is an A / D converter that performs four-phase processing, six-phase processing, or the like, the same operation can be easily performed.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a video signal processing device according to a first embodiment of the present invention.
FIG. 2 is an operation explanatory diagram of the video signal processing device according to the first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a video signal processing device according to a second embodiment of the present invention.
FIG. 4 is an operation explanatory diagram of a video signal processing device according to a second embodiment of the present invention.
FIG. 5 is a diagram illustrating a data flow when leading data in an effective video signal area is output from a first phase of an A / D converter 3;
FIG. 6 is a diagram showing a data flow when leading data is output from the second phase of the A / D converter 3;
FIG. 7 is a block diagram showing a configuration of a video signal processing device according to a third embodiment of the present invention.
FIG. 8 is an operation explanatory diagram of a video signal processing device according to a third embodiment of the present invention.
FIG. 9 is a diagram showing a relationship between a detection signal generated in an effective video period detection circuit 17 and first-phase data 10 and second-phase data 11;
FIG. 10 is a block diagram illustrating a configuration of a video signal processing device according to a fourth embodiment of the present invention.
FIG. 11 is an operation explanatory diagram of a video signal processing device according to a fourth embodiment of the present invention.
FIG. 12 is a block diagram illustrating a configuration of a video signal processing device according to a fifth embodiment of the present invention.
FIG. 13 is an operation explanatory diagram of a video signal processing device according to a fifth embodiment of the present invention.
FIG. 14 is a block diagram showing a configuration of a video signal processing device according to a sixth embodiment of the present invention.
FIG. 15 is an operation explanatory diagram of a video signal processing device according to a sixth embodiment of the present invention.
FIG. 16 is a block diagram showing a configuration of a video signal processing device according to a seventh embodiment of the present invention.
FIG. 17 is a block diagram showing a configuration of a conventional video signal processing device.
FIG. 18 is a diagram illustrating the operation of an A / D converter that performs two-phase processing.
FIG. 19 is a diagram illustrating the operation of a conventional video signal processing device when the head of video data is output as first-phase data from an A / D converter.
FIG. 20 is a diagram illustrating the operation of a conventional video signal processing device when the head of video data is output from the A / D converter as second-phase data.
[Explanation of symbols]
11 1 clock delay circuit
2 Multiplexer
3 A / D converter
4. First Leading Edge Detection Circuit
5. Second leading edge detection circuit
6. First back porch detection circuit
7. Second back porch detection circuit
8 Comparators
9 Reference signal
10 First phase data
11 Phase 2 data
12 Control signal
13 Memory
15 Comparators
16 Trailing edge detection circuit
17 Effective video period detection circuit
18 Comparators
20 First effective video period detection circuit
21 Second trailing edge detection circuit
22. First effective video period detection circuit
23 Comparator
24 Video signal
25 One Clock Delay Circuit
26 first multiplexer
27 Second multiplexer
30 1st minimum value holding circuit
31 Second minimum value holding circuit
40 Leading edge detection circuit
60 back porch circuit
160 First Trailing Edge Detection Circuit

Claims (13)

A video signal processing device for displaying pixels included in a video signal input from an image signal source without dropping on a display,
A clock delay circuit to which a reference signal is input, the reference signal being delayed by an odd clock and output;
A multiplexer that selects and outputs one of the reference signal and the output signal from the clock delay circuit;
An A / D converter that converts the video signal into a digital signal based on an output signal from the multiplexer and outputs two-phase data as first-phase data and second-phase data;
A first leading edge detection circuit that detects a leading edge of an effective video signal area in the first phase data and outputs a corresponding detection signal;
A second leading edge detection circuit that detects a leading edge of an effective video signal area in the second phase data and outputs a corresponding detection signal;
A first back porch detection circuit for detecting a first back porch period using an output signal from the multiplexer as a start point and a detection signal output from the first leading edge detection circuit as an end point;
A second back porch detection circuit for detecting a second back porch period with an output signal from the multiplexer as a starting point and a detection signal output from the second leading edge detection circuit as an end point;
Comparing the first back porch period and the second back porch period, and when the first back porch period is longer than the second back porch period, an effective video signal in the video signal A video signal processing device comprising: a comparator that determines that head data of an area is not included in the first phase data and outputs a signal that controls switching of a signal selected and output by the multiplexer. The first back porch detection circuit detects the first back porch period using the number of clocks in the video signal,
2. The video signal processing device according to claim 1, wherein the second back porch detection circuit detects the second back porch period using the number of clocks in the video signal. A first minimum value holding circuit for newly inputting a minimum value of the first back porch period output from the first back porch detection circuit to the comparator as a first back porch period;
And a second minimum value holding circuit for newly inputting a minimum value of the second back porch period output from the second back porch detection circuit to the comparator as a second back porch period. The video signal processing device according to claim 1. A video signal processing device for displaying pixels included in a video signal input from an image signal source without dropping on a display,
A clock delay circuit to which a reference signal is input, the reference signal being delayed by an odd clock and output;
A multiplexer that selects and outputs one of the reference signal and the output signal from the clock delay circuit;
An A / D converter that converts the video signal into a digital signal based on an output signal from the multiplexer and outputs two-phase data as first-phase data and second-phase data;
A leading edge detection circuit that detects a leading edge of an effective video signal area in one of the predetermined first phase data or the second phase data, and outputs a corresponding detection signal;
A back porch detection circuit for detecting a back porch period, with the output signal from the multiplexer as a start point and the detection signal output from the leading edge detection circuit as an end point,
A storage unit to which the back porch period is input, and stores and outputs the reference signal and the output signal from the clock delay circuit, which are selected and output by the multiplexer, respectively.
Outputting, from the storage unit, a control signal for controlling switching of a signal selected and output by the multiplexer such that a back porch period corresponding to a signal selected and output by the multiplexer is output; by comparing each the back porch period it is outputted respectively corresponding to the parts, less than or equal to the back porch period back porch period corresponding to the reference signal corresponds to the output signal from the clock delay circuit In this case, the video signal processing device further comprises: a comparator that determines that the first data of the effective video signal area in the video signal is included in the first phase data and outputs the control signal again. The video signal processing device according to claim 4, wherein the back porch detection circuit detects the back porch period using the number of clocks in the video signal. A video signal processing device for displaying pixels included in a video signal input from an image signal source without dropping on a display,
A clock delay circuit to which a reference signal is input, the reference signal being delayed by an odd clock and output;
A multiplexer that selects and outputs one of the reference signal and the output signal from the clock delay circuit;
An A / D converter that converts the video signal into a digital signal based on an output signal from the multiplexer and outputs two-phase data as first-phase data and second-phase data;
A leading edge detection circuit that detects a leading edge of an effective video signal area in the first phase data and outputs a corresponding detection signal;
A trailing edge detection circuit that detects a trailing edge of the effective video signal area in the second phase data and outputs a corresponding detection signal;
With the detection signal output from the leading edge detection circuit as a start point, and with the detection signal output from the trailing edge detection circuit as an end point, an effective video period detection circuit that detects the number of pixels included in the effective video period,
The half value of the input horizontal resolution is compared with the number of pixels detected by the effective video period detection circuit, and the value of half the horizontal resolution is detected by the effective video period detection circuit. If the number of pixels is larger than the number of pixels, it is determined that the leading data of the effective video signal area in the video signal is not included in the first phase data, and the multiplexer selects and switches the signal to be output. And a comparator that outputs a control signal. The video signal processing device according to claim 6, wherein the valid video period detection circuit detects the valid video period using the number of clocks in the video signal. A video signal processing device for displaying pixels included in a video signal input from an image signal source without dropping on a display,
A clock delay circuit to which a reference signal is input, the reference signal being delayed by an odd clock and output;
A multiplexer that selects and outputs one of the reference signal and the output signal from the clock delay circuit;
An A / D converter that converts the video signal into a digital signal based on an output signal from the multiplexer and outputs two-phase data as first-phase data and second-phase data;
A leading edge detection circuit that detects a leading edge of an effective video signal area in the second phase data and outputs a corresponding detection signal;
A trailing edge detection circuit that detects a trailing edge of the effective video signal area in the first phase data and outputs a corresponding detection signal;
With the detection signal output from the leading edge detection circuit as a start point, and with the detection signal output from the trailing edge detection circuit as an end point, an effective video period detection circuit that detects the number of pixels included in the effective video period,
When the value of 1/2 of the input horizontal resolution is compared with the effective video period, and the value of 1/2 of the horizontal resolution is smaller than the number of pixels detected by the effective video period detection circuit, In the comparison, it is determined that the first data of the effective video signal area in the video signal is not included in the first phase data, and a signal for controlling the multiplexer to select and output a signal is output. A video signal processing device comprising a device. 9. The video signal processing device according to claim 8, wherein the effective video period detection circuit detects the effective video period using the number of clocks in the video signal. A video signal processing device for displaying pixels included in a video signal input from an image signal source without dropping on a display,
A clock delay circuit to which a reference signal is input, the reference signal being delayed by an odd clock and output;
A multiplexer that selects and outputs one of the reference signal and the output signal from the clock delay circuit;
An A / D converter that converts the video signal into a digital signal based on an output signal from the multiplexer and outputs two-phase data as first-phase data and second-phase data;
A first leading edge detection circuit that detects a leading edge of an effective video signal area in the first phase data and outputs a corresponding detection signal;
A second leading edge detection circuit that detects a leading edge of an effective video signal area in the second phase data and outputs a corresponding detection signal;
A first trailing edge detection circuit that detects a trailing edge of the effective video signal area in the second phase data and outputs a corresponding detection signal;
A second trailing edge detection circuit that detects the trailing edge of the effective video signal area in the first phase data and outputs a corresponding detection signal;
A first effective image for detecting a first effective image period using a detection signal output from the first leading edge detection circuit as a starting point and a detection signal output from the first trailing edge detection circuit as an end point. A period detection circuit;
A second effective image for detecting a second effective image period using the detection signal output from the second leading edge detection circuit as a start point and the detection signal output from the second trailing edge detection circuit as an end point A period detection circuit;
Comparing the first effective video period with the second effective video period, and when the second effective video period is longer than the first effective video period, an effective video signal in the video signal; A video signal processing device comprising: a comparator that determines that head data of an area is not included in the first phase data and outputs a signal that controls switching of a signal selected and output by the multiplexer. The first effective video period detection circuit detects the first effective video period using the number of clocks in the video signal,
The video signal processing apparatus according to claim 10, wherein the second valid video period detection circuit detects the second valid video period using the number of clocks in the video signal. A video signal processing device for displaying pixels included in a video signal input from an image signal source without dropping on a display,
An A / D converter that converts the video signal into a digital signal based on an input reference signal and outputs two phases as first phase data and second phase data;
A clock delay circuit to which the second-phase data is input and which delays and outputs the second-phase data by an odd clock;
A first multiplexer that selects and outputs one of the first phase data and an output signal from the clock delay circuit;
A second multiplexer that selects and outputs one of the second phase data and the first phase data;
A first leading edge detection circuit that detects a leading edge of an effective video signal area in the first phase data and outputs a corresponding detection signal;
A second leading edge detection circuit that detects a leading edge of an effective video signal area in the second phase data and outputs a corresponding detection signal;
A first back porch detection circuit that detects a first back porch period with the reference signal as a starting point and a detection signal output from the first leading edge detection circuit as an end point;
A second back porch detection circuit for detecting a second back porch period with the reference signal as a starting point and a detection signal output from the second leading edge detection circuit as an end point;
Comparing the first back porch period and the second back porch period, and when the first back porch period is longer than the second back porch period, an effective video signal in the video signal A comparator that determines that the first data of the area is not included in the first-phase data and outputs a signal that controls to switch simultaneously the signals selected and output by the first and second multiplexers; Prepare,
A video signal processing apparatus characterized in that a first multiplexer selects and outputs first-phase data and a second multiplexer selects and outputs second-phase data at the beginning of startup. The first back porch detection circuit detects the first back porch period using the number of clocks in the video signal,
13. The video signal processing device according to claim 12, wherein the second back porch detection circuit detects the second back porch period using the number of clocks in the video signal.

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