JP3576918B2 - Power distribution synthesis circuit - Google Patents

Description

で表され、また、前記第２の端子と前記第３の端子との間のアイソレーションを確保する条件が次の式（３）と式（４）
【数４】

で表され、前記容量Ｃ１、Ｃ２と前記電気長Ｅ１と前記抵抗値Ｒと前記特性インピーダンスＺ ₁ との間に前記式（１）から式（４）が成立することを特徴とする。
【００２４】
請求項１においては、第１のキャパシタ，第２のキャパシタ及び第３のキャパシタを設けてあるため、この電力分配合成回路の各端子間の伝達特性が周波数に応じて変化する。この周波数特性により、前記第２の端子と第３の端子との間でベースバンド信号の伝達を阻止することができる。
また、所定の条件を満足するように第１のキャパシタ，第２のキャパシタ及び第３のキャパシタ並びに他の素子の特性を定めることにより、各端子間の入出力が整合し、しかも各端子間で信号の分配及び合成を行うことが可能になる。
【００２５】
この電力分配合成回路を受信機などに用いる場合には、ベースバンド信号を阻止する機能を偶高調波ミキサに設ける必要がなくなり、偶高調波ミキサを小型化できる。実際には、電力分配合成回路に設ける第１のキャパシタ，第２のキャパシタ及び第３のキャパシタの合計の容量を、図２２のキャパシタ２０８と比べて十分小さくすることができるので、受信機全体の小型化が可能になる。
【００２６】
請求項２は、第１の端子，第２の端子及び第３の端子を備え、前記第１の端子に入力された信号を２系統に分配して前記第２の端子及び第３の端子に出力し、又は前記第２の端子及び第３の端子にそれぞれ入力された信号を合成して前記第１の端子に出力する電力分配合成回路であって、一端が前記第１の端子と接続され、他端が接地された第１のキャパシタと、一端が前記第１の端子と電気的に接続された第１の分布定数線路と、一端が前記第１の端子と電気的に接続された第２の分布定数線路と、前記第１の分布定数線路の他端と第２の分布定数線路の他端とを電気的に接続する抵抗素子と、前記第１の分布定数線路の他端と前記第２の端子とを接続する第２のキャパシタと、前記第２の分布定数線路の他端と前記第３の端子とを接続する第３のキャパシタとを設けたことを特徴とする。
【００２７】
請求項２においては、第１のキャパシタ，第２のキャパシタ及び第３のキャパシタを設けてあるため、この電力分配合成回路の各端子間の伝達特性が周波数に応じて変化する。この周波数特性により、前記第２の端子と第３の端子との間でベースバンド信号の伝達を阻止することができる。
また、所定の条件を満足するように第１のキャパシタ，第２のキャパシタ及び第３のキャパシタ並びに他の素子の特性を定めることにより、各端子間の入出力が整合し、しかも各端子間で信号の分配及び合成を行うことが可能になる。
【００２８】
この電力分配合成回路を受信機などに用いる場合には、ベースバンド信号を阻止する機能を偶高調波ミキサに設ける必要がなくなり、偶高調波ミキサを小型化できる。実際には、電力分配合成回路に設ける第１のキャパシタ，第２のキャパシタ及び第３のキャパシタの合計の容量を、図２２のキャパシタ２０８と比べて十分小さくすることができるので、受信機全体の小型化が可能になる。
【００３２】
請求項３は、第１の端子，第２の端子及び第３の端子を備え、前記第１の端子に入力された信号を２系統に分配して前記第２の端子及び第３の端子に出力し、又は前記第２の端子及び第３の端子にそれぞれ入力された信号を合成して前記第１の端子に出力する電力分配合成回路であって、一端が前記第１の端子に接続され、他端が接地された第１のインダクタと、一端が前記第１の端子に接続され、他端が前記第２の端子に接続された第１のキャパシタと、一端が前記第１の端子に接続され、他端が前記第３の端子に接続された第２のキャパシタと、抵抗素子，第２のインダクタ及び第３のキャパシタの直列回路で構成され、一端が前記第２の端子に接続され、他端が前記第３の端子に接続された抵抗回路とを設けたことを特徴とする。
【００３３】
請求項３においては、前記第１の端子に入力された信号を２系統に分配して前記第２の端子及び第３の端子に出力し、又は前記第２の端子及び第３の端子にそれぞれ入力された信号を合成して前記第１の端子に出力することができる。
また、抵抗素子，第２のインダクタ及び第３のキャパシタの直列回路が共振回路を形成するため、この電力分配合成回路の各端子間の伝達特性は周波数に応じて変化する。この周波数特性により、前記第２の端子と第３の端子との間でベースバンド信号の伝達を阻止することができる。
【００３４】
さらに、所定の条件を満足するように各素子の特性を定めることにより、各端子間の入出力特性を整合させるとともに各端子間での信号の分配・合成の機能を実現することができる。この電力分配合成回路を受信機などに用いる場合には、ベースバンド信号を阻止する機能を偶高調波ミキサに設ける必要がなくなり、偶高調波ミキサを小型化できる。
【００３５】
実際には、電力分配合成回路に設ける第１のキャパシタ，第２のキャパシタ及び第３のキャパシタの合計の容量を、図２２のキャパシタ２０８と比べて十分小さくすることができるので、受信機全体の小型化が可能になる。
請求項４は、第１の端子，第２の端子及び第３の端子を備え、前記第１の端子に入力された信号を２系統に分配して前記第２の端子及び第３の端子に出力し、又は前記第２の端子及び第３の端子にそれぞれ入力された信号を合成して前記第１の端子に出力する電力分配合成回路であって、一端が前記第１の端子に接続され、他端が接地された第１のキャパシタと、一端が前記第２の端子に接続された第２のキャパシタと、一端が前記第３の端子に接続された第３のキャパシタと、一端が前記第１の端子に接続され、他端が前記第２のキャパシタの他端と接続された第１のインダクタと、一端が前記第１の端子に接続され、他端が前記第３のキャパシタの他端と接続された第２のインダクタと、前記第１のインダクタの他端と、第２のインダクタの他端との間を接続する抵抗素子とを設けたことを特徴とする。
【００３６】
請求項４においては、前記第１の端子に入力された信号を２系統に分配して前記第２の端子及び第３の端子に出力し、又は前記第２の端子及び第３の端子にそれぞれ入力された信号を合成して前記第１の端子に出力することができる。
また、この電力分配合成回路の各端子間の伝達特性は周波数に応じて変化する。この周波数特性により、前記第２の端子と第３の端子との間でベースバンド信号の伝達を阻止することができる。
【００３７】
さらに、所定の条件を満足するように各素子の特性を定めることにより、各端子間の入出力特性を整合させるとともに、各端子間での信号の分配・合成の機能を実現することができる。この電力分配合成回路を受信機などに用いる場合には、ベースバンド信号を阻止する機能を偶高調波ミキサに設ける必要がなくなり、偶高調波ミキサを小型化できる。
【００３８】
実際には、電力分配合成回路に設ける第１のキャパシタ，第２のキャパシタ及び第３のキャパシタの合計の容量を、図２２のキャパシタ２０８と比べて十分小さくすることができるので、受信機全体の小型化が可能になる。
【００３９】
【発明の実施の形態】
（第１の実施の形態）
本発明の電力分配合成回路の１つの実施の形態について、図１〜図４を参照して説明する。この形態は請求項１に対応する。
【００４０】
図１はこの形態の電力分配合成回路の構成を示すブロック図である。図２は図１の電力分配合成回路を入出力端子１２，１３から同相励振する場合の等価回路図である。図３は図１の電力分配合成回路を入出力端子１２，１３から逆相励振する場合の等価回路図である。図４はこの形態の電力分配合成回路の周波数特性を示すグラフである。
【００４１】
この形態では、請求項１の第１の端子，第２の端子，第３の端子，第１の分布定数線路，第２の分布定数線路，抵抗素子は、それぞれ入出力端子１１，入出力端子１２，入出力端子１３，分布定数線路１４，分布定数線路１５及び抵抗素子１６に対応する。
また、請求項１の第１のキャパシタ，第２のキャパシタ及び第３のキャパシタは、それぞれキャパシタ１７，キャパシタ１８及びキャパシタ１９に対応する。
【００４２】
この形態の電力分配合成回路は、例えば図２１に示すような受信機を構成する場合に０度電力分配合成回路２１４として用いることができる。但し、この形態の電力分配合成回路は、それ自身がベースバンド信号を阻止する機能を有するため、電力分配合成回路に接続される偶高調波ミキサにはベースバンド信号を阻止する機能（図２２のキャパシタ２０８）を設ける必要がない。
【００４３】
図１を参照すると、この電力分配合成回路は入出力端子１１，１２，１３，分布定数線路１４，１５，抵抗素子１６，キャパシタ１７，１８，１９を備えている。但し、２つの分布定数線路１４，１５の特性は同一であり、２つのキャパシタ１８，１９の特性も同一である。
ここでは、キャパシタ１７の容量をＣ１で表し、キャパシタ１８，１９の容量をＣ２で表す。また、抵抗素子１６の抵抗値はＲで表す。さらに、分布定数線路１４，１５の特性については、特定の周波数ｆ_０における電気長をＥ１で表し、特性インピーダンスをＺ_１で表す。また、入出力端子１１，１２，１３にそれぞれ接続される負荷インピーダンスはＺ_０で表す。
【００４４】
図１の電力分配合成回路に必要とされる機能を想定すると、入出力端子１１に入力された信号は２つに分配されて入出力端子１２，１３に出力される。従って、入出力端子１２の信号と入出力端子１３の信号とは同相になる。
そこで、図１の電力分配合成回路を入出力端子１２，１３から同相励振する場合を考えると、図１の電力分配合成回路は図２の等価回路で表すことができる。図２において、キャパシタ２３の容量は（Ｃ１／２）になり、キャパシタ２４の容量はＣ２になる。分布定数線路２５の特性は分布定数線路１４，１５と同一である。ここでは、入出力端子１１，１２，１３に負荷インピーダンスＺ_０が接続された場合を想定している。
【００４５】
また、図１の電力分配合成回路においては、例えば反射信号として入出力端子１２に入力された信号が入出力端子１３に現れないように入出力端子１２と入出力端子１３との間のアイソレーションを確保する必要がある。この場合、入力された反射信号を抵抗素子１６で全て吸収すれば、入出力端子１２と入出力端子１３との間のアイソレーションを確保することができる。
【００４６】
そこで、図１の電力分配合成回路を入出力端子１２，１３から逆相励振する場合を考えると、図１の電力分配合成回路は図３の等価回路で表すことができる。図３において、抵抗３４の抵抗値は（Ｒ／２）になり、キャパシタ３５の容量はＣ２になる。また、分布定数線路３３の特性は分布定数線路１４，１５と同一になる。ここでは、入出力端子１１，１２，１３に負荷インピーダンスＺ_０が接続された場合を想定している。
【００４７】
従って、図１の電力分配合成回路において周波数ｆ_０で入出力端子１１〜１３の入出力を整合させるための条件、ならびに入出力端子１１と入出力端子１２，１３との間で信号を均等に分配・合成するために必要な条件は、図２の等価回路に基づいて求めることができる。これらの条件は、次の第（１）式及び第（２）式で表される。
【数１】

また、図１の電力分配合成回路において入出力端子１２と入出力端子１３との間のアイソレーションを確保するために必要な条件は図３の等価回路に基づいて求めることができる。この条件は、次の第（３）式及び第（４）式で表される。
【数２】

すなわち、上記第（１）式〜第（４）式の全ての条件を満たすように各構成要素の特性Ｅ１，Ｃ１，Ｃ２，Ｒ，Ｚ_１を決定すれば、必要とされる電力分配合成回路の機能を実現することができる。
【００４８】
この場合、入出力端子１１から高周波信号を入力すると、１／２ずつに分配された高周波信号が入出力端子１２及び入出力端子１３から同相で出力される。また、入出力端子１２から高周波信号を入力した場合、入出力端子１３では抵抗素子１６を通過した高周波信号と分布定数線路１４，１５を通過した高周波信号とが等振幅かつ逆相で合成されるため、入出力端子１３には信号が現れない。
【００４９】
特定の条件を想定して具体的な計算を行った。その結果は次の通りである。
分布定数線路１４，１５の電気長Ｅ１：６０度
周波数ｆ_０：１０ＧＨｚ
負荷インピーダンスＺ_０：５０Ω
特性インピーダンスＺ_１：１１６Ω
容量Ｃ１：０．３４ｐＦ
容量Ｃ２：１．１９ｐＦ
抵抗値Ｒ：１０７Ω
以上の条件で構成される図１の電力分配合成回路の周波数特性を数値シミュレーションで求めた結果、図４に示す周波数特性が得られた。図４に示す各パラメータの内容は次の通りである。
【００５０】
Ｓ２１：順方向伝達係数
Ｓ１１：一次側（入出力端子１１側）の入力反射係数
Ｓ２２：二次側（入出力端子１２側）の入力反射係数
Ｓ３２：アイソレーション
図４を参照すると、周波数９．４ＧＨｚ〜１０．７ＧＨｚにおいて、分配損失として（３．０５±０．０５）ｄＢ、入力反射量として−２０ｄＢ以下、アイソレーションとして２０ｄＢ以上の特性が得られていることがわかる。
【００５１】
なお、図２２に示す従来例の偶高調波ミキサの場合、キャパシタ２０８として同じ条件では１０ｐＦ程度の容量が必要になるが、キャパシタ１７〜１９の合計の容量は２．７２ｐＦであり、図１の電力分配合成回路を用いた方が回路全体をより小型化できる。
（第２の実施の形態）
本発明の電力分配合成回路の１つの実施の形態について、図５〜図８を参照して説明する。この形態は請求項２に対応する。
【００５２】
図５はこの形態の電力分配合成回路の構成を示すブロック図である。図６は図５の電力分配合成回路を入出力端子１２，１３から同相励振する場合の等価回路図である。図７は図５の電力分配合成回路を入出力端子１２，１３から逆相励振する場合の等価回路図である。図８はこの形態の電力分配合成回路の周波数特性を示すグラフである。
【００５３】
この形態は第１の実施の形態の変形例である。図５〜図８において、第１の実施の形態と対応する要素は同一の符号を付けて示してある。第１の実施の形態と同一の部分については、以下の説明を省略する。
この形態では、請求項２の第１の端子，第２の端子，第３の端子，第１の分布定数線路，第２の分布定数線路，抵抗素子は、それぞれ入出力端子１１，入出力端子１２，入出力端子１３，分布定数線路１４，分布定数線路１５及び抵抗素子１６に対応する。
【００５４】
また、請求項２の第１のキャパシタ，第２のキャパシタ及び第３のキャパシタは、それぞれキャパシタ４１，キャパシタ４２及びキャパシタ４３に対応する。
図５を参照すると、この電力分配合成回路は入出力端子１１，１２，１３，分布定数線路１４，１５，抵抗素子１６，キャパシタ４１，４２，４３を備えている。２つの分布定数線路１４，１５の特性は同一であり、２つのキャパシタ４２，４３の特性も同一である。キャパシタ４１は一端が入出力端子１１と接続され、他端が接地されている。
【００５５】
ここでは、キャパシタ４１の容量をＣ１で表し、キャパシタ４２，４３の容量をＣ２で表す。また、抵抗素子１６の抵抗値はＲで表す。さらに、分布定数線路１４，１５の特性については、特定の周波数ｆ_０における電気長をＥ１で表し、特性インピーダンスをＺ_１で表す。また、入出力端子１１，１２，１３にそれぞれ接続される負荷インピーダンスはＺ_０で表す。
【００５６】
図５の電力分配合成回路に必要とされる機能を想定すると、入出力端子１１に入力された信号は２つに分配されて入出力端子１２，１３に出力される。従って、入出力端子１２の信号と入出力端子１３の信号とは同相になる。
そこで、図５の電力分配合成回路を入出力端子１２，１３から同相励振する場合を考えると、図５の電力分配合成回路は図６の等価回路で表すことができる。図６において、キャパシタ４４の容量は（Ｃ１／２）になり、キャパシタ４５の容量はＣ２になる。分布定数線路４６の特性は分布定数線路１４，１５と同一である。ここでは、入出力端子１１，１２，１３に負荷インピーダンスＺ_０が接続された場合を想定している。
【００５７】
また、図５の電力分配合成回路においては、例えば反射信号として入出力端子１２に入力された信号が入出力端子１３に現れないように入出力端子１２と入出力端子１３との間のアイソレーションを確保する必要がある。この場合、入力された反射信号を抵抗素子１６で全て吸収すれば、入出力端子１２と入出力端子１３との間のアイソレーションを確保することができる。
【００５８】
そこで、図５の電力分配合成回路を入出力端子１２，１３から逆相励振する場合を考えると、図５の電力分配合成回路は図７の等価回路で表すことができる。図７において、抵抗４８の抵抗値は（Ｒ／２）になり、キャパシタ４９の容量はＣ２になる。また、分布定数線路４７の特性は分布定数線路１４，１５と同一になる。ここでは、入出力端子１１，１２，１３に負荷インピーダンスＺ_０が接続された場合を想定している。
【００５９】
従って、図５の電力分配合成回路において周波数ｆ_０で入出力端子１１〜１３の入出力を整合させるための条件、ならびに入出力端子１１と入出力端子１２，１３との間で信号を均等に分配・合成するために必要な条件は、図６の等価回路に基づいて求めることができる。これらの条件は、次の第（５）式及び第（６）式で表される。
【数３】

また、図５の電力分配合成回路において入出力端子１２と入出力端子１３との間のアイソレーションを確保するために必要な条件は図７の等価回路に基づいて求めることができる。この条件は、次の第（７）式及び第（８）式で表される。
【数４】

すなわち、上記第（５）式〜第（８）式の全ての条件を満たすように各構成要素の特性Ｅ１，Ｃ１，Ｃ２，Ｒ，Ｚ_１を決定すれば、必要とされる電力分配合成回路の機能を実現することができる。
【００６０】
この場合、入出力端子１１から高周波信号を入力すると、１／２ずつに分配された高周波信号が入出力端子１２及び入出力端子１３から同相で出力される。また、入出力端子１２から高周波信号を入力した場合、入出力端子１３では抵抗素子１６を通過した高周波信号と分布定数線路１４，１５を通過した高周波信号とが等振幅かつ逆相で合成されるため、入出力端子１３には信号が現れない。
【００６１】
特定の条件を想定して具体的な計算を行った。その結果は次の通りである。
分布定数線路１４，１５の電気長Ｅ１：４５度
周波数ｆ_０：１０ＧＨｚ
負荷インピーダンスＺ_０：５０Ω
特性インピーダンスＺ_１：１１５Ω
容量Ｃ１：０．２８ｐＦ
容量Ｃ２：０．５５ｐＦ
抵抗値Ｒ：１３３Ω
以上の条件で構成される図５の電力分配合成回路の周波数特性を数値シミュレーションで求めた結果、図８に示す周波数特性が得られた。
【００６２】
図８を参照すると、周波数９．３ＧＨｚ〜１０．７ＧＨｚにおいて、分配損失として（３．０５±０．０５）ｄＢ、入力反射量として−２０ｄＢ以下、アイソレーションとして２０ｄＢ以上の特性が得られていることがわかる。
なお、図２２に示す従来例の偶高調波ミキサの場合、キャパシタ２０８として同じ条件では１０ｐＦ程度の容量が必要になるが、キャパシタ４１〜４３の合計の容量は１．３８ｐＦであり、図５の電力分配合成回路を用いた方が回路全体をより小型化できる。
【００６３】
（本発明に関連する電力分配合成回路の例）
本発明に関連する電力分配合成回路について、図９〜図１２を参照して説明する。
図９はこの電力分配合成回路の構成を示すブロック図である。図１０は図９の電力分配合成回路を入出力端子１２，１３から同相励振する場合の等価回路図である。図１１は図９の電力分配合成回路を入出力端子１２，１３から逆相励振する場合の等価回路図である。図１２はこの形態の電力分配合成回路の周波数特性を示すグラフである。
【００６４】
図９の電力分配合成回路は、第１の実施の形態の変形例である。図９〜図１２において、第１の実施の形態と対応する要素は同一の符号を付けて示してある。
【００６５】
図９を参照すると、この電力分配合成回路は入出力端子１１，１２，１３，分布定数線路１４，１５，抵抗素子１６，キャパシタ５１，５２，５３を備えている。２つの分布定数線路１４，１５の特性は同一であり、２つのキャパシタ５１，５２の特性も同一である。キャパシタ５３は抵抗素子１６と直列に接続されている。
【００６６】
ここでは、キャパシタ５１，５２の容量をＣ１で表し、キャパシタ５３の容量をＣ２で表す。また、抵抗素子１６の抵抗値はＲで表す。さらに、分布定数線路１４，１５の特性については、特定の周波数ｆ_０における電気長をＥ１で表し、特性インピーダンスをＺ_１で表す。また、入出力端子１１，１２，１３にそれぞれ接続される負荷インピーダンスはＺ_０で表す。
【００６７】
図９の電力分配合成回路に必要とされる機能を想定すると、入出力端子１１に入力された信号は２つに分配されて入出力端子１２，１３に出力される。従って、入出力端子１２の信号と入出力端子１３の信号とは同相になる。
そこで、図９の電力分配合成回路を入出力端子１２，１３から同相励振する場合を考えると、図９の電力分配合成回路は図１０の等価回路で表すことができる。図１０において、キャパシタ５４の容量はＣ１になる。分布定数線路５５の特性は分布定数線路１４，１５と同一である。ここでは、入出力端子１１，１２，１３に負荷インピーダンスＺ_０が接続された場合を想定している。
【００６８】
また、図９の電力分配合成回路においては、例えば反射信号として入出力端子１２に入力された信号が入出力端子１３に現れないように入出力端子１２と入出力端子１３との間のアイソレーションを確保する必要がある。この場合、入力された反射信号を抵抗素子１６で全て吸収すれば、入出力端子１２と入出力端子１３との間のアイソレーションを確保することができる。
【００６９】
そこで、図９の電力分配合成回路を入出力端子１２，１３から逆相励振する場合を考えると、図９の電力分配合成回路は図１１の等価回路で表すことができる。図１１において、抵抗５８の抵抗値は（Ｒ／２）になり、キャパシタ５９の容量は（２・Ｃ２）になり、キャパシタ５６の容量はＣ１になる。また、分布定数線路５７の特性は分布定数線路１４，１５と同一になる。ここでは、入出力端子１１，１２，１３に負荷インピーダンスＺ_０が接続された場合を想定している。
【００７０】
従って、図９の電力分配合成回路において周波数ｆ_０で入出力端子１１〜１３の入出力を整合させるための条件、ならびに入出力端子１１と入出力端子１２，１３との間で信号を均等に分配・合成するために必要な条件は、図１０の等価回路に基づいて求めることができる。これらの条件は、次の第（９）式及び第（１０）式で表される。
【数５】

また、図９の電力分配合成回路において入出力端子１２と入出力端子１３との間のアイソレーションを確保するために必要な条件は図１１の等価回路に基づいて求めることができる。この条件は、次の第（１１）式及び第（１２）式で表される。
【数６】

すなわち、上記第（９）式〜第（１２）式の全ての条件を満たすように各構成要素の特性Ｅ１，Ｃ１，Ｃ２，Ｒ，Ｚ_１を決定すれば、必要とされる電力分配合成回路の機能を実現することができる。
【００７１】
この場合、入出力端子１１から高周波信号を入力すると、１／２ずつに分配された高周波信号が入出力端子１２及び入出力端子１３から同相で出力される。また、入出力端子１２から高周波信号を入力した場合、入出力端子１３では抵抗素子１６を通過した高周波信号と分布定数線路１４，１５を通過した高周波信号とが等振幅かつ逆相で合成されるため、入出力端子１３には信号が現れない。
【００７２】
特定の条件を想定して具体的な計算を行った。その結果は次の通りである。
分布定数線路１４，１５の電気長Ｅ１：６０度
周波数ｆ_０：１０ＧＨｚ
負荷インピーダンスＺ_０：５０Ω
特性インピーダンスＺ_１：８６．６Ω
容量Ｃ１：０．３２ｐＦ
容量Ｃ２：０．３２ｐＦ
抵抗値Ｒ：５０Ω
以上の条件で構成される図９の電力分配合成回路の周波数特性を数値シミュレーションで求めた結果、図１２に示す周波数特性が得られた。
【００７３】
図１２を参照すると、周波数９．４ＧＨｚ〜１１．０ＧＨｚにおいて、分配損失として（３．０５±０．０５）ｄＢ、入力反射量として−２０ｄＢ以下、アイソレーションとして２０ｄＢ以上の特性が得られていることがわかる。
なお、図２２に示す従来例の偶高調波ミキサの場合、キャパシタ２０８として同じ条件では１０ｐＦ程度の容量が必要になるが、キャパシタ４１〜４３の合計の容量は０．９６ｐＦであり、図９の電力分配合成回路を用いた方が回路全体をより小型化できる。
【００７４】
（第３の実施の形態）
本発明の電力分配合成回路の１つの実施の形態について、図１３〜図１６を参照して説明する。この形態は請求項３に対応する。
図１３はこの形態の電力分配合成回路の構成を示すブロック図である。図１４は図１３の電力分配合成回路を入出力端子１２，１３から同相励振する場合の等価回路図である。図１５は図１３の電力分配合成回路を入出力端子１２，１３から逆相励振する場合の等価回路図である。図１６はこの形態の電力分配合成回路の周波数特性を示すグラフである。
【００７５】
この形態は第１の実施の形態の変形例である。図１３〜図１６において、第１の実施の形態と対応する要素は同一の符号を付けて示してある。第１の実施の形態と同一の部分については、以下の説明を省略する。
この形態では、請求項３の第１の端子，第２の端子，第３の端子，第１のインダクタ，第１のキャパシタ，第２のキャパシタ，抵抗素子，第２のインダクタ及び第３のキャパシタは、それぞれ入出力端子１１，１２，１３，インダクタ６４，キャパシタ６１，キャパシタ６２，抵抗素子１６，インダクタ６５及びキャパシタ６３に対応する。
【００７６】
図１３を参照すると、この電力分配合成回路は入出力端子１１，１２，１３，キャパシタ６１，６２，６３，インダクタ６４，６５及び抵抗素子１６を備えている。２つのキャパシタ６１，６２の特性は同一である。抵抗素子１６，インダクタ６５，キャパシタ６３は直列に接続されている。
ここでは、キャパシタ６１，６２の容量をＣ１で表し、キャパシタ６３の容量をＣ２で表す。また、抵抗素子１６の抵抗値はＲで表す。さらに、インダクタ６４のインダクタンスをＬ１で表し、インダクタ６５のインダクタンスをＬ２で表す。また、入出力端子１１，１２，１３にそれぞれ接続される負荷インピーダンスはＺ_０で表す。
【００７７】
図１３の電力分配合成回路に必要とされる機能を想定すると、入出力端子１１に入力された信号は２つに分配されて入出力端子１２，１３に出力される。従って、入出力端子１２の信号と入出力端子１３の信号とは同相になる。
そこで、図１３の電力分配合成回路を入出力端子１２，１３から同相励振する場合を考えると、図１３の電力分配合成回路は図１４の等価回路で表すことができる。図１４において、キャパシタ６７の容量はＣ１になる。インダクタ６６のインダクタンスは（２・Ｌ１）になる。ここでは、入出力端子１１，１２，１３に負荷インピーダンスＺ_０が接続された場合を想定している。
【００７８】
また、図１３の電力分配合成回路においては、例えば反射信号として入出力端子１２に入力された信号が入出力端子１３に現れないように入出力端子１２と入出力端子１３との間のアイソレーションを確保する必要がある。この場合、入力された反射信号を抵抗素子１６で全て吸収すれば、入出力端子１２と入出力端子１３との間のアイソレーションを確保することができる。
【００７９】
そこで、図１３の電力分配合成回路を入出力端子１２，１３から逆相励振する場合を考えると、図１３の電力分配合成回路は図１５の等価回路で表すことができる。図１５において、抵抗７２の抵抗値は（Ｒ／２）になり、キャパシタ７４の容量は（２・Ｃ２）になり、キャパシタ７１の容量はＣ１になり、インダクタ７３のインダクタンスは（Ｌ２／２）になる。ここでは、入出力端子１１，１２，１３に負荷インピーダンスＺ_０が接続された場合を想定している。
【００８０】
従って、図１３の電力分配合成回路において周波数ｆ_０で入出力端子１１〜１３の入出力を整合させるための条件、ならびに入出力端子１１と入出力端子１２，１３との間で信号を均等に分配・合成するために必要な条件は、図１４の等価回路に基づいて求めることができる。これらの条件は、次の第（１３）式及び第（１４）式で表される。
【数７】

また、図１３の電力分配合成回路において入出力端子１２と入出力端子１３との間のアイソレーションを確保するために必要な条件は図１５の等価回路に基づいて求めることができる。この条件は、次の第（１５）式及び第（１６）式で表される。
【数８】

すなわち、上記第（１３）式〜第（１６）式の全ての条件を満たすように各構成要素の特性Ｌ１，Ｌ２，Ｃ１，Ｃ２，Ｒを決定すれば、必要とされる電力分配合成回路の機能を実現することができる。
【００８１】
この場合、入出力端子１１から高周波信号を入力すると、１／２ずつに分配された高周波信号が入出力端子１２及び入出力端子１３から同相で出力される。また、入出力端子１２から高周波信号を入力した場合、入出力端子１３では抵抗素子１６を通過した高周波信号とキャパシタ６１，６２を通過した高周波信号とが等振幅かつ逆相で合成されるため、入出力端子１３には信号が現れない。
【００８２】
特定の条件を想定して具体的な計算を行った。その結果は次の通りである。
周波数ｆ_０：１ＧＨｚ
負荷インピーダンスＺ_０：５０Ω
容量Ｃ１：３．１８ｐＦ
容量Ｃ２：３．１８ｐＦ
抵抗値Ｒ：５０Ω
インダクタンスＬ１：７．９６ｎＨ
インダクタンスＬ２：１５．９ｎＨ（＝Ｚ_０／πｆ_０）
以上の条件で構成される図１３の電力分配合成回路の周波数特性を数値シミュレーションで求めた結果、図１６に示す周波数特性が得られた。
【００８３】
図１６を参照すると、周波数０．９１ＧＨｚ〜１．１０ＧＨｚにおいて、分配損失として（３．０５±０．０５）ｄＢ、入力反射量として−２０ｄＢ以下、アイソレーションとして２０ｄＢ以上の特性が得られていることがわかる。
（第４の実施の形態）
本発明の電力分配合成回路の１つの実施の形態について、図１７〜図２０を参照して説明する。この形態は請求項４に対応する。
【００８４】
図１７はこの形態の電力分配合成回路の構成を示すブロック図である。図１８は図１７の電力分配合成回路を入出力端子１２，１３から同相励振する場合の等価回路図である。図１９は図１７の電力分配合成回路を入出力端子１２，１３から逆相励振する場合の等価回路図である。図２０はこの形態の電力分配合成回路の周波数特性を示すグラフである。
【００８５】
この形態は第１の実施の形態の変形例である。図１７〜図２０において、第１の実施の形態と対応する要素は同一の符号を付けて示してある。第１の実施の形態と同一の部分については、以下の説明を省略する。
この形態では、請求項４の第１の端子，第２の端子，第３の端子，第１のキャパシタ，第２のキャパシタ，第３のキャパシタ，第１のインダクタ，第２のインダクタ及び抵抗素子は、それぞれ入出力端子１１，１２，１３，キャパシタ８１，８４，８５，インダクタ８２，８３及び抵抗素子１６に対応する。
【００８６】
図１７を参照すると、この電力分配合成回路は入出力端子１１，１２，１３，キャパシタ８１，８４，８５，インダクタ８２，８３及び抵抗素子１６を備えている。２つのキャパシタ８４，８５の特性は同一である。また、２つのインダクタ８２，８３の特性も同一である。
ここでは、キャパシタ８１の容量をＣ１で表し、キャパシタ８４，８５の容量をＣ２で表す。また、抵抗素子１６の抵抗値はＲで表す。さらに、インダクタ８２，８３のインダクタンスをＬで表す。また、入出力端子１１，１２，１３にそれぞれ接続される負荷インピーダンスはＺ_０で表す。
【００８７】
図１７の電力分配合成回路に必要とされる機能を想定すると、入出力端子１１に入力された信号は２つに分配されて入出力端子１２，１３に出力される。従って、入出力端子１２の信号と入出力端子１３の信号とは同相になる。
そこで、図１７の電力分配合成回路を入出力端子１２，１３から同相励振する場合を考えると、図１７の電力分配合成回路は図１８の等価回路で表すことができる。図１８において、キャパシタ８６の容量は（Ｃ１／２）になり、キャパシタ８８の容量はＣ２になる。インダクタ８７のインダクタンスは（Ｌ）になる。ここでは、入出力端子１１，１２，１３に負荷インピーダンスＺ_０が接続された場合を想定している。
【００８８】
また、図１７の電力分配合成回路においては、例えば反射信号として入出力端子１２に入力された信号が入出力端子１３に現れないように入出力端子１２と入出力端子１３との間のアイソレーションを確保する必要がある。この場合、入力された反射信号を抵抗素子１６で全て吸収すれば、入出力端子１２と入出力端子１３との間のアイソレーションを確保することができる。
【００８９】
そこで、図１７の電力分配合成回路を入出力端子１２，１３から逆相励振する場合を考えると、図１７の電力分配合成回路は図１９の等価回路で表すことができる。図１９において、抵抗９２の抵抗値は（Ｒ／２）になり、キャパシタ９３の容量はＣ２になり、インダクタ９１のインダクタンスはＬになる。ここでは、入出力端子１１，１２，１３に負荷インピーダンスＺ_０が接続された場合を想定している。
【００９０】
従って、図１７の電力分配合成回路において周波数ｆ_０で入出力端子１１〜１３の入出力を整合させるための条件、ならびに入出力端子１１と入出力端子１２，１３との間で信号を均等に分配・合成するために必要な条件は、図１８の等価回路に基づいて求めることができる。これらの条件は、次の第（１７）式及び第（１８）式で表される。
【数９】

また、図１７の電力分配合成回路において入出力端子１２と入出力端子１３との間のアイソレーションを確保するために必要な条件は図１９の等価回路に基づいて求めることができる。この条件は、次の第（１９）式及び第（２０）式で表される。
【数１０】

従って、上記第（１７）式〜第（２０）式に基づいて、次の第（２１）式のように各構成要素の特性を決定すれば、必要とされる電力分配合成回路の機能を実現することができる。
【数１１】

この場合、入出力端子１１から高周波信号を入力すると、１／２ずつに分配された高周波信号が入出力端子１２及び入出力端子１３から同相で出力される。また、入出力端子１２から高周波信号を入力した場合、入出力端子１３では抵抗素子１６を通過した高周波信号とインダクタ８２，８３を通過した高周波信号とが等振幅かつ逆相で合成されるため、入出力端子１３には信号が現れない。
【００９１】
特定の条件を想定して具体的な計算を行った。その結果は次の通りである。
周波数ｆ_０：１ＧＨｚ
負荷インピーダンスＺ_０：５０Ω
容量Ｃ１：３．１８ｐＦ
容量Ｃ２：３．１８ｐＦ
抵抗値Ｒ：２００Ω
インダクタンスＬ：１５．９ｎＨ
以上の条件で構成される図１７の電力分配合成回路の周波数特性を数値シミュレーションで求めた結果、図２０に示す周波数特性が得られた。
【００９２】
図２０を参照すると、周波数０．９４ＧＨｚ〜１．０６ＧＨｚにおいて、分配損失として（３．０５±０．０５）ｄＢ、入力反射量として−２０ｄＢ以下、アイソレーションとして２０ｄＢ以上の特性が得られていることがわかる。
なお、上記の５つの実施の形態以外の構成であっても本発明の電力分配合成回路を構成することは可能である。例えば、回路に接続するキャパシタやインダクタの接続位置を変更したり、回路に接続する構成要素の数をさらに増やすこともできる。
【００９３】
【発明の効果】
本発明によれば、例えば図４，図８，図１２，図１６，図２０の特性から明らかなように電力分配合成回路においてベースバンド信号を阻止することができるので、ベースバンド信号を阻止するためのキャパシタをミキサ回路に設ける必要がなく、回路全体の小型化が可能になる。従って、特にチップ面積の小型化が要求されるモノリシックマイクロ波集積回路への適用に本発明は有効である。
【図面の簡単な説明】
【図１】第１の実施の形態の電力分配合成回路の構成を示すブロック図である。
【図２】図１の電力分配合成回路を入出力端子１２，１３から同相励振する場合の等価回路図である。
【図３】図１の電力分配合成回路を入出力端子１２，１３から逆相励振する場合の等価回路図である。
【図４】第１の実施の形態の電力分配合成回路の周波数特性を示すグラフである。
【図５】第２の実施の形態の電力分配合成回路の構成を示すブロック図である。
【図６】図５の電力分配合成回路を入出力端子１２，１３から同相励振する場合の等価回路図である。
【図７】図５の電力分配合成回路を入出力端子１２，１３から逆相励振する場合の等価回路図である。
【図８】第２の実施の形態の電力分配合成回路の周波数特性を示すグラフである。
【図９】本発明に関連する電力分配合成回路の構成を示すブロック図である。
【図１０】図９の電力分配合成回路を入出力端子１２，１３から同相励振する場合の等価回路図である。
【図１１】図９の電力分配合成回路を入出力端子１２，１３から逆相励振する場合の等価回路図である。
【図１２】本発明に関連する電力分配合成回路の周波数特性を示すグラフである。
【図１３】第３の実施の形態の電力分配合成回路の構成を示すブロック図である。
【図１４】図１３の電力分配合成回路を入出力端子１２，１３から同相励振する場合の等価回路図である。
【図１５】図１３の電力分配合成回路を入出力端子１２，１３から逆相励振する場合の等価回路図である。
【図１６】第３の実施の形態の電力分配合成回路の周波数特性を示すグラフである。
【図１７】第４の実施の形態の電力分配合成回路の構成を示すブロック図である。
【図１８】図１７の電力分配合成回路を入出力端子１２，１３から同相励振する場合の等価回路図である。
【図１９】図１７の電力分配合成回路を入出力端子１２，１３から逆相励振する場合の等価回路図である。
【図２０】第４の実施の形態の電力分配合成回路の周波数特性を示すグラフである。
【図２１】偶高調波ミキサを用いたホモダイン形式の受信機の構成を示すブロック図である。
【図２２】従来例の偶高調波ミキサの構成を示すブロック図である。
【図２３】従来例の電力分配合成回路の構成を示すブロック図である。
【符号の説明】
１１，１２，１３ 入出力端子
１４，１５ 分布定数線路
１６ 抵抗素子
１７，１８，１９ キャパシタ
２１，２２，３２ 端子
２３，２４，３５ キャパシタ
２５，３３ 分布定数線路
３４ 抵抗
４１，４２，４３，４４，４５，４９ キャパシタ
４６ 分布定数線路
４８ 抵抗
５１，５２，５３，５４，５６，５９ キャパシタ
５５，５７ 分布定数線路
５８ 抵抗
６１，６２，６３，６７，７１，７４ キャパシタ
６４，６５，６６，７３ インダクタ
７２ 抵抗
８１，８４，８５，８６，８８，９３ キャパシタ
８２，８３，８７，９１ インダクタ
９２ 抵抗
２００ａ，２００ｂ ミキサダイオード
２０１ アンチパラレルダイオードペア
２０２ ＲＦ端子
２０３ ＬＯ端子
２０４ ベースバンド端子
２０５ 先端開放スタブ
２０６ 先端短絡スタブ
２０７ 高周波信号阻止用のインダクタ
２０８ ベースバンド信号阻止用のキャパシタ
２１１ 空中線
２１２ 低雑音増幅回路
２１３ 帯域通過フィルタ
２１４ ０度電力分配合成回路
２１５ａ，２１５ｂ 偶高調波ミキサ
２１６ ４５度電力分配合成回路
２１７ 偶高調波直交ミキサ
２１８ 局部発振回路
２１９ａ，２１９ｂ 低域通過フィルタ
２２０ａ，２２０ｂ ベースバンド増幅回路
２２１ 復調回路
２３１，２３２，２３３ 入出力端子
２３４ 抵抗素子
２３５，２３６ 分布定数線路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a power distribution / synthesis circuit that handles a high-frequency signal and a baseband signal, and particularly includes a first terminal, a second terminal, and a third terminal, and converts a signal input to the first terminal into two systems. A power distribution / combination circuit that distributes and outputs the signals to the second terminal and the third terminal, or combines the signals input to the second and third terminals and outputs the combined signal to the first terminal About.
[0002]
[Prior art]
A mixer (mixer) used for frequency conversion and detection of a signal in a wireless device or the like mixes a local oscillation wave output from a local oscillator with a signal wave. A mixer called an even harmonic mixer outputs a mixed wave of a second harmonic of a local oscillation wave (a component whose frequency is twice the fundamental wave) and a signal wave. The even harmonic mixer can suppress even harmonics of the local oscillation wave.
[0003]
Various configurations of the even harmonic mixer have been reported before. For example, the even harmonic mixer of the conventional example shown in FIG. 22 is described in pages 879 to 882 of “1991 MTT-S Digest” of “International Microwave Symposium” sponsored by IEEE, which was held in Boston in June 1991. Have been.
Referring to FIG. 22, an anti-parallel diode pair (APDP) 201 included in the even harmonic mixer includes mixer diodes 200a and 200b having opposite polarities connected in parallel.
[0004]
The RF terminal 202 has a frequency of f_rfIs input. LO terminal 203 has frequency f_pIs input. Further, a baseband signal which is a mixed output is output to the baseband terminal 204.
The RF terminal 202 is connected to one end (A end) of the APDP 201 via a capacitor 208 for blocking a baseband signal. The baseband terminal 204 is connected to one end (A end) of the APDP 201 via an inductor 207 for blocking a high-frequency signal. The LO terminal 203 is connected to the other end (B end) of the APDP 201.
[0005]
The even harmonic mixer shown in FIG. 22 uses an open-end stub 205 connected to the A-end of the APDP 201 and a short-circuited stub 206 connected to the B-end of the APDP 201 to obtain a frequency f._pSignal and frequency f_rf(= 2f_p) Is configured to split the signal.
The even harmonic mixer in FIG. 22 is used, for example, in a homodyne receiver shown in FIG. In this receiver, the signal wave received by the antenna 211 is amplified by the low-noise amplifier circuit 212, and is input to the even harmonic quadrature mixer 217 through the band-pass filter 213. The even harmonic orthogonal mixer 217 detects a signal wave based on the local oscillation wave, and outputs a modulated signal component of the signal wave as an I signal and a Q signal.
[0006]
The even harmonic quadrature mixer 217 includes a 0-degree power distribution / synthesis circuit 214 that distributes the output of the band-pass filter 213 into two with equal phase and equal amplitude, and a unit with 45-degree equal amplitude when receiving a local oscillation wave from outside. A 45-degree power distribution / synthesis circuit 216 for distributing the signals into two signals having a phase difference, and even harmonic mixers 215a and 215b for mixing the distributed signal wave and the local oscillation wave to output an I signal and a Q signal, respectively; It has. As the even harmonic mixers 215a and 215b, the same mixers as in FIG. 22 can be used.
[0007]
Here, the 45-degree power distribution / combination circuit 216 generates a 45-degree phase difference, but the phase difference of the second harmonic of the local oscillation wave applied from the local oscillation circuit 218 to the even harmonic mixers 215a and 215b is: It becomes 90 degrees which is twice the phase difference of 45 degrees.
The I signal and the Q signal output from the even harmonic quadrature mixer 217 pass through low-pass filters 219a and 219b, respectively, are amplified by the baseband amplifier circuits 220a and 220b, input to the demodulation circuit 221, and are input to the demodulation circuit 221. The data is demodulated.
[0008]
The operation of the even harmonic mixers 215a and 215b will be described with reference to FIG.
The open-end stub 205 and the short-circuited stub 206 of the even harmonic mixers 215a and 215b have a frequency f_p概略 wavelength, ie, the frequency f_rfIs designed to be approximately 波長 wavelength with respect to.
[0009]
The open-end stub 205 is connected to a terminal on the A-end side of the APDP 201. Near DC (direct current) and f_rf(= 2f_pAt a frequency near), the open end stub 205 has a high impedance, so that the APDP 201 is connected to the RF terminal 202 and the baseband terminal 204, respectively.
On the other hand, the frequency f_p, The open end stub 205 has a low impedance, so that the A-end side of the APDP 201 is grounded.
[0010]
Conversely, the tip short-circuit stub 206 connected to the B-end side of the APDP 201_rfThe impedance becomes low at a frequency in the vicinity. Therefore, the vicinity of DC and f_rfAt the nearby frequency, the B-end side of the APDP 201 is grounded.
Further, the tip short-circuit stub 206 is f_pSince the impedance becomes high at a nearby frequency, f_pAt the nearby frequency, the B terminal side of the APDP 201 is connected to the LO terminal 203.
[0011]
In the even harmonic mixers 215a and 215b, when a local oscillation wave is supplied to the LO terminal 203, the mixer diodes 200a and 200b are turned on every half cycle, and current flows. Therefore, the APDP 201 operates so that the conductivity (conductance) increases every half cycle of the local oscillation wave.
For this reason, when a mixer is configured using the APDP 201, the APDP 201 appears to be modulated by an even harmonic of the local oscillation wave, so that the second harmonic of the local oscillation wave (2f_p) And the signal wave (f_rf) Is mixed with f_pAnd f_rfIs suppressed.
[0012]
In such an even harmonic mixer, even-order harmonics of the local oscillation wave can be suppressed only by the balance of the two diodes, so that a much higher suppression can be achieved as compared with a normal balanced mixer.
By the way, as the 0-degree power distribution / combination circuit 214 in FIG. 21, a power distribution / combination circuit combining distributed constant lines as shown in FIG. 23 is generally used. Such a power distribution and synthesis circuit is described, for example, in "RK Gupta et al .:" Quasi-lumped-element 3-and 4-port networks for MIC and MMIC applications ", 1984 IEEE MTT e-Stipe. , 409-411. "Shows the basic operation principle.
[0013]
23 includes input / output terminals 231, 232, and 233, a resistance element 234 (resistance value is R), and distributed constant lines 235 and 236. The distributed constant lines 235 and 236 have the frequency f₀Has an electrical length of 90 degrees.
Here, the load impedance connected to the input / output terminals 231 to 233 is Z₀, The frequency f₀, The input / output matching conditions at the input / output terminals 231 to 233 are satisfied, and the distribution / synthesis ratio between the input / output terminals 231 and 232 and the input / output terminals 231 and 233 is made equal. In this case, the characteristic impedance of the high-frequency transmission lines 235 and 236 is (Z₀× (square root of 2)).
[0014]
In this case, when a high-frequency signal is input from the input / output terminal 231, the high-frequency signal divided into ず つ is output from the input / output terminal 232 and the input / output terminal 233 in the same phase.
Also, the frequency f₀In order to satisfy the isolation condition between the input / output terminal 232 and the input / output terminal 233 in the above, the resistance value R of the resistance element 234 is (2Z₀).
[0015]
In this case, when a high-frequency signal is input from the input / output terminal 232, the high-frequency signal passing through the resistance element 234 having the resistance value R and the high-frequency signal passing through the distributed constant line 235 and the distributed constant line 236 have the same amplitude at the input / output terminal 233. In addition, since the signals are combined in the opposite phases, no signal appears at the input / output terminal 233.
[0016]
[Problems to be solved by the invention]
By the way, since the conventional power distribution / synthesis circuit combining distributed constant lines as shown in FIG. 23 does not have a function of blocking a baseband signal, the even harmonic mixer shown in FIG. It was necessary to block the baseband signal.
[0017]
That is, it is necessary to sufficiently increase the impedance of the capacitor 208 for the baseband signal to prevent the baseband signal from being input to the power distribution / synthesis circuit.
However, it is necessary to sufficiently reduce the impedance of the capacitor 208 so that a high-frequency signal input from the power distribution / synthesis circuit to the even harmonic mixer is not attenuated by passing through the capacitor 208.
[0018]
Actually, since the frequency of the high-frequency signal to be handled is much higher than that of the baseband signal, the baseband signal can be blocked even if the capacitance of the capacitor 208 is made sufficiently large to reduce the impedance to the high-frequency signal. .
Therefore, a large-capacity capacitor has conventionally been used as the capacitor 208 in order to prevent attenuation of the high-frequency signal. However, since a large-capacity capacitor is large, using it makes it difficult to reduce the circuit size of the receiver.
[0019]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a power distribution / combination circuit useful for downsizing an even harmonic mixer.
[0023]
[Means for Solving the Problems]
Claim 1 describes the load impedance Z.₀Has a first terminal, a second terminal, and a third terminal respectively connected thereto, and divides a signal input to the first terminal into two systems, and distributes the signal to the second terminal and the third terminal. A power distribution / synthesis circuit that outputs or combines signals input to the second terminal and the third terminal and outputs the combined signal to the first terminal, one end of which is connected to the first terminal. A first capacitor (capacitance C1) and a first distributed constant line (specific frequency f 1) having one end electrically connected to the other end of the first capacitor.₀SmellRudenTemperament is E1, characteristic impedance is Z₁) And a second distributed constant line (one end of which is electrically connected to the other end of the first capacitor).₀SmellRudenTemperament is E1, characteristic impedance is Z₁), A resistance element (resistance R) for electrically connecting the other end of the first distributed constant line and the other end of the second distributed constant line, and the other end of the first distributed constant line. A second capacitor (capacitance C2) for connecting to the second terminal; and a third capacitor (capacitance C2) for connecting the other end of the second distributed constant line to the third terminal. ,The specific frequency f ₀ A condition for matching input and output of the first terminal, the second terminal, and the third terminal, and a condition between the first terminal and the second terminal, and the first terminal and the second terminal. The conditions for uniformly distributing and synthesizing the signal between the third terminals are expressed by the following equations (1) and (2).
(Equation 3)

And the condition for ensuring the isolation between the second terminal and the third terminal is expressed by the following equations (3) and (4).
(Equation 4)

And the capacitances C1 and C2, the electrical length E1, the resistance value R, and the characteristic impedance Z ₁ Between Equations (1) to (4)It is characterized by being established.
[0024]
Claim1AtIs theSince the first capacitor, the second capacitor, and the third capacitor are provided, the transfer characteristic between the terminals of the power distribution / synthesis circuit changes according to the frequency. With this frequency characteristic, transmission of a baseband signal between the second terminal and the third terminal can be prevented.
Further, by determining the characteristics of the first capacitor, the second capacitor, the third capacitor, and other elements so as to satisfy a predetermined condition, input and output between the terminals are matched, and furthermore, between the terminals. Signal distribution and synthesis can be performed.
[0025]
When this power distribution / combination circuit is used in a receiver or the like, it is not necessary to provide a function of blocking a baseband signal in the even harmonic mixer, and the even harmonic mixer can be downsized. Actually, the total capacitance of the first capacitor, the second capacitor, and the third capacitor provided in the power distribution / synthesis circuit can be made sufficiently smaller than that of the capacitor 208 in FIG. The size can be reduced.
[0026]
Claim2Comprises a first terminal, a second terminal, and a third terminal, distributes a signal input to the first terminal to two systems, and outputs the divided signals to the second terminal and the third terminal; Or a power distribution / combination circuit that combines signals input to the second terminal and the third terminal and outputs the combined signal to the first terminal, one end of which is connected to the first terminal; , A first distributed constant line having one end electrically connected to the first terminal, and a second distribution line having one end electrically connected to the first terminal. A constant line, a resistance element that electrically connects the other end of the first distributed constant line and the other end of the second distributed constant line, and a second end of the first distributed constant line and the second end of the second distributed constant line. A second capacitor connecting the second terminal to the third terminal; and a second capacitor connecting the other terminal of the second distributed constant line to the third terminal. Characterized by providing a Yapashita.
[0027]
Claim2AtIs theSince the first capacitor, the second capacitor, and the third capacitor are provided, the transfer characteristic between the terminals of the power distribution / synthesis circuit changes according to the frequency. With this frequency characteristic, transmission of a baseband signal between the second terminal and the third terminal can be prevented.
Further, by determining the characteristics of the first capacitor, the second capacitor, the third capacitor, and other elements so as to satisfy a predetermined condition, input and output between the terminals are matched, and furthermore, between the terminals. Signal distribution and synthesis can be performed.
[0028]
When this power distribution / combination circuit is used in a receiver or the like, it is not necessary to provide a function of blocking a baseband signal in the even harmonic mixer, and the even harmonic mixer can be downsized. Actually, the total capacitance of the first capacitor, the second capacitor, and the third capacitor provided in the power distribution / synthesis circuit can be made sufficiently smaller than that of the capacitor 208 in FIG. The size can be reduced.
[0032]
Claim3Comprises a first terminal, a second terminal, and a third terminal, distributes a signal input to the first terminal to two systems, and outputs the divided signals to the second terminal and the third terminal; Or a power distribution / combination circuit that combines signals input to the second terminal and the third terminal and outputs the combined signal to the first terminal, wherein one end is connected to the first terminal and the other end is Is connected to the first terminal, one end is connected to the first terminal, the other end is connected to the first capacitor connected to the second terminal, one end is connected to the first terminal, The other end includes a second capacitor connected to the third terminal, a series circuit of a resistor, a second inductor, and a third capacitor, one end connected to the second terminal, and the other end connected. And a resistor circuit connected to the third terminal.
[0033]
Claim3In the method, the signal input to the first terminal is distributed to two systems and output to the second terminal and the third terminal, or the signal input to the second terminal and the third terminal A signal can be synthesized and output to the first terminal.
In addition, since a series circuit of the resistance element, the second inductor, and the third capacitor forms a resonance circuit, the transfer characteristics between the terminals of the power distribution and synthesis circuit change according to the frequency. With this frequency characteristic, transmission of a baseband signal between the second terminal and the third terminal can be prevented.
[0034]
Furthermore, by defining the characteristics of each element so as to satisfy a predetermined condition, it is possible to match input / output characteristics between the terminals and to realize a function of distributing and synthesizing signals between the terminals. When this power distribution / combination circuit is used in a receiver or the like, it is not necessary to provide a function of blocking a baseband signal in the even harmonic mixer, and the even harmonic mixer can be downsized.
[0035]
Actually, the total capacitance of the first capacitor, the second capacitor, and the third capacitor provided in the power distribution / synthesis circuit can be made sufficiently smaller than that of the capacitor 208 in FIG. The size can be reduced.
Claim4Comprises a first terminal, a second terminal, and a third terminal, distributes a signal input to the first terminal to two systems, and outputs the divided signals to the second terminal and the third terminal; Or a power distribution / combination circuit that combines signals input to the second terminal and the third terminal and outputs the combined signal to the first terminal, wherein one end is connected to the first terminal and the other end is , A first capacitor having one end connected to the second terminal, a third capacitor having one end connected to the third terminal, and a first capacitor having one end connected to the first terminal. A first inductor connected to a terminal and the other end connected to the other end of the second capacitor; one end connected to the first terminal; and another end connected to the other end of the third capacitor Second inductor, the other end of the first inductor, and the other end of the second inductor Characterized by providing a resistance element connected between the.
[0036]
Claim4In the method, the signal input to the first terminal is distributed to two systems and output to the second terminal and the third terminal, or the signal input to the second terminal and the third terminal A signal can be synthesized and output to the first terminal.
The transfer characteristics between the terminals of the power distribution / synthesis circuit change according to the frequency. With this frequency characteristic, transmission of a baseband signal between the second terminal and the third terminal can be prevented.
[0037]
Further, by defining the characteristics of each element so as to satisfy a predetermined condition, the input / output characteristics between the terminals can be matched, and the function of distributing and synthesizing signals between the terminals can be realized. When this power distribution / combination circuit is used in a receiver or the like, it is not necessary to provide a function of blocking a baseband signal in the even harmonic mixer, and the even harmonic mixer can be downsized.
[0038]
Actually, the total capacitance of the first capacitor, the second capacitor, and the third capacitor provided in the power distribution / synthesis circuit can be made sufficiently smaller than that of the capacitor 208 in FIG. The size can be reduced.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
(First Embodiment)
One embodiment of a power distribution / synthesis circuit according to the present invention will be described with reference to FIGS. This form is claimedIn oneCorresponding.
[0040]
FIG. 1 is a block diagram showing a configuration of a power distribution / synthesis circuit of this embodiment. FIG. 2 is an equivalent circuit diagram when the power distribution / synthesis circuit of FIG. FIG. 3 is an equivalent circuit diagram when the power distribution / synthesis circuit of FIG. FIG. 4 is a graph showing frequency characteristics of the power distribution / synthesis circuit of this embodiment.
[0041]
In this form, the claimOneThe first terminal, the second terminal, the third terminal, the first distributed constant line, the second distributed constant line, and the resistance element are respectively an input / output terminal 11, an input / output terminal 12, an input / output terminal 13, It corresponds to the constant line 14, the distributed constant line 15, and the resistance element 16.
MaWasClaim1, The first capacitor, the second capacitor, and the third capacitor correspond to the capacitor 17, the capacitor 18, and the capacitor 19, respectively.
[0042]
The power distribution / combination circuit of this embodiment can be used as the 0-degree power distribution / combination circuit 214 when configuring a receiver as shown in FIG. 21, for example. However, since the power distribution / combination circuit of this embodiment has a function of blocking the baseband signal itself, the even harmonic mixer connected to the power distribution / combination circuit has a function of blocking the baseband signal (see FIG. 22). There is no need to provide the capacitor 208).
[0043]
Referring to FIG. 1, this power distribution / synthesis circuit includes input / output terminals 11, 12, and 13, distributed constant lines and 15, a resistance element 16, and capacitors 17, 18, and 19. However, the characteristics of the two distributed constant lines 14 and 15 are the same, and the characteristics of the two capacitors 18 and 19 are also the same.
Here, the capacitance of the capacitor 17 is represented by C1, and the capacitances of the capacitors 18, 19 are represented by C2. The resistance value of the resistance element 16 is represented by R. Further, regarding the characteristics of the distributed constant lines 14 and 15, the specific frequency f₀Is represented by E1, and the characteristic impedance is represented by Z₁Expressed by The load impedance connected to the input / output terminals 11, 12, and 13 is Z₀Expressed by
[0044]
Assuming the functions required for the power distribution / synthesis circuit of FIG. 1, the signal input to the input / output terminal 11 is split into two and output to the input / output terminals 12 and 13. Therefore, the signal of the input / output terminal 12 and the signal of the input / output terminal 13 have the same phase.
Therefore, considering the case where the power distribution / combination circuit of FIG. 1 is excited in-phase from the input / output terminals 12 and 13, the power distribution / combination circuit of FIG. 1 can be represented by an equivalent circuit of FIG. In FIG. 2, the capacitance of the capacitor 23 becomes (C1 / 2), and the capacitance of the capacitor 24 becomes C2. The characteristics of the distributed constant line 25 are the same as those of the distributed constant lines 14 and 15. Here, the load impedance Z is applied to the input / output terminals 11, 12, and 13.₀Is assumed to be connected.
[0045]
In the power distribution / synthesis circuit of FIG. 1, for example, the isolation between the input / output terminal 12 and the input / output terminal 13 is performed so that a signal input to the input / output terminal 12 as a reflected signal does not appear at the input / output terminal 13. Need to be secured. In this case, if all of the input reflected signals are absorbed by the resistance element 16, isolation between the input / output terminal 12 and the input / output terminal 13 can be ensured.
[0046]
Considering the case where the power distribution / combination circuit of FIG. 1 is excited in the opposite phase from the input / output terminals 12 and 13, the power distribution / combination circuit of FIG. 1 can be represented by an equivalent circuit of FIG. In FIG. 3, the resistance value of the resistor 34 is (R / 2), and the capacitance of the capacitor 35 is C2. Further, the characteristics of the distributed constant line 33 become the same as those of the distributed constant lines 14 and 15. Here, the load impedance Z is applied to the input / output terminals 11, 12, and 13.₀Is assumed to be connected.
[0047]
Therefore, in the power distribution / synthesis circuit of FIG.₀The conditions for matching the input and output of the input / output terminals 11 to 13 and the conditions for uniformly distributing and synthesizing the signal between the input / output terminal 11 and the input / output terminals 12 and 13 are shown in FIG. Can be obtained based on the equivalent circuit of These conditions are expressed by the following equations (1) and (2).
(Equation 1)

Further, in the power distribution / synthesis circuit of FIG. 1, the conditions necessary for ensuring the isolation between the input / output terminal 12 and the input / output terminal 13 can be obtained based on the equivalent circuit of FIG. This condition is expressed by the following equations (3) and (4).
(Equation 2)

That is, the characteristics E1, C1, C2, R, and Z of each component are set so as to satisfy all the conditions of the above-described equations (1) to (4).₁Is determined, the required function of the power distribution / synthesis circuit can be realized.
[0048]
In this case, when a high-frequency signal is input from the input / output terminal 11, the high-frequency signal divided into ず つ is output from the input / output terminal 12 and the input / output terminal 13 in the same phase. When a high-frequency signal is input from the input / output terminal 12, the input / output terminal 13 combines the high-frequency signal passing through the resistance element 16 and the high-frequency signal passing through the distributed constant lines 14 and 15 with equal amplitude and opposite phases. Therefore, no signal appears at the input / output terminal 13.
[0049]
Specific calculations were performed assuming specific conditions. The results are as follows.
Electrical length E1: 60 degrees of the distributed constant lines 14 and 15
Frequency f₀： 10GHz
Load impedance Z₀: 50Ω
Characteristic impedance Z₁: 116Ω
Capacitance C1: 0.34 pF
Capacity C2: 1.19 pF
Resistance value R: 107Ω
The frequency characteristics of the power distribution / synthesis circuit of FIG. 1 configured under the above conditions were obtained by numerical simulation, and as a result, the frequency characteristics shown in FIG. 4 were obtained. The contents of each parameter shown in FIG. 4 are as follows.
[0050]
S21: Forward transfer coefficient
S11: Input reflection coefficient of primary side (input / output terminal 11 side)
S22: Input reflection coefficient on the secondary side (input / output terminal 12 side)
S32: Isolation
Referring to FIG. 4, at a frequency of 9.4 GHz to 10.7 GHz, characteristics of (3.05 ± 0.05) dB as distribution loss, −20 dB or less as input reflection amount, and 20 dB or more as isolation are obtained. You can see that.
[0051]
In the case of the even harmonic mixer of the conventional example shown in FIG. 22, a capacitance of about 10 pF is required as the capacitor 208 under the same conditions, but the total capacitance of the capacitors 17 to 19 is 2.72 pF. The use of the power distribution / synthesis circuit can further reduce the size of the entire circuit.
(Second embodiment)
One embodiment of a power distribution / synthesis circuit according to the present invention will be described with reference to FIGS. This formHaRequest2Corresponding to
[0052]
FIG. 5 is a block diagram showing the configuration of the power distribution / synthesis circuit of this embodiment. FIG. 6 is an equivalent circuit diagram in the case of in-phase excitation of the power distribution / synthesis circuit of FIG. FIG. 7 is an equivalent circuit diagram when the power distribution / synthesis circuit of FIG. FIG. 8 is a graph showing frequency characteristics of the power distribution / synthesis circuit of this embodiment.
[0053]
This embodiment is a modification of the first embodiment. 5 to 8, elements corresponding to those in the first embodiment are denoted by the same reference numerals. For the same parts as those in the first embodiment, the following description is omitted.
In this form,ContractRequest2, A first terminal, a second terminal, a third terminal, a first distributed constant line, a second distributed constant line, and a resistance element are respectively an input / output terminal 11, an input / output terminal 12, an input / output terminal 13, It corresponds to the distributed constant line 14, the distributed constant line 15, and the resistance element 16.
[0054]
MaTRequest2, The second capacitor and the third capacitor correspond to the capacitor 41, the capacitor 42, and the capacitor 43, respectively.
Referring to FIG. 5, the power distribution / synthesis circuit includes input / output terminals 11, 12, 13, distributed constant lines 14, 15, a resistance element 16, and capacitors 41, 42, 43. The characteristics of the two distributed constant lines 14 and 15 are the same, and the characteristics of the two capacitors 42 and 43 are also the same. The capacitor 41 has one end connected to the input / output terminal 11 and the other end grounded.
[0055]
Here, the capacitance of the capacitor 41 is represented by C1, and the capacitances of the capacitors 42 and 43 are represented by C2. The resistance value of the resistance element 16 is represented by R. Further, regarding the characteristics of the distributed constant lines 14 and 15, the specific frequency f₀Is represented by E1, and the characteristic impedance is represented by Z₁Expressed by The load impedance connected to the input / output terminals 11, 12, and 13 is Z₀Expressed by
[0056]
Assuming the functions required for the power distribution / synthesis circuit of FIG. 5, the signal input to the input / output terminal 11 is split into two and output to the input / output terminals 12 and 13. Therefore, the signal of the input / output terminal 12 and the signal of the input / output terminal 13 have the same phase.
Considering the case where the power distribution / synthesis circuit in FIG. 5 is excited in-phase from the input / output terminals 12 and 13, the power distribution / synthesis circuit in FIG. 5 can be represented by an equivalent circuit in FIG. In FIG. 6, the capacitance of the capacitor 44 becomes (C1 / 2), and the capacitance of the capacitor 45 becomes C2. The characteristics of the distributed constant line 46 are the same as those of the distributed constant lines 14 and 15. Here, the load impedance Z is applied to the input / output terminals 11, 12, and 13.₀Is assumed to be connected.
[0057]
Further, in the power distribution / synthesis circuit of FIG. 5, for example, the isolation between the input / output terminal 12 and the input / output terminal 13 is performed so that a signal input to the input / output terminal 12 as a reflected signal does not appear at the input / output terminal 13. Need to be secured. In this case, if all of the input reflected signals are absorbed by the resistance element 16, isolation between the input / output terminal 12 and the input / output terminal 13 can be ensured.
[0058]
Considering the case where the power distribution / combination circuit of FIG. 5 is excited in the opposite phase from the input / output terminals 12 and 13, the power distribution / combination circuit of FIG. 5 can be represented by an equivalent circuit of FIG. In FIG. 7, the resistance value of the resistor 48 is (R / 2), and the capacitance of the capacitor 49 is C2. The characteristics of the distributed constant line 47 are the same as those of the distributed constant lines 14 and 15. Here, the load impedance Z is applied to the input / output terminals 11, 12, and 13.₀Is assumed to be connected.
[0059]
Therefore, the frequency f₀The conditions for matching the inputs and outputs of the input / output terminals 11 to 13 and the conditions for uniformly distributing and combining the signals between the input / output terminal 11 and the input / output terminals 12 and 13 are shown in FIG. Can be obtained based on the equivalent circuit of These conditions are expressed by the following equations (5) and (6).
(Equation 3)

Further, in the power distribution / synthesis circuit of FIG. 5, the conditions necessary for ensuring the isolation between the input / output terminal 12 and the input / output terminal 13 can be obtained based on the equivalent circuit of FIG. This condition is expressed by the following equations (7) and (8).
(Equation 4)

That is, the characteristics E1, C1, C2, R, and Z of each component are set so as to satisfy all the conditions of the above-described equations (5) to (8).₁Is determined, the required function of the power distribution / synthesis circuit can be realized.
[0060]
In this case, when a high-frequency signal is input from the input / output terminal 11, the high-frequency signal divided into ず つ is output from the input / output terminal 12 and the input / output terminal 13 in the same phase. When a high-frequency signal is input from the input / output terminal 12, the high-frequency signal passing through the resistance element 16 and the high-frequency signal passing through the distributed constant lines 14 and 15 are combined at the input / output terminal 13 with equal amplitude and opposite phases. Therefore, no signal appears at the input / output terminal 13.
[0061]
Specific calculations were performed assuming specific conditions. The results are as follows.
Electrical length E1: 45 degrees of distributed constant lines 14 and 15
Frequency f₀： 10GHz
Load impedance Z₀: 50Ω
Characteristic impedance Z₁: 115Ω
Capacity C1: 0.28 pF
Capacity C2: 0.55 pF
Resistance value: 133Ω
The frequency characteristics of the power distribution / synthesis circuit of FIG. 5 configured under the above conditions were obtained by numerical simulation, and as a result, the frequency characteristics shown in FIG. 8 were obtained.
[0062]
Referring to FIG. 8, at a frequency of 9.3 GHz to 10.7 GHz, a distribution loss (3.05 ± 0.05) dB, an input reflection amount of −20 dB or less, and an isolation of 20 dB or more are obtained. You can see that.
In the case of the even harmonic mixer of the conventional example shown in FIG. 22, a capacitance of about 10 pF is required as the capacitor 208 under the same conditions, but the total capacitance of the capacitors 41 to 43 is 1.38 pF. The use of the power distribution / synthesis circuit can further reduce the size of the entire circuit.
[0063]
(Example of power distribution / combination circuit related to the present invention)
Power distribution / synthesis circuit related to the present inventionWill be described with reference to FIGS.You.
Figure 9No electricityFIG. 3 is a block diagram illustrating a configuration of a force distribution synthesis circuit. FIG. 10 is an equivalent circuit diagram when the power distribution / synthesis circuit of FIG. FIG. 11 is an equivalent circuit diagram in a case where the power distribution / synthesis circuit of FIG. FIG. 12 is a graph showing frequency characteristics of the power distribution / synthesis circuit of this embodiment.
[0064]
The power distribution synthesis circuit of FIG.It is a modification of the first embodiment. 9 to 12, elements corresponding to those of the first embodiment are denoted by the same reference numerals.You.
[0065]
FigureReferring to FIG. 9, the power distribution / synthesis circuit includes input / output terminals 11, 12, 13, distributed constant lines 14, 15, a resistance element 16, and capacitors 51, 52, 53. The characteristics of the two distributed constant lines 14 and 15 are the same, and the characteristics of the two capacitors 51 and 52 are also the same. Capacitor 53 is connected in series with resistance element 16.
[0066]
Here, the capacitance of the capacitors 51 and 52 is represented by C1, and the capacitance of the capacitor 53 is represented by C2. The resistance value of the resistance element 16 is represented by R. Further, regarding the characteristics of the distributed constant lines 14 and 15, the specific frequency f₀Is represented by E1, and the characteristic impedance is represented by Z₁Expressed by The load impedance connected to the input / output terminals 11, 12, and 13 is Z₀Expressed by
[0067]
Assuming a function required for the power distribution / synthesis circuit in FIG. 9, the signal input to the input / output terminal 11 is split into two and output to the input / output terminals 12 and 13. Therefore, the signal of the input / output terminal 12 and the signal of the input / output terminal 13 have the same phase.
Considering the case where the power distribution / synthesis circuit of FIG. 9 is excited in-phase from the input / output terminals 12 and 13, the power distribution / synthesis circuit of FIG. 9 can be represented by an equivalent circuit of FIG. In FIG. 10, the capacitance of the capacitor 54 becomes C1. The characteristics of the distributed constant line 55 are the same as those of the distributed constant lines 14 and 15. Here, the load impedance Z is applied to the input / output terminals 11, 12, and 13.₀Is assumed to be connected.
[0068]
Further, in the power distribution / synthesis circuit of FIG. 9, for example, an isolation between the input / output terminal 12 and the input / output terminal 13 so that a signal input to the input / output terminal 12 as a reflected signal does not appear at the input / output terminal 13. Need to be secured. In this case, if all of the input reflected signals are absorbed by the resistance element 16, isolation between the input / output terminal 12 and the input / output terminal 13 can be ensured.
[0069]
Considering the case where the power distribution / synthesis circuit of FIG. 9 is excited in the opposite phase from the input / output terminals 12 and 13, the power distribution / synthesis circuit of FIG. 9 can be represented by an equivalent circuit of FIG. In FIG. 11, the resistance value of the resistor 58 is (R / 2), the capacitance of the capacitor 59 is (2 · C2), and the capacitance of the capacitor 56 is C1. The characteristics of the distributed constant line 57 are the same as those of the distributed constant lines 14 and 15. Here, the load impedance Z is applied to the input / output terminals 11, 12, and 13.₀Is assumed to be connected.
[0070]
Therefore, in the power distribution / synthesis circuit of FIG.₀The conditions for matching the input and output of the input / output terminals 11 to 13 and the conditions for uniformly distributing and synthesizing the signal between the input / output terminal 11 and the input / output terminals 12 and 13 are shown in FIG. Can be obtained based on the equivalent circuit of These conditions are expressed by the following equations (9) and (10).
(Equation 5)

Further, in the power distribution / synthesis circuit of FIG. 9, conditions necessary for ensuring isolation between the input / output terminal 12 and the input / output terminal 13 can be obtained based on the equivalent circuit of FIG. 11. This condition is expressed by the following equations (11) and (12).
(Equation 6)

That is, the characteristics E1, C1, C2, R, Z₁Is determined, the required function of the power distribution / synthesis circuit can be realized.
[0071]
In this case, when a high-frequency signal is input from the input / output terminal 11, the high-frequency signal divided into ず つ is output from the input / output terminal 12 and the input / output terminal 13 in the same phase. When a high-frequency signal is input from the input / output terminal 12, the input / output terminal 13 combines the high-frequency signal passing through the resistance element 16 and the high-frequency signal passing through the distributed constant lines 14 and 15 with equal amplitude and opposite phases. Therefore, no signal appears at the input / output terminal 13.
[0072]
Specific calculations were performed assuming specific conditions. The results are as follows.
Electrical length E1: 60 degrees of the distributed constant lines 14 and 15
Frequency f₀： 10GHz
Load impedance Z₀: 50Ω
Characteristic impedance Z₁: 86.6Ω
Capacitance C1: 0.32 pF
Capacity C2: 0.32 pF
Resistance value R: 50Ω
The frequency characteristics of the power distribution / synthesis circuit of FIG. 9 configured under the above conditions were obtained by numerical simulation, and the frequency characteristics shown in FIG. 12 were obtained.
[0073]
Referring to FIG. 12, at a frequency of 9.4 GHz to 11.0 GHz, a distribution loss of (3.05 ± 0.05) dB, an input reflection amount of −20 dB or less, and an isolation of 20 dB or more are obtained. You can see that.
In the case of the even harmonic mixer of the conventional example shown in FIG. 22, a capacitance of about 10 pF is required as the capacitor 208 under the same conditions, but the total capacitance of the capacitors 41 to 43 is 0.96 pF. The use of the power distribution / synthesis circuit can further reduce the size of the entire circuit.
[0074]
(No.3Embodiment)
One embodiment of the power distribution / synthesis circuit of the present invention will be described with reference to FIGS. This form is claimed3Corresponding to
FIG. 13 is a block diagram showing the configuration of the power distribution / synthesis circuit of this embodiment. FIG. 14 is an equivalent circuit diagram in the case of in-phase excitation of the power distribution / synthesis circuit of FIG. FIG. 15 is an equivalent circuit diagram in a case where the power distribution / synthesis circuit of FIG. FIG. 16 is a graph showing frequency characteristics of the power distribution / synthesis circuit of this embodiment.
[0075]
This embodiment is a modification of the first embodiment. 13 to 16, elements corresponding to those in the first embodiment are denoted by the same reference numerals. For the same parts as those in the first embodiment, the following description is omitted.
In this form, the claim3, A second terminal, a third terminal, a first inductor, a first capacitor, a second capacitor, a resistive element, a second inductor, and a third capacitor are respectively connected to the input / output terminal 11. , 12, 13, the inductor 64, the capacitor 61, the capacitor 62, the resistance element 16, the inductor 65, and the capacitor 63.
[0076]
Referring to FIG. 13, this power distribution / synthesis circuit includes input / output terminals 11, 12, 13, capacitors 61, 62, 63, inductors 64, 65, and a resistance element 16. The characteristics of the two capacitors 61 and 62 are the same. The resistance element 16, the inductor 65, and the capacitor 63 are connected in series.
Here, the capacitance of the capacitors 61 and 62 is represented by C1, and the capacitance of the capacitor 63 is represented by C2. The resistance value of the resistance element 16 is represented by R. Further, the inductance of the inductor 64 is represented by L1, and the inductance of the inductor 65 is represented by L2. The load impedance connected to the input / output terminals 11, 12, and 13 is Z₀Expressed by
[0077]
Assuming a function required for the power distribution / synthesis circuit in FIG. 13, the signal input to the input / output terminal 11 is split into two and output to the input / output terminals 12 and 13. Therefore, the signal of the input / output terminal 12 and the signal of the input / output terminal 13 have the same phase.
Considering the case where the power distribution / synthesis circuit in FIG. 13 is excited in-phase from the input / output terminals 12 and 13, the power distribution / synthesis circuit in FIG. 13 can be represented by an equivalent circuit in FIG. In FIG. 14, the capacitance of the capacitor 67 is C1. The inductance of the inductor 66 is (2 · L1). Here, the load impedance Z is applied to the input / output terminals 11, 12, and 13.₀Is assumed to be connected.
[0078]
Further, in the power distribution / synthesis circuit shown in FIG. Need to be secured. In this case, if all of the input reflected signals are absorbed by the resistance element 16, isolation between the input / output terminal 12 and the input / output terminal 13 can be ensured.
[0079]
Considering the case where the power distribution / combination circuit of FIG. 13 is excited in the opposite phase from the input / output terminals 12 and 13, the power distribution / combination circuit of FIG. 13 can be represented by an equivalent circuit of FIG. In FIG. 15, the resistance value of the resistor 72 is (R / 2), the capacitance of the capacitor 74 is (2 · C2), the capacitance of the capacitor 71 is C1, and the inductance of the inductor 73 is (L2 / 2). become. Here, the load impedance Z is applied to the input / output terminals 11, 12, and 13.₀Is assumed to be connected.
[0080]
Therefore, in the power distribution / synthesis circuit of FIG.₀The conditions for matching the input and output of the input / output terminals 11 to 13 and the conditions for uniformly distributing and synthesizing the signal between the input / output terminal 11 and the input / output terminals 12 and 13 are shown in FIG. Can be obtained based on the equivalent circuit of These conditions are expressed by the following equations (13) and (14).
(Equation 7)

In addition, the conditions required for ensuring the isolation between the input / output terminal 12 and the input / output terminal 13 in the power distribution / synthesis circuit of FIG. 13 can be obtained based on the equivalent circuit of FIG. This condition is expressed by the following equations (15) and (16).
(Equation 8)

That is, if the characteristics L1, L2, C1, C2, and R of the respective components are determined so as to satisfy all the conditions of the above Expressions (13) to (16), the required power distribution and synthesis circuit Function can be realized.
[0081]
In this case, when a high-frequency signal is input from the input / output terminal 11, the high-frequency signal divided into ず つ is output from the input / output terminal 12 and the input / output terminal 13 in the same phase. When a high-frequency signal is input from the input / output terminal 12, the high-frequency signal passing through the resistance element 16 and the high-frequency signal passing through the capacitors 61 and 62 are combined with equal amplitude and opposite phases at the input / output terminal 13. No signal appears at the input / output terminal 13.
[0082]
Specific calculations were performed assuming specific conditions. The results are as follows.
Frequency f₀: 1GHz
Load impedance Z₀: 50Ω
Capacitance C1: 3.18 pF
Capacity C2: 3.18 pF
Resistance value R: 50Ω
Inductance L1: 7.96 nH
Inductance L2: 15.9 nH (= Z₀/ Πf₀)
The frequency characteristics of the power distribution / synthesis circuit of FIG. 13 configured under the above conditions were obtained by numerical simulation, and the frequency characteristics shown in FIG. 16 were obtained.
[0083]
Referring to FIG. 16, at a frequency of 0.91 GHz to 1.10 GHz, characteristics of (3.05 ± 0.05) dB as distribution loss, -20 dB or less as input reflection amount, and 20 dB or more as isolation are obtained. You can see that.
(No.4Embodiment)
One embodiment of a power distribution / synthesis circuit according to the present invention will be described with reference to FIGS. This form is claimed4Corresponding to
[0084]
FIG. 17 is a block diagram showing the configuration of the power distribution / synthesis circuit of this embodiment. FIG. 18 is an equivalent circuit diagram when the power distribution / synthesis circuit of FIG. 17 is excited in-phase from the input / output terminals 12 and 13. FIG. 19 is an equivalent circuit diagram in the case where the power distribution / synthesis circuit of FIG. FIG. 20 is a graph showing frequency characteristics of the power distribution / synthesis circuit of this embodiment.
[0085]
This embodiment is a modification of the first embodiment. 17 to 20, elements corresponding to those in the first embodiment are denoted by the same reference numerals. For the same parts as those in the first embodiment, the following description is omitted.
In this form, the claim4The first terminal, the second terminal, the third terminal, the first capacitor, the second capacitor, the third capacitor, the first inductor, the second inductor, and the resistance element of the , 12, 13, capacitors 81, 84, 85, inductors 82, 83 and resistance element 16.
[0086]
Referring to FIG. 17, this power distribution / synthesis circuit includes input / output terminals 11, 12, and 13, capacitors 81, 84, and 85, inductors 82 and 83, and a resistance element 16. The characteristics of the two capacitors 84 and 85 are the same. The characteristics of the two inductors 82 and 83 are also the same.
Here, the capacitance of the capacitor 81 is represented by C1, and the capacitances of the capacitors 84 and 85 are represented by C2. The resistance value of the resistance element 16 is represented by R. Further, the inductance of the inductors 82 and 83 is represented by L. The load impedance connected to the input / output terminals 11, 12, and 13 is Z₀Expressed by
[0087]
Assuming a function required for the power distribution / synthesis circuit of FIG. 17, the signal input to the input / output terminal 11 is split into two and output to the input / output terminals 12 and 13. Therefore, the signal of the input / output terminal 12 and the signal of the input / output terminal 13 have the same phase.
Considering the case where the power distribution / synthesis circuit of FIG. 17 is excited in-phase from the input / output terminals 12 and 13, the power distribution / synthesis circuit of FIG. 17 can be represented by an equivalent circuit of FIG. In FIG. 18, the capacitance of the capacitor 86 becomes (C1 / 2), and the capacitance of the capacitor 88 becomes C2. The inductance of the inductor 87 becomes (L). Here, the load impedance Z is applied to the input / output terminals 11, 12, and 13.₀Is assumed to be connected.
[0088]
In the power distribution / synthesis circuit of FIG. 17, for example, the isolation between the input / output terminal 12 and the input / output terminal 13 is performed so that a signal input to the input / output terminal 12 as a reflected signal does not appear at the input / output terminal 13. Need to be secured. In this case, if all of the input reflected signals are absorbed by the resistance element 16, isolation between the input / output terminal 12 and the input / output terminal 13 can be ensured.
[0089]
Considering the case where the power distribution / combination circuit of FIG. 17 is excited in the opposite phase from the input / output terminals 12 and 13, the power distribution / combination circuit of FIG. 17 can be represented by an equivalent circuit of FIG. In FIG. 19, the resistance value of the resistor 92 is (R / 2), the capacitance of the capacitor 93 is C2, and the inductance of the inductor 91 is L. Here, the load impedance Z is applied to the input / output terminals 11, 12, and 13.₀Is assumed to be connected.
[0090]
Therefore, in the power distribution / synthesis circuit of FIG.₀The conditions for matching the input and output of the input / output terminals 11 to 13 and the conditions for uniformly distributing and synthesizing the signal between the input / output terminal 11 and the input / output terminals 12 and 13 are shown in FIG. Can be obtained based on the equivalent circuit of These conditions are expressed by the following equations (17) and (18).
(Equation 9)

Further, in the power distribution / synthesis circuit of FIG. 17, the conditions necessary for ensuring the isolation between the input / output terminal 12 and the input / output terminal 13 can be obtained based on the equivalent circuit of FIG. This condition is expressed by the following equations (19) and (20).
(Equation 10)

Therefore, if the characteristics of each component are determined as in the following equation (21) based on the above equations (17) to (20), the required function of the power distribution / synthesis circuit is realized. can do.
(Equation 11)

In this case, when a high-frequency signal is input from the input / output terminal 11, the high-frequency signal divided into ず つ is output from the input / output terminal 12 and the input / output terminal 13 in the same phase. When a high-frequency signal is input from the input / output terminal 12, the high-frequency signal passing through the resistance element 16 and the high-frequency signal passing through the inductors 82 and 83 are combined with equal amplitude and opposite phases at the input / output terminal 13. No signal appears at the input / output terminal 13.
[0091]
Specific calculations were performed assuming specific conditions. The results are as follows.
Frequency f₀: 1GHz
Load impedance Z₀: 50Ω
Capacitance C1: 3.18 pF
Capacity C2: 3.18 pF
Resistance value R: 200Ω
Inductance L: 15.9 nH
The frequency characteristics of the power distribution / synthesis circuit of FIG. 17 configured under the above conditions were obtained by numerical simulation, and the frequency characteristics shown in FIG. 20 were obtained.
[0092]
Referring to FIG. 20, at a frequency of 0.94 GHz to 1.06 GHz, a distribution loss (3.05 ± 0.05) dB, an input reflection amount of −20 dB or less, and an isolation of 20 dB or more are obtained. You can see that.
It should be noted that the power distribution / combination circuit of the present invention can be configured even with a configuration other than the above-described five embodiments. For example, the connection positions of capacitors and inductors connected to the circuit can be changed, and the number of components connected to the circuit can be further increased.
[0093]
【The invention's effect】
According to the present invention, for example, as is clear from the characteristics of FIGS. 4, 8, 12, 16, and 20, the baseband signal can be blocked in the power distribution / synthesis circuit, so that the baseband signal is blocked. Need not be provided in the mixer circuit, and the entire circuit can be reduced in size. Therefore, the present invention is particularly effective for application to a monolithic microwave integrated circuit that requires a reduction in chip area.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a power distribution and synthesis circuit according to a first embodiment.
FIG. 2 is an equivalent circuit diagram when the power distribution / synthesis circuit of FIG. 1 is excited in-phase from input / output terminals 12 and 13;
FIG. 3 is an equivalent circuit diagram in a case where the power distribution / synthesis circuit of FIG.
FIG. 4 is a graph illustrating frequency characteristics of the power distribution / synthesis circuit according to the first embodiment;
FIG. 5 is a block diagram illustrating a configuration of a power distribution / synthesis circuit according to a second embodiment;
6 is an equivalent circuit diagram when the power distribution / synthesis circuit of FIG. 5 is excited in-phase from input / output terminals 12 and 13. FIG.
7 is an equivalent circuit diagram in a case where the power distribution / synthesis circuit of FIG. 5 is excited in reverse phase from input / output terminals 12 and 13. FIG.
FIG. 8 is a graph illustrating frequency characteristics of the power distribution / synthesis circuit according to the second embodiment.
FIG. 9Related to the present inventionFIG. 3 is a block diagram illustrating a configuration of a power distribution / synthesis circuit.
FIG. 10 is an equivalent circuit diagram in the case of in-phase excitation of the power distribution / synthesis circuit of FIG. 9 from input / output terminals 12 and 13.
11 is an equivalent circuit diagram in a case where the power distribution / synthesis circuit of FIG. 9 is excited in reverse phase from input / output terminals 12 and 13. FIG.
FIG.Related to the present invention5 is a graph illustrating frequency characteristics of the power distribution / synthesis circuit.
FIG. 133FIG. 3 is a block diagram illustrating a configuration of a power distribution / combination circuit according to the embodiment.
FIG. 14 is an equivalent circuit diagram in the case of in-phase excitation of the power distribution / synthesis circuit of FIG. 13 from input / output terminals 12 and 13.
FIG. 15 is an equivalent circuit diagram in the case where the power distribution / synthesis circuit of FIG. 13 is excited in reverse phase from input / output terminals 12 and 13.
FIG. 1639 is a graph illustrating frequency characteristics of the power distribution / synthesis circuit according to the embodiment.
FIG. 174FIG. 3 is a block diagram illustrating a configuration of a power distribution / combination circuit according to the embodiment.
18 is an equivalent circuit diagram when the power distribution / synthesis circuit in FIG. 17 is excited in-phase from input / output terminals 12 and 13.
19 is an equivalent circuit diagram in the case where the power distribution / synthesis circuit of FIG. 17 is excited in the opposite phase from the input / output terminals 12 and 13. FIG.
FIG. 2049 is a graph illustrating frequency characteristics of the power distribution / synthesis circuit according to the embodiment.
FIG. 21 is a block diagram showing a configuration of a homodyne type receiver using an even harmonic mixer.
FIG. 22 is a block diagram showing a configuration of a conventional even harmonic mixer.
FIG. 23 is a block diagram showing a configuration of a conventional power distribution / synthesis circuit.
[Explanation of symbols]
11, 12, 13 input / output terminals
14,15 Distributed parameter line
16 Resistance element
17,18,19 Capacitor
21, 22, 32 terminals
23, 24, 35 capacitors
25,33 Distributed parameter line
34 Resistance
41, 42, 43, 44, 45, 49 Capacitor
46 Distributed parameter line
48 Resistance
51, 52, 53, 54, 56, 59 Capacitor
55,57 Distributed constant line
58 Resistance
61, 62, 63, 67, 71, 74 Capacitor
64, 65, 66, 73 inductor
72 Resistance
81, 84, 85, 86, 88, 93 capacitors
82, 83, 87, 91 inductor
92 Resistance
200a, 200b mixer diode
201 Anti-parallel diode pair
202 RF terminal
203 LO terminal
204 Baseband terminal
205 Open end stub
206 Short-end stub
207 High frequency signal blocking inductor
208 Capacitor for blocking baseband signal
211 Antenna
212 Low noise amplifier circuit
213 Bandpass filter
214 0 degree power distribution and synthesis circuit
215a, 215b Even harmonic mixer
216 45-degree power distribution / combination circuit
217 Even harmonic quadrature mixer
218 Local oscillation circuit
219a, 219b Low-pass filter
220a, 220b Baseband amplifier circuit
221 Demodulation circuit
231,232,233 I / O terminal
234 resistance element
235,236 Distributed parameter line

Claims (4)

A first terminal, a second terminal, and a third terminal respectively connected to a load impedance Z _0, and a signal input to the first terminal is divided into two systems to distribute the signal to the second terminal and the third terminal; A power distributing / combining circuit that outputs the signal to a third terminal, or combines the signals input to the second terminal and the third terminal and outputs the combined signal to the first terminal,
A first capacitor (capacitance C1) having one end connected to the first terminal;
The first distributed constant line having one end connected to the first capacitor of the other end in electrical (electrodeposition that put in a specific frequency f ₀ patiently E1, the characteristic impedance Z ₁₎ and,
The second distributed constant line having one end connected to the first capacitor of the other end in electrical (electrodeposition that put in a specific frequency f ₀ patiently E1, the characteristic impedance Z ₁₎ and,
A resistance element (resistance value R) for electrically connecting the other end of the first distributed constant line and the other end of the second distributed constant line,
A second capacitor (capacitance C2) connecting the other end of the first distributed constant line and the second terminal;
A third capacitor (capacitance C2) for connecting the other end of the second distributed constant line and the third terminal;
A condition for matching input and output of each of the first terminal, the second terminal, and the third terminal at the specific frequency f ₀ ;
The conditions for uniformly distributing and synthesizing signals between the first terminal and the second terminal and between the first terminal and the third terminal are expressed by the following equations (1) and (2).

Represented by
Further, the conditions for ensuring the isolation between the second terminal and the third terminal are expressed by the following equations (3) and (4).

Represented by
Power divider combining circuit, wherein the formula (1) has the formula (4) from the established between the capacitance C1, C2 and the electrical length E1 and the resistance R and the characteristic impedance Z _1. A first terminal, a second terminal, and a third terminal, wherein the signal input to the first terminal is distributed to two systems and output to the second terminal and the third terminal; or A power distribution / combination circuit that combines signals input to a second terminal and a third terminal and outputs the combined signal to the first terminal,
A first capacitor having one end connected to the first terminal and the other end grounded;
A first distributed constant line having one end electrically connected to the first terminal;
A second distributed constant line having one end electrically connected to the first terminal;
A resistance element for electrically connecting the other end of the first distributed constant line and the other end of the second distributed constant line;
A second capacitor connecting the other end of the first distributed constant line and the second terminal;
A power distribution / combination circuit comprising: a third capacitor that connects the other end of the second distributed constant line and the third terminal. A first terminal, a second terminal, and a third terminal, wherein the signal input to the first terminal is distributed to two systems and output to the second terminal and the third terminal; or A power distribution / combination circuit that combines signals input to a second terminal and a third terminal and outputs the combined signal to the first terminal,
A first inductor having one end connected to the first terminal and the other end grounded;
A first capacitor having one end connected to the first terminal and the other end connected to the second terminal;
A second capacitor having one end connected to the first terminal and the other end connected to the third terminal;
A resistor circuit comprising a series circuit of a resistance element, a second inductor, and a third capacitor, one end of which is connected to the second terminal, and the other end of which is connected to the third terminal. Characteristic power distribution synthesis circuit. A first terminal, a second terminal, and a third terminal, wherein the signal input to the first terminal is distributed to two systems and output to the second terminal and the third terminal; or A power distribution / combination circuit that combines signals input to a second terminal and a third terminal and outputs the combined signal to the first terminal,
A first capacitor having one end connected to the first terminal and the other end grounded;
A second capacitor having one end connected to the second terminal;
A third capacitor having one end connected to the third terminal;
A first inductor having one end connected to the first terminal and the other end connected to the other end of the second capacitor;
A second inductor having one end connected to the first terminal and the other end connected to the other end of the third capacitor;
A power distribution / synthesis circuit, comprising: a resistor connected between the other end of the first inductor and the other end of the second inductor.

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