JP3577289B2 - Optical signal processing method and optical signal processing device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an optical signal processing method and apparatus for performing serial-parallel conversion by inputting an optical pulse train such as an optical packet or the like, or parallel-serial conversion for converting a parallel electric signal into one optical signal.
[0002]
Furthermore, the present invention relates to a label processing method and apparatus for recognizing high-speed optical packet address information and the like.
[0003]
Furthermore, the present invention relates to an optical memory method and apparatus for freely writing and reading a high-speed optical packet signal to and from a memory by an electronic circuit and outputting the optical packet signal again as an optical packet signal.
[0004]
Furthermore, the present invention relates to realizing higher-order functions of a router, an optical computer, and the like by combining technologies such as the above-described serial-parallel conversion, optical clock pulse generation, label processing, and optical memory.
[0005]
[Prior art]
2. Description of the Related Art In recent years, with the explosion of data communication represented by the Internet, a demand for faster optical signals has been increasing. However, after converting an optical signal into an electric signal by a light receiving element, there is a problem that an electric signal of 10 Gbps or more is directly processed by a conventional electronic circuit. For example, in optical packet communication, a router or the like decodes address information contained in a label of an optical packet to determine a label output port and a packet signal for avoiding collision between optical packets. Although a buffer memory function that delays by an arbitrary time is required, conventionally, since the functions of the label recognition processing and the memory processing are configured by a silicon-based LSI, the operation speed is 1 Gbps or less. .
Therefore, it is becoming difficult to realize the label recognition processing and the memory processing for a high-speed optical packet signal using a conventional silicon-based electronic circuit.
[0006]
In recent years, as shown in FIG. 19, a high-speed optical packet signal is converted into an electric signal by an O / E (optical / electrical) receiving circuit 1 using a light receiving element, and the electric signal is converted into a high-speed InP or GaAs-based electronic device. A clock signal is extracted by an electric clock signal generator 2 using circuit technology, and a high-speed electric signal is parallel-converted into a plurality of low-speed electric signals in an electric serial-parallel converter 3 by the clock signal. On the other hand, in the memory processing, the parallel-converted electric signals are stored in the memory cell array 4 of the SRAM. 4 A plurality of low-speed output electric signals read out from the electronic device are reconstructed into a high-speed serial electric signal by an electric parallel-serial converter 5 using electronic circuit technology. (/ Light) A method of converting the signal into an optical packet signal by the transmission circuit 6 is considered.
[0007]
However, in such a method, the clock generation, the serial-parallel conversion, and the inverse conversion are all dependent on the electronic circuits 2, 3, and 5, so that the speed of about 40 Gbps is considered to be the limit. Further, when serial-parallel conversion is performed by InP or GaAs-based high-speed electronic circuit technology to convert a plurality of low-speed signals, a high-speed electric signal is sequentially frequency-divided by half (40 GHz → 20 GHz →... →). (Several 100 MHz), which requires a considerable number of stages, and also causes problems such as clock extraction and phase control in each stage. Also, when these electronic circuits are used, the overall power consumption is expected to be considerably large. Moreover, in the conventional clock extraction using an electronic circuit, it is necessary to apply feedback by a PLL (Phase Locked Loop) to lock the oscillation frequency of a VCO (Voltage-Controlled Oscilltor: voltage-controlled oscillator). It is impossible to instantaneously extract a clock from a packet signal input in a burst.
On the other hand, independently of the above system, some researches on parallel conversion of high-speed serial optical signals (also referred to as spatial conversion time) have been performed. As a conventional optical serial-parallel conversion method, a method of branching a high-speed optical signal into a plurality of signals and converting each optical signal into a low-speed optical signal by using a high-speed optical-optical switch can be considered. For example, when performing a parallel conversion of a high-speed optical signal of 100 Gbps into ten low-speed optical signals of 10 Gbps, ten optical-optical switches are used.
[0008]
As another optical serial-parallel conversion method, a method using generation of a plurality of surface-emitted second-order harmonics (Shih-Chen Wang et al., J. Lihgtwave Technology 1. Vo 1.14, No. 12, P. 2736 (l996) )), A method using an exciton-like giant nonlinear effect (K. Ema et al., App 1. Rhys. Lett. Vol. 59, No. 25, p. 2799 (1991)), a method using a hologram (P. C. Suneta 1., 0 pt. Lett. Vo 1.20, No. 16, p. 1728 (1995)).
[0009]
[Problems to be solved by the invention]
However, the conventional method using a plurality of light-to-light switches for the light serial-to-light parallel conversion has a problem that the device becomes considerably large and the power consumption becomes large. Further, the conventional method using surface-emitting second-harmonic generation requires a non-resonant light Since the nonlinear effect is used, there is a problem that the efficiency is extremely low and the loss is very large. Further, the conventional method using the exciton-like giant nonlinear effect has a problem that it is necessary to cool the nonlinear medium to a liquid helium temperature in order to obtain a large nonlinear effect. Further, the conventional method using a hologram has a problem that the loss is extremely large because the diffraction effect is used. Therefore, such conventional methods all have extremely high running costs, are inefficient, and have a problem that it is very difficult to maintain stable performance over a long period of time.
[0010]
Therefore, a first object of the present invention is to solve the above-mentioned problems of the prior art by converting an input high-speed optical packet signal into a low-speed parallel optical signal by itself, thereby making it possible to use various silicon-based parallel optical signals. An object of the present invention is to enable optical signal processing by an electronic circuit to be realized with low power consumption and a relatively simple configuration.
[0011]
A second object of the present invention is to generate a single optical pulse from an input optical packet and to collectively label the label portion of the optical packet using the optical pulse in order to solve the above-mentioned problem of the prior art. The purpose of the present invention is to make it possible to instantaneously read the label information of a high-speed optical packet input in a burst by performing parallel conversion and leading the signal to the label recognition circuit as the silicon-based electronic circuit.
[0012]
Further, a third object of the present invention is to realize an optical memory method and apparatus capable of responding to a burst signal with high speed and low power consumption in order to solve the above-mentioned problems of the prior art.
[0013]
Further, a fourth object of the present invention is to realize high-order functions such as high-performance routers and optical computers by combining the above-mentioned technologies such as serial-parallel conversion, optical clock pulse generation, label processing, and optical memory. It is in.
[0014]
[Means for Solving the Problems]
The optical signal processing method of the present invention burst The optical packet converts itself into a low-speed parallel signal, thereby enabling signal processing in a silicon-based electronic circuit having a low operation speed but high functionality. In the above-described conventional electronic circuit, a clock is extracted and the frequency division of the optical packet signal is repeated (10 GHz → 5 GHz, 2 lines → 2.5 GHz, 4 lines →...) To convert the signal into a low-speed parallel electric signal. Therefore, clock division and timing adjustment are required as needed. On the other hand, in the first method of the present invention, a single optical pulse is generated based on the first bit of the optical packet signal, whereby a part or the whole of the optical packet is parallelized in a collective light state. The conversion is performed, and high-speed optical signal processing can be realized with an extremely simple configuration.
[0015]
In the first optical signal processing method of the present invention, as described above, burst It is necessary to always generate a single optical pulse from an optical packet signal at a constant timing. Therefore, in the present method, the optical packet is irradiated on the photoconductive switch, and the charges generated there are sent to the capacitor and accumulated. When the charge generated in the first bit of the optical packet fully charges the capacitor, the potential of the capacitor is fixed and the potential of the capacitor changes regardless of the pattern of the subsequent light pulse applied to the photoconductive switch. do not do. The potential of the capacitor, which has risen sharply by the first bit, is converted into an electric pulse by differentiating it with a CR differentiating circuit, and the electric pulse is used to drive a semiconductor laser to generate an optical pulse. The advantage of the method of the present invention is that the optical pulse is always generated from the first bit for the arrival of the optical packet, so that the timing from the input of the optical packet to the generation of a single optical pulse is always constant, It is possible to instantaneously generate a single pulse even for an optical packet that enters in a burst, which is difficult to apply in an electronic circuit. Further, it operates without depending on the polarization state of an incident optical packet, and the polarization state of an output optical pulse can always be kept constant (this characteristic is obtained by an optical-optical serial-parallel converter described later). Indispensable). Furthermore, after the head bit has fully charged the capacitor, the intensity does not depend, so that even if the intensity of the input optical packet fluctuates, the intensity of the output optical pulse can be kept constant. Further, in the case of extracting a clock of 40 GHz by a conventional method using an electronic circuit, the electronic circuit naturally needs to have such a high speed. However, in the method of the present invention, the gain-switch method (several 100 ps) of the semiconductor laser is used. Since an optical pulse of 20 ps or less is generated from an electric pulse), the bandwidth of the electronic circuit portion of the present invention is about several GHz.
[0018]
According to a second optical signal processing method of the present invention, the single optical pulse is converted into an optical pulse train by a loop-shaped optical waveguide, and the optical-optical serial-parallel converter sequentially converts the optical packets into k bits at a time. That converts the entire optical packet into a low-speed k optical signal train by repeating the parallel conversion in the above, converts it into k electric signal trains with a low-speed photoelectric converter, and performs processing with a silicon-based electronic circuit. It is. This method is effective when the optical packet length is long and it is desired to process the whole.For example, by using a silicon-based electronic memory as the electronic circuit, it is possible to freely write an extremely high-speed optical packet signal to the electronic memory. It becomes. Further, the k parallel electric signals read from the electronic memory are reconstructed into high-speed optical packet signals again by an electric-optical type parallel-serial converter (details will be described later) and output.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0020]
As described above, it has become difficult to directly process a high-speed optical signal by a conventional silicon electronic circuit with an increase in the speed of the optical signal. FIG. 1A and FIG. 1B are diagrams showing a configuration example of an optical signal processing device of the present invention. The high-speed optical packet signal is split into two, and one is guided to the optical pulse generator 102 to generate an optical pulse, and the optical-optical serial-parallel converter 104 spatially separates the other optical packet signal. To parallel. Thereafter, using the low-speed light-receiving element array 106 as a photoelectric converter, these short-pulse optical signals are converted into low-speed electric signals, and processed by an electronic circuit 108 composed of a silicon LSI. This enables high-speed signal processing of an optical packet signal (operating speed of electronic circuit × number of parallel circuits).
[0021]
FIG. 1A shows a case where the optical pulse generator 102 generates one optical pulse each time one optical packet arrives, thereby performing parallel conversion of all bits of the optical packet at once. Is effective when the number of bits is small (<100). For example, in optical data communication represented by the Internet, the bit length of an optical packet itself is long, but a label (or header) portion having address information and the like is about several tens of bits. By performing parallel conversion and performing processing in a label recognition circuit (label recognition circuit 34 in FIG. 13 described later) in the silicon LSI 108, it is possible to extract an address of an optical packet at an extremely high speed.
[0022]
Further, in an optical computer or the like, signal processing for 32-bit or 64-bit high-speed optical data is required. In this case, for example, by using a D / A converter as the electronic circuit 108, a high-speed digital-analog converter can be configured. 1A is placed in parallel, and the parallel signal is input to one logical operation circuit (not shown), whereby an extremely high-speed logical operation unit between two high-speed optical data signals is obtained. Can be configured.
[0023]
On the other hand, when processing the entire optical packet having a long packet length, the number of parallels becomes extremely large in the method of FIG. 1A, and it is difficult to configure the optical-optical serial-parallel converter 104. . In this case, as shown in FIG. 1B, the optical pulse generator 102 generates an optical pulse train having a low repetition rate (having a period k times the bit interval of the input optical packet). The optical-to-optical serial-to-parallel converter 104 repeatedly converts the optical packet signal into k bits at a time, converts the signal into a low-speed electric signal by the low-speed light receiving element 106, and causes the electronic circuit 108 to execute the processing. For example, this is a case where it is desired to store the entire high-speed optical packet signal in a silicon-based electronic memory (Si-based RAM array 400 in FIG. 14 described later).
[0024]
Hereinafter, the optical pulse generator 102, the optical-optical serial-parallel converter 104, and the high-speed optical label processing circuit according to the embodiment of FIG. An optical memory according to an embodiment will be described in detail. In the case of an optical memory, when reading recorded optical packets, it is necessary to reconstruct parallel optical signals into original optical packets, which will be described later.
[0025]
[Optical-optical serial-parallel converter]
FIG. 2 is a diagram showing a configuration of an optical-optical serial-parallel converter 200 according to an embodiment of the present invention. In FIG. 2, reference numeral 201 denotes an optical demultiplexer that demultiplexes an input optical serial signal into k signals, 202 denotes an optical delay device that sequentially delays each demultiplexed parallel optical signal by one bit, and 203 denotes a condenser lens. Reference numeral 204 denotes a transmission-type surface switch (light-light switch), and reference numeral 205 denotes a condenser lens.
[0026]
The input optical packet is divided into k packets by the demultiplexer 201, and each packet is delayed so as to be shifted by one bit. At this time, focusing on a certain time timing of the k parallel optical signals, the optical pulse of k consecutive bits of the original optical packet is included one by one. Although the k parallel optical signals are represented two-dimensionally in FIG. 2, there is no problem if they are two-dimensionally arranged in a direction perpendicular to the paper surface. Assuming that the array is arranged in a matrix of 5 × 5 in the direction perpendicular to the paper, only the central one is a control light pulse, and the remaining 24 around it are split by a splitter 201. This is a parallel optical signal. These twenty-four parallel optical signals and one control light pulse are condensed by the front condenser lens 203 at one point on the surface type optical switch 204.
[0027]
When a control light pulse is applied to the surface type optical switch 204, the surface-type optical switch 204 transmits light when the absorption coefficient decreases in the active layer and the transmittance increases because the refractive index in the active layer changes. An etalon type or the like whose rate changes is used. In any case, when the control light pulse (optical clock) is “0”, the transmittance of the surface-type optical switch 204 is extremely low, and these parallel optical signals cannot pass, but the control light pulse is “1”. In this case, the transmittance increases so that those parallel optical signals can pass.
[0028]
Since the 24 parallel optical signals spatially arranged are delayed by one bit for each port, the original optical signal continues at the timing when the control optical pulse reaches the optical switch 204. The 24-bit data arrives at the optical switch 204 in parallel at the same time. Therefore, when the transmittance of the optical switch 204 increases due to the control light pulse, the 24-bit data of all ports simultaneously passes through the optical switch 204 and is spatially developed again by the rear lens 205 in a spatially parallel manner. This means that the information of the high-speed optical signal (optical packet) is parallel-converted into 24 low-speed parallel optical signals synchronized with the control optical pulse. The period of the control light pulse at this time is 24 times the bit period of the original optical packet.
[0029]
FIG. 3 is a diagram showing an embodiment of an optical serial-to-parallel converter using a reflection type surface optical switch 211 as the surface optical switch. A 100% mirror is vapor-deposited on one surface (the left side surface in FIG. 3) of the surface type optical switch 204 shown in FIG. 2 to be a reflection type, thereby enhancing the change in the absorption coefficient or the refractive index in the active layer. Thus, it is possible to realize the reflection type surface optical switch 211 having a large extinction ratio. Here, one control light A and a plurality of signal lights B are incident from many optical fibers 207 attached to individual microlens arrays 206. Reference numeral 208 denotes a polarizing beam splitter (PBS) having the microlens array 206 attached to the light incident surface, and reference numeral 209 denotes a λ / 4 wavelength plate arranged on the PBS 208 on the side of the condenser lens 210.
[0030]
By setting the control light A and each signal light B to linearly polarized light passing through the PBS 208, the signal light B is reflected on the reflective surface type optical switch 211 and then reciprocates through the λ / 4 wavelength plate 209. , The signal light B is reflected by the PBS 208 and extracted as a parallel optical pulse train.
[0031]
However, in the case of this method, even when the control light A is “0”, a part of the signal light that is not completely absorbed by the surface light switch 211 may be reflected by the surface light switch 211 and output. In order to increase the On / Off ratio of the signal light B (the ratio of the intensity of the output signal light when the control light is “1” and the intensity of the output signal light when the control light is “0”), the absorption of the surface-type optical switch 211 is required. It is necessary to increase the change in the coefficient, and for that purpose, it is necessary to increase the intensity of the control light A. Therefore, in order to increase the On / Off ratio of the signal light B without increasing the control light A too much, it is essential to suppress the output of the signal light B when the control light A is "0" as much as possible. .
[0032]
Therefore, here, as shown in FIG. 4, the parallel optical signal and the control light obtained by demultiplexing the optical signal are preset to linearly polarized light passing through the PBS 208, and only the central control light is λ / The size and position of the λ / 4 wavelength plate 209 are set so as to pass through the four wavelength plate 209. For this reason, only the control light is converted into circularly polarized light by the λ / 4 wavelength plate 209, and the other parallel optical signals are irradiated to one point of the reflection type surface optical switch 211 by the lens 210 in a state of being linearly polarized. You. The operation principle at this time will be described below using an absorption-saturated surface optical switch as an example.
[0033]
Electrons and holes exist in which two states of up spin and down spin degenerate with respect to one energy state. Now, considering the exciton transition between an electron and a heavy hole, when a control light of a circularly polarized light is incident on one point of a multiple quantum wells layer (MQW layer) of the optical switch 211, one of the spins is rotated. Only if a parallel optical signal of linear polarization is incident, both spins will be excited. As a result, when only one of the spins is excited by the circularly polarized control light “1”, only the parallel optical signal in the polarization state interacting with the spin feels a change in absorption and refractive index. That is, in this case, when the parallel optical signal of linear polarization is irradiated, only the same circularly polarized light component as the control light is modulated by the control light, and the parallel optical signal reflected by the surface type optical switch 211 becomes an elliptically polarized light signal. Therefore, the light is reflected by the PBS 208. On the other hand, when the control light is “0”, the parallel optical signal cannot change its polarization state, and therefore returns to the original port without being reflected by the PBS 208, and the output light is almost “0”. ".
[0034]
The switching speed of the planar optical switch 211 according to this method is determined by the shorter of the spin relaxation time and the carrier lifetime. In the case of a multiple quantum well layer grown at 500 degrees Celsius, which is generally used as an active layer, since the carrier lifetime is on the order of nanoseconds, the switching speed can be improved to a spin relaxation time of several tens ps. On the other hand, it is grown at a low temperature of about 200 degrees Celsius, and a p-type element or Be is ³⁷ cm ^-3 With the above addition, a higher-speed surface optical switch can be manufactured by using a quantum well layer having a carrier lifetime of 10 ps or less.
[0035]
By the way, in the above method, the polarization state of the parallel optical signal is limited to linearly polarized light. However, when considering applications in actual optical communication and the like, it is necessary to operate on an optical signal having an arbitrary polarization state. Therefore, in FIG. 5, the reflection type surface optical switches 211 and 211A, the λ / 4 wave plates 209 and 209A, and the lenses 210 and 210A are respectively arranged on two adjacent sides of the PBS 208, and the control light is circularly polarized. , The polarization independence of the parallel optical signal is enabled.
[0036]
The central circularly polarized control light is split into two orthogonal linearly polarized lights of the same intensity by the PBS 208, and becomes circularly polarized again by passing through the λ / 4 wavelength plates 209 and 209A, respectively. To reflect the parallel optical signal. In this case, since the control light intensities applied to the surface type optical switches 211 and 211A are completely equal, the reflectances of both are equal.
[0037]
Therefore, the parallel optical signal incident with an arbitrary polarization is split by the PBS 208 according to the polarization state and reflected by the optical switches 211 and 211A. The sum of the parallel optical signal intensities respectively reflected by 211 and 211A is always equal, and is multiplexed again by PBS 208 and output. That is, this makes it possible to realize polarization independence for the optical signal.
[0038]
In the method of FIGS. 2 to 5, in order to increase the number of parallel conversions, it is necessary to increase the number of microlens arrays 206. Accordingly, the ratio of the beam diameter of each input light to the diameter of the condenser lens 210 is reduced. Since the spot size becomes smaller, the size of the spot when condensed by the condensing lens 210 increases, and it may be necessary to increase the energy of the control light pulse in order to obtain the same power density. Further, since all optical signals are concentrated on the same spot, nonlinear effects such as a saturable absorption effect occur only with the optical signals, and the effect when the control light is irradiated may be weakened. There is a possibility that the influence of the heat generated by the absorption may be large.
[0039]
Therefore, as shown in FIG. 6, a method of bundling L optical fibers from one lens of the microlens array 206 and making an optical signal incident thereon is considered. Now consider the case of L = 2. When the optical fibers of A1 and A2 are arranged close to the input port of the control light pulse, the control light pulses emitted from each of them propagate with a slight difference in angle. The light is collected at two points. Similarly, if the optical fibers for B1 and B2 are arranged close to each other at the port for inputting the optical packet signal, the optical packet signals input from B1 and B2 are focused on the same spot as A1 and A2, respectively. As shown in FIG. 7, the branched optical packet signal is delayed by one bit, and the two control optical pulses are simultaneously output at the time when all the bits are aligned at the same time. Is irradiated. Light reflected at two different points on the surface-type optical switch 211 propagates again at different angles, and is collected at two different points by the microlens array 206 arranged on the output side. The light receiving element array 106 is arranged so as to be able to independently receive these parallel-converted light pulses. According to this method, the number of parallel conversions can be increased L times without increasing the size of the microlens array.
[0040]
On the other hand, the conventional electrical method required the same number of electrical serial-to-parallel converters to process a plurality of optical packets, but using this method, as shown in FIG. , And B2, another optical packet signal is input, so that a single optical-optical serial-parallel converter can be used to independently and simultaneously execute parallel conversion processing of a plurality of optical packet signals. .
[0041]
By inverting the input ports of the optical signal and the control light shown in FIGS. 2 to 8, an optical signal processing device for performing optical serial-optical parallel conversion as shown in FIG. 9 (corresponding to FIG. 2) is also provided. It becomes possible. That is, in FIG. 9, two types of optical signals are used, a high-speed signal light A and a low-speed repetitive probe light B. In FIG. 2, a serial optical signal A is input from a port for inputting control light, and an optical signal is input in FIG. A parallel probe light B (hereinafter, referred to as a probe light instead of a control light due to a difference in action) is input from a port to be connected, so that one serial signal light A is serial-parallelized by a plurality of probe lights B. Convert. At this time, the light pulse train of the signal light A and the probe light B is condensed by the condensing lens 203 to one point on a transmission type surface optical switch 204 having a semiconductor multiple quantum well layer, for example, as in FIG. Is done.
[0042]
The plurality of probe lights B spatially arranged are delayed by one bit of the signal light A for each port, and have different phases. If the number of the probe lights B is k, the cycle of each probe light B is k times of 1 bit of the signal light A. Therefore, a certain bit of the signal light A is the first probe light, the second bit is the second probe light, the third bit is the third probe light,..., The k-th bit is the k-th probe light. Is synchronized with For this reason, when the bit of the signal light A synchronized with the probe light B is “1”, the signal light increases the transmittance of the surface-type optical switch 204, so that the probe light becomes “1” and the probe light becomes “1”. When the bit of the signal light A synchronized with B is “0”, the probe light becomes “0” and appears on the lens 205 side.
[0043]
In this way, the probe light B of each port is sequentially modulated in transmittance by the multiple quantum well layer of the surface type optical switch 204 by the signal light A, and is developed spatially in parallel again by the rear condenser lens 205. . Thus, the information of the high-speed signal light A is parallel-converted into a plurality of lower-speed optical signals.
[0044]
Also in the configurations shown in FIGS. 3 to 8, it is possible to perform optical serial-optical parallel conversion in the same manner as described above. Furthermore, by integrally configuring the duplexer 201, the optical delay unit 202, and the optical fiber array 207 with a glass waveguide such as a PLC, it is possible to further reduce the size as a whole.
[0045]
In the above-described embodiment, since only one point of the surface type optical switch 204 or 211 is used, only one or two surface type optical switches 204 or 211 are required. An element can be manufactured.
[0046]
[Light pulse generator]
FIG. 10 is a circuit diagram illustrating a configuration example of an embodiment of an optical pulse generator that generates a control optical pulse (or a probe pulse) required for the optical serial-parallel conversion described above.
[0047]
In FIG. 10, reference numeral 71 denotes a single light emitting pulse generator that generates a single light pulse from an optical packet, and includes a power supply 41, a photoconductive switch 42, a capacitor 43, a differentiating circuit 44, and a semiconductor laser (LD) 45. . Reference numeral 72 denotes an optical pulse train generator that converts a single light pulse generated by the single light emission pulse generator 71 into a continuous light pulse, and is a loop-shaped waveguide formed on a PLC (Planar Lightwave Circuit). It comprises a waveguide 81, an optical coupler 82, a saturable absorber 83, and an optical amplifier 84.
[0048]
The single light emission pulse generator 71 includes a photoconductive switch 42 as a light receiving element to which a voltage Va is applied by a direct current power supply (DC power supply) 41, a capacitor 43 for charging a photocurrent output from the photoconductive switch 42, and the capacitor 43 And a semiconductor laser 45 driven by the output pulse of the differentiating circuit 44 to generate one optical pulse.
[0049]
In this configuration, as shown in the time chart of FIG. 11, when the first light pulse is input to the photoconductive switch 42, a photocurrent flows by the voltage Va and the capacitor 43 is charged. When the capacitor 43 is fully charged and the potentials at both ends of the photoconductive switch 42 become the same, the potential at the common connection point a between the photoconductive switch 42 and the capacitor 43 changes from Va even if there is a subsequent light pulse. And keep a constant value. The differentiating circuit 44 detects the rise of the voltage Va of the capacitor 43 to generate an electric pulse, and the semiconductor laser 45 is driven by the electric pulse. Therefore, even if a plurality of light pulses are input, the semiconductor laser 45 is driven only by the first light pulse.
[0050]
That is, the single light emission pulse generator 71 generates one optical pulse when irradiating the photoconductive switch 42 with an optical packet in which the leading bit is always set to “1”. If the charge of the capacitor 43 is extinguished in units of one packet by a discharge circuit (not shown), one light pulse is generated from the single light emission pulse generator 71 each time an optical packet arrives.
[0051]
This single optical pulse enters the loop-shaped waveguide 81 of the optical pulse train generator 72, and a part thereof is extracted to the output side by the optical coupler 82, but the remaining optical pulse is lost by the optical amplifier 84. Is compensated, and the loop of the waveguide 81 is swirled. Therefore, by adjusting the loop length of the waveguide 81, a control light pulse train having a desired period can be extracted to the output side.
[0052]
The saturable absorber 83 inserted into the loop waveguide 81 has a different transmittance depending on the light intensity, and is for suppressing the oscillation of the spontaneous emission light emitted from the optical amplifier 84. Further, by using the voltage of the capacitor 43 as the control signal of the optical amplifier 84, it is possible to continue outputting the optical pulse only during the continuation of the optical packet, and to terminate the output of the optical pulse almost simultaneously with the end of the optical packet. Although the waveguide 81 using PLC is used here, a waveguide using an optical fiber may be used.
[0053]
FIG. 12 is a diagram showing a configuration of a control light pulse train generating apparatus in which the above single light emitting pulse generator 71 is combined with another light pulse train generator 72A having another structure for generating a repetitive light pulse. The optical pulse train generator 72A includes a PBS 85, a λ / 4 wavelength plate 86, an optical amplifier 87 having an anti-reflection film on the left side and an appropriate reflection film of about 30% on the right side in FIG. In the figure, the saturable absorber 88 has a high reflection film on the left side.
[0054]
In the optical pulse train generator 72A, when one optical pulse is input from the single light emission pulse generator 71, the optical pulse passes through the PBS 85 and the λ / 4 wavelength plate 86 and becomes circularly polarized light. The light is then reflected and transmitted through the λ / 4 wavelength plate 86 again, so that the light is converted to linearly polarized light having a polarization orthogonal to the original input light pulse by 90 degrees, reflected by the PBS 85 and output to the outside. At this time, a part of the light pulse reflected by the saturable absorber 88 is again amplified by the optical amplifier 87, then reflected on the right side of the optical amplifier 87, and reflected again by the saturable absorber 88. By repeating this, a pulse train of the control light can be extracted from the output side.
[0055]
In the configuration of the optical pulse train generator 72A of FIG. 12, a pulse train having a desired period can be obtained by adjusting the distance between the optical amplifier 87 and the saturable absorber 88. Here, a simple optical circulator function is realized by using the PBS 85 and the λ / 4 wavelength plate 86. However, as long as it has an optical circulator function, the same applies to other configurations. Can be used.
[0056]
As described above, in the optical pulse generator of the present embodiment, since only the first bit of the optical packet is accurately extracted with a very simple and compact configuration, it is possible to extract a high-speed burst signal which is difficult with the conventional electrical method. Of a single optical pulse can be generated. Furthermore, in the optical pulse generation device of the present embodiment, after the head bit charges the capacitor, the operation is performed regardless of the intensity, so that even if the intensity of the input optical packet fluctuates, the intensity of the output optical pulse is kept constant. be able to. Further, it is possible to fix the polarization state of the output light pulse to an input light packet having an arbitrary polarization state. This is an indispensable condition when used as control light (or probe light) for the light-light type serial-parallel converter. Further, in the conventional electrical method, a high-speed electronic circuit having the same band is required to extract a clock from a high-speed optical packet. However, in the optical pulse generator of the present embodiment, the gain of the semiconductor laser Gain- Since the switch method is used, a driving electric pulse of about several hundred ps is sufficient, that is, a band required for an electronic circuit may be as slow as about several GHz. An optical pulse directly generated by the gain-switch method of a semiconductor laser is about 10-20 ps in the current technology, and can correspond to an optical packet of about 10-40 Gbps. However, a pulse compression technique using a fiber or the like is required. If it is used, it can be easily compressed to about 3 ps, so that it is possible to cope with extremely high-speed optical packet processing of 100 Gbps or more. Further, a single optical pulse generated every time an optical packet arrives can generate an optical pulse train having an arbitrary period by the configuration of FIG. 10 or FIG.
[0057]
[Label recognition circuit]
As described in the section of the related art, in optical packet communication, it is necessary for a router to read address information included in a label (also referred to as a header) of a high-speed optical packet instantaneously. FIG. 13 is a diagram showing an embodiment of an optical signal processing device for processing label information of an optical packet, in which the above-mentioned single pulse generator 71 and an optical serial-parallel converter are combined.
[0058]
In FIG. 13, the input optical packet is split into two, one of which is input to the single light emission pulse generator 71 described in FIG. 10 to generate one control light pulse. 2- The optical serial-to-parallel converter 32 described with reference to FIG. The other divided optical packet is demultiplexed by the demultiplexer 23 into n pieces of the same number as the number of bits of the label, and after the n pieces are delayed by one bit by the optical delay 24, the optical serial-parallel conversion is performed. The gate of the planar optical switch 204 of the optical serial-parallel converter 32 is opened by the control pulse.
[0059]
At this time, when the timing of the control light pulse output from the light pulse generator 71 is adjusted to a certain appropriate time, all the pulses of the optical label are simultaneously irradiated to the surface type optical switch 204 at the same time. . Therefore, when the gate of the surface type optical switch 204 is opened only at a certain moment by the control light, all the optical pulses of the optical label are spatially output in parallel. These parallel n light pulses emitted from the optical serial-parallel converter 32 are converted into electric signals by a photoelectric conversion unit 33 having n low-speed light-receiving elements, and the electric signals are thereafter formed by a silicon LSI. Is sent to the label processing circuit 34, and the label processing circuit 34 can decode the information of the label.
[0060]
By the way, the input optical packet is branched into two, and one control light pulse generated from one of the optical packets by the single light emission pulse generator 71 is divided into a demultiplexer similar to the demultiplexer 23 and the light Through the same optical delay device as the delay device 24, n probe lights of the same number as the bit number of the label are generated, and this probe light and the other optical packet branched are converted into the optical serial-parallel conversion described in FIG. As can be seen from FIG. 9, optical serial-to-parallel conversion of the label portion of the optical packet is possible, and thus label identification is possible. However, in this case, unlike the configuration shown in FIG. 13, the label portion of the optical packet cannot be parallel-converted at once, and is not suitable for instantaneous reading of label information.
[0061]
[Optical memory]
Next, an embodiment of an optical memory to which the present invention is applied will be described. In the present embodiment, as in the previous embodiment, the first bit of an input optical packet is always set to “1”, and a single optical pulse is always generated at the same timing every time an optical packet is input. This is put in a loop-shaped optical waveguide to generate an optical pulse train having a period k times the bit period of the optical packet. Also, using the optical pulse train, an input optical packet is converted into k parallel optical signals by optical-optical serial-parallel conversion, and the k parallel optical signals are converted into k parallel optical signals by a light receiving element. After being converted into an electric signal, it is simultaneously written into k memory circuits constituted by electronic circuits. For reading from the k memory circuits, k parallel electric signals are read simultaneously, converted into one optical pulse train by electro-optical parallel-serial conversion, and output as an optical packet.
[0062]
The optical-optical serial-parallel conversion uses a transmission-type or reflection-type surface optical switch having a semiconductor multiple quantum well layer, thereby realizing an extremely small size and low power consumption as a whole. Even in the electric-optical parallel-serial conversion, an extremely simple configuration is used as described later. As described above, the configuration in which light is actively used for the input / output portion and the Si-based electronic memory circuit is used for the memory portion enables a very high-speed burst optical signal to be handled, and a large capacity, small size, An optical memory with low power consumption can be realized. The details will be described below.
[0063]
FIG. 14 is a diagram showing the entire configuration of the optical memory device according to the present invention. The input optical packet P is split into two by a demultiplexer (not shown), and one of them is input to the optical pulse train generator 100 described with reference to FIG. 10 or FIG. 12, where k of the bit period of the original optical packet is k. A low-speed optical pulse train with a double cycle is generated. The optical pulse train is input to the above-mentioned optical-optical serial-parallel converter 200, where the other optical packet is converted into k low-speed parallel optical pulse trains (having a period k times the bit period of the original optical packet). Convert to a signal. This parallel optical pulse train signal is output simultaneously for each k bits. Each of the k-bit parallel optical pulse train signals is converted into an electric signal by the low-speed light-receiving element array 300, and the electric signal is converted into one electric signal in k arrays of the Si-based memory cell array 401 in which the column and row addresses are shared. Are held at the same time.
[0064]
As shown in FIG. 15, an array 400 of a Si-based memory cell array (hereinafter, referred to as a memory array) has k memory cell arrays 401 corresponding to the k light receiving elements 301 included in the light receiving element array 300. Then, reading and writing are performed by the column address circuit 403 and the row address circuit 404 controlled by the control circuit 402. That is, when one address is designated by both address circuits 403 and 404, k data are simultaneously written into each memory cell array 401. As described above, the optical packet is converted into parallel data by k bits one by one while the optical packet is continued by the optical pulse train generated by the optical pulse train generator 100 and written into the memory array 400. It will be written to the memory circuit. At this time, the bit rate of the optical packet signal can be increased up to k times the writing speed of the memory cell array 401.
[0065]
When reading data written in each memory cell array 401, k data is simultaneously output every time an address is designated by both address circuits 403 and 404. The electric data read out in this manner is output again as one high-speed optical packet signal by the electric-optical parallel-serial converter 500.
[0066]
As a method of sending the k output electric signals from the memory array 400 to the electro-optical parallel-serial converter 500, as shown on the left side of FIG. 16, the surface-emitting laser 405 converts the electric signals into optical signals. Thereafter, the contact point 406 and the contact point 502 are adhered by an optical I / O method in which the light signal is converted again into an electric signal by the light receiving element 501 or as shown on the right side of FIG. A sending method can be used.
[0067]
[Electric-optical parallel-serial converter]
FIG. 17 is a diagram showing a configuration example of the electric-optical parallel-serial converter 500. An optical pulse light source 503 oscillates a pulse having a period k times the bit period of the original optical packet. Reference numeral 504 denotes a demultiplexer, 505 denotes k optical modulators, 506 denotes an optical delay device, and 507 denotes an optical multiplexer. Of these, the waveguide portion is constituted by PLC. Note that the optical delay unit 506 may be provided between the demultiplexer 504 and the optical modulator 505.
[0068]
As described above, in the memory array 400, when the address of the written data is specified and read, k low-speed electric signals are simultaneously output from the k memory cell arrays 401 whose addresses are shared. These k parallel electric signals are supplied to k optical modulators 505, respectively. The light pulse from the light pulse light source 503 is divided into k pulses by the demultiplexer 504, and when passing through the k light modulators 505, the light pulse is modulated by the k electric signals and modulated. The optical pulses are delayed by one bit by the optical delay unit 506 and then combined by the multiplexer 507. As described above, the k low-speed parallel electric signals are reconstructed into one high-speed optical packet whose bit period is 1 / k times again.
[0069]
FIG. 18 is a diagram showing another configuration example of the electric-optical type parallel-serial converter 500. In the electro-optical type parallel-serial converter 500 shown in FIG. 17, when k is large, a large amount of optical modulator is required.
[0070]
Therefore, when k is large as described above, as shown in FIG. 18, k parallel electric signals are bundled in units of n to create m parallel electric signal trains (k = n × m). Similarly to the above, the original high-speed optical packet signal is output again by the m optical modulators 505A. As a result, the number of required optical modulators can be significantly reduced (1 / n).
[0071]
To bundle the n parallel electric signals, n of the k parallel electric signals output simultaneously from the RAM array 400 are supplied to the drains of the n transistors 508 as a bias power supply. FIG. 18 shows only one set of n transistors 508 and related parts, but m sets of such circuits are used. Then, an electric pulse is input to the gate of each transistor 508 to sample a part of the electric signal, and the sampling signal charges a capacitor 509 connected to the source of the transistor. The above-described transistor 508 and capacitor 509 constitute a sample-and-hold unit, where n electrical signals are sampled and held at the same time.
[0072]
Further, the optical clock (the cycle is k times the bit cycle of the original optical packet) is delayed one bit at a time by an optical delay unit 511 composed of a PLC or the like, and is sequentially irradiated on the n photoconductive switches 510. The electric charges accumulated in each capacitor 509 are sequentially discharged, and are converted by the load resistor 512 into an electric pulse train signal in which n pulses are continuous. The photoconductive switch 510, the optical delay unit 511, and the load resistor 512 constitute an electric-electric type parallel-serial conversion unit.
[0073]
The electric pulse train signal obtained as described above is input to one of the optical modulators 505A. In this case, k parallel signals are modulated by the optical modulator 505A in n divisions every m lines. The pulse cycle output from the optical pulse light source 503A used here is set to be m times the bit cycle of the original optical packet. In this way, k data are sequentially read, and the original optical packet is output as a whole.
[0074]
As described above, according to the above embodiment of the present invention, there is provided a large-capacity optical memory device capable of writing a high-speed burst optical packet signal to a Si-based memory circuit and freely reading it again as a high-speed optical packet. It can be realized with small size and low power consumption.
[0075]
[Other embodiments]
The optical memory device of the present invention can be used as an optical buffer memory for avoiding collision between optical packets in a router device, and can be used at a high speed in a data center that stores a large amount of data and retrieves data as needed. It can also be used as an optical memory device for transmitting and receiving optical packet signals. Furthermore, in a high-speed optical computer, it can be used as a cache memory for exchanging data instantaneously. Furthermore, by storing a high-speed optical packet signal in a memory once and outputting it as a lower-speed optical packet when reading (low-speed to high-speed conversion is also possible), it can be used as a bit rate converter necessary for an edge node or the like. It can be used.
[0076]
Also, as can be understood from the above description, the present invention combines the above-described techniques such as serial-parallel conversion, optical clock pulse generation, and parallel-serial conversion according to the present invention to achieve label processing, optical memory, and optical bit rate. Functions such as conversion can be realized, and by combining them, a high-performance optical information processing apparatus or system such as a high-performance router or optical computer can be realized.
[0077]
【The invention's effect】
As described above, according to the present invention, it is possible to configure a high-speed optical signal processing device with low power consumption, simple and small size.
[0078]
Further, according to the present invention, it is possible to cope with a burst signal, and it is also possible to freely perform a partial processing or a whole processing of a high-speed optical packet.
[0079]
Further, according to the present invention, by combining the above-described technologies such as serial-parallel conversion, optical clock pulse generation, and parallel-serial conversion, and using a label recognition circuit or an electronic memory as an electronic circuit, an extremely high speed in the future can be achieved. High-speed optical label recognition (a function to read address information of optical packets and determine output ports), which is indispensable as a router function, and a high-speed optical buffer memory (to prevent optical packets from colliding at output ports, (A function of temporarily saving), optical bit rate conversion (conversion of high-speed optical packets to low-speed optical packets, or vice versa), and the like.
[0080]
Further, by integrating functions such as label processing, optical memory, and optical bit rate conversion according to the present invention, an optical information processing apparatus or an optical information processing system having higher-order functions such as a high-performance router and an optical computer can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of an optical signal processing device according to the present invention.
FIG. 2 is an explanatory diagram of one embodiment of the present invention for performing serial-parallel conversion of an optical signal sequence.
FIG. 3 is an explanatory diagram of one embodiment of the present invention for performing serial-parallel conversion of an optical signal sequence.
FIG. 4 is an explanatory diagram of one embodiment of the present invention for performing serial-parallel conversion of an optical signal sequence.
FIG. 5 is an explanatory diagram of one embodiment of the present invention for performing serial-parallel conversion of an optical signal sequence.
FIG. 6 is an explanatory diagram of one embodiment of the present invention for performing serial-parallel conversion of an optical signal sequence.
FIG. 7 is an explanatory diagram of one embodiment of the present invention for performing serial-parallel conversion of an optical signal sequence.
FIG. 8 is an explanatory diagram of one embodiment of the present invention for performing serial-parallel conversion of an optical signal sequence.
FIG. 9 is an explanatory diagram of one embodiment of the present invention for performing serial-parallel conversion of an optical signal sequence.
FIG. 10 is a circuit diagram of an optical pulse generator according to an embodiment of the present invention.
FIG. 11 is a time chart of the single pulse generator of FIG. 10;
FIG. 12 is a circuit diagram of an optical pulse generator according to one embodiment of the present invention.
FIG. 13 is a block diagram of an optical signal processing device according to an embodiment of the present invention that performs label recognition of an optical packet.
FIG. 14 is a block diagram of an optical random access memory device according to an embodiment of the present invention.
FIG. 15 is a detailed explanatory diagram of a Si-based RAM array part.
FIG. 16 is an explanatory diagram of a method of transferring electric data output from a Si-based RAM array to an electric-optical parallel-serial converter.
FIG. 17 is an explanatory diagram of an electric-optical parallel-serial converter according to an embodiment of the present invention.
FIG. 18 is an explanatory diagram of another example of an electric-optical parallel-serial converter according to an embodiment of the present invention.
FIG. 19: Conventional optical packet communication system FIG. 3 is a block diagram showing a configuration example of the present invention.
[Explanation of symbols]
1 O / E receiving circuit
2 Electric clock signal generator
3 Electric serial-parallel converter
4 Si memory cell array
5 Electric parallel-serial converter
6 E / O transmission circuit
23 demultiplexer
24 Optical delay device
32 Optical-optical serial-parallel converter
34 Label Recognition Circuit
35 Photoelectric converter
41 power supply
42 Photoconductive switch
43 Capacitor
44 Differentiating circuit
45 Semiconductor laser (LD)
71 Single optical pulse generator
72, 72A Optical pulse train generator
81 Looped director
82 optical coupler
83 Saturable absorber
84 Optical Amplifier
85 Polarizing Beam Splitter (PBS)
86 λ / 4 wavelength plate
87 Optical Amplifier
88 Saturable absorber
100 Optical pulse train generator
102 Optical pulse generator
104 Optical-optical serial-parallel converter
106 light receiving element array
108 silicon electronic circuit
200 Optical-optical serial-parallel converter
201 duplexer
202 Optical delay unit
203,205 Condensing lens
204 Transmission type optical switch
206 micro lens array
207 Optical fiber (optical fiber array)
208 Polarizing Beam Splitter (PBS)
209 λ / 4 wavelength plate
210 Condensing lens
211 Reflective surface type optical switch
300 light receiving element array
301 light receiving element
400 Si RAM array
401 memory cell array
402 control circuit
403 column address circuit
404 row address circuit
405 surface emitting laser
406, 502 contacts
500 Electric-optical parallel-serial converter
501 light receiving element
503, 503A Optical pulse light source
504, 504A duplexer
505, 505A optical modulator
506, 506A Optical delay device
507, 507A multiplexer

Claims (23)

One or more optical pulse generators for generating a single optical pulse from one or a plurality of input burst optical packets input in parallel,
One optical-optical serial-parallel converter for separating a part or all of the bit signals of the input optical packet by the single optical pulse collectively and spatially in parallel;
A photoelectric converter for converting a parallel optical signal pulse developed in parallel by the optical-optical serial-parallel converter into a low-speed electric signal;
An electronic circuit for processing the electric signal converted by the photoelectric converter. One or more optical pulse generators for generating a single optical pulse from a plurality of input burst optical packets input in one or in parallel,
One or more optical pulse train generators that convert the single optical pulse into an optical pulse train that is repeated only for the duration of the input burst optical packet;
One optical-optical serial-parallel converter that repetitively spatially separates a predetermined number of bits of the input burst optical packet by the optical pulse train in parallel;
A photoelectric converter that converts parallel optical signal pulses developed in parallel by the optical-optical serial-parallel converter into low-speed parallel electric signals;
An electronic circuit for processing the parallel electric signal converted by the photoelectric converter. The apparatus of claim 1, wherein the light pulse generator comprises:
DC power supply,
A capacitor,
A photoconductive switch that fully charges the capacitor from the DC power supply upon receiving a leading optical pulse of an input optical packet;
A differentiation circuit for differentiating the voltage of the capacitor,
An optical signal processing apparatus comprising: a semiconductor laser that generates one optical pulse by an electric pulse output from the differentiating circuit. 3. The apparatus of claim 2, wherein the input optical signal sequence is an optical packet signal, and the optical pulse generator comprises:
DC power supply,
A capacitor,
A photoconductive switch that fully charges the capacitor from the DC power supply upon receiving a leading optical pulse of an input optical packet;
A differentiation circuit for differentiating the voltage of the capacitor,
A semiconductor laser that generates one light pulse by one electric pulse obtained by the differentiating circuit;
A loop waveguide for inputting one optical pulse obtained by the semiconductor laser,
A saturable absorber and an optical amplifier inserted into the waveguide;
An optical signal processing device comprising: a photocoupler for extracting an optical pulse train obtained by the waveguide. 3. The device according to claim 1, wherein the light-light type serial-parallel converter comprises:
A demultiplexer for demultiplexing an input optical packet signal into k parallel optical signals;
An optical delay unit for sequentially delaying each of the k optical signals demultiplexed by the demultiplexer by one bit;
A transmission type surface optical switch,
A first lens for condensing the k parallel optical signals delayed by 1 bit by the optical delay unit and the single optical pulse at one point of the surface-type optical switch;
An optical signal processing device comprising: a second lens that spatially separates the k parallel optical signals transmitted through the surface-type optical switch. 3. The device according to claim 1, wherein the light-light type serial-parallel converter comprises:
A demultiplexer for demultiplexing an input optical packet signal into k parallel optical signals;
An optical delay unit for sequentially delaying the k optical signals demultiplexed by the demultiplexer by one bit, and k parallel optical signals delayed by one bit by the optical delay unit and circularly or linearly polarized light; A polarizing beam splitter through which the control light pulse passes;
A λ / 4 wavelength plate disposed on the entire surface on one or two output sides of the polarizing beam splitter, or only on a portion through which a central control light pulse passes;
A lens for condensing the transmitted light of the polarization beam splitter and the λ / 4 wavelength plate at one point,
An optical signal processing device comprising: a reflection type surface optical switch that receives light collected by the lens. 3. The device according to claim 1, wherein the light-light type serial-parallel converter comprises:
A demultiplexer for demultiplexing the input optical packet signal into k × L parallel optical signals, and an optical delay for sequentially delaying the k × L optical signals demultiplexed by the demultiplexer one bit at a time Vessels,
A demultiplexer for demultiplexing the input control light pulse, which is the single optical pulse, into L light, and each of the k × L optical signals demultiplexed by the demultiplexer and delayed by the optical delay device And L total of (k + 1) × L optical waveguides for propagating each of the control light pulses, and k + 1 lenses for converting the light output from the optical waveguide into parallel light. A lens array,
A polarization beam splitter through which the k parallel optical signals delayed by one bit and the control light pulse of circular polarization or linear polarization pass;
A λ / 4 wavelength plate disposed on the entire surface of one or two output sides of the polarization beam splitter or only in a central portion where the control light pulse passes, and a λ / 4 wavelength plate comprising the polarization beam splitter and the λ / 4 wavelength plate. A lens for collecting transmitted light,
A reflective surface-type optical switch that receives light collected by the lens;
An optical signal processing device comprising: a lens array including k + 1 lenses for separating and condensing light reflected by the surface-type optical switch and output from the polarization beam splitter. 3. The device according to claim 1, wherein the light-light type serial-parallel converter comprises:
L demultiplexers for demultiplexing each of the L optical packet signals input in parallel into k parallel optical signals, and one beam of the k optical signals demultiplexed by the demultiplexer. L optical delayers for sequentially delaying
A demultiplexer for demultiplexing the input control light pulse, which is the single optical pulse, into L light, and each of the k × L optical signals demultiplexed by the demultiplexer and delayed by the optical delay device And a total of (k + 1) × L optical waveguides for transmitting the L control light pulses and k + 1 lenses for converting the light output from the optical waveguide into parallel light An array,
A polarization beam splitter through which the parallel optical signal and the circularly or linearly polarized control light pulse pass,
A λ / 4 wavelength plate disposed on the entire surface on one or two output sides of the polarizing beam splitter, or only on a portion through which a central control light pulse passes;
A lens for condensing light transmitted through the polarizing beam splitter and the λ / 4 wavelength plate, a reflection type surface optical switch for receiving the light condensed by the lens, and a light reflected by the surface type optical switch An optical signal processing device comprising: a lens array configured by k + 1 lenses for separating and condensing the light output from the polarization beam splitter. 2. The apparatus according to claim 1, wherein the electronic circuit is a label recognition circuit for identifying optical label information of an optical packet signal, and the entire optical signal processing apparatus is used as an optical label processing apparatus. Optical signal processing device. 10. The optical signal processing device according to claim 9, wherein the optical label processing device is used for a router. 11. The device according to claim 9, wherein the electronic circuit includes a label recognition circuit for identifying a label of the input optical signal sequence, and the optical signal processing device as a whole transmits a high-speed optical packet signal to an electronic memory array. An optical signal processing device, which is a writable optical memory device. An optical pulse generator that generates a low-repetition optical pulse train from an input burst optical packet;
An optical-optical serial-parallel converter for repetitively spatially separating the input optical packet by k bits by the optical pulse train in parallel;
K photoelectric converters for converting k parallel optical signal pulses developed in parallel by the optical-optical serial-parallel converter into low-speed parallel electric signals;
An electronic memory array for writing the parallel electrical signals,
An electro-optical parallel-serial converter for reconstructing the k parallel electric signals read from the electronic memory array into a serial optical packet signal again;
An optical memory device comprising: 13. The device of claim 12, wherein the light pulse generator comprises:
DC power supply,
A capacitor,
A photoconductive switch for fully charging the capacitor from the DC power supply upon receiving a leading pulse of an input optical packet signal;
A differentiation circuit for differentiating the voltage of the capacitor,
A semiconductor laser that generates one light pulse by one electric pulse signal obtained by the differentiating circuit;
A loop waveguide for inputting one optical pulse obtained by the semiconductor laser,
A saturable absorber and an optical amplifier inserted into the waveguide;
An optical memory device comprising: a photocoupler for extracting an optical pulse train obtained by the waveguide. 13. The device of claim 12, wherein the light-light type serial-parallel converter comprises:
A demultiplexer for demultiplexing the input optical packet signal into k parallel optical signals;
An optical delay unit for sequentially delaying each of the k optical signals demultiplexed by the demultiplexer by one bit;
A polarization beam splitter through which k parallel optical signals delayed by one bit by the optical delay unit and a control light pulse which is the light pulse train of circularly or linearly polarized light pass; and one or two of the polarization beam splitters A λ / 4 wavelength plate disposed on the entire surface on one of the output sides or only in the portion where the central control light pulse passes;
A lens for condensing the transmitted light of the polarization beam splitter and the λ / 4 wavelength plate at one point,
An optical memory device comprising: a reflection type surface optical switch for receiving light condensed by the lens. 13. The device of claim 12, wherein the light-light type serial-parallel converter comprises:
A demultiplexer for demultiplexing one input optical packet signal into k × L parallel optical signals; and sequentially delaying the k × L optical signals demultiplexed by the demultiplexer by one bit. An optical delay unit, and a demultiplexer that demultiplexes the input control pulse, which is the optical pulse train, into L pulses.
A total of (k + 1) × L optical waveguides for propagating the k × L optical signals and the L control optical pulses that are demultiplexed by the demultiplexer and delayed by the optical delay device; A lens array including k + 1 lenses for converting the light output from the optical waveguide into parallel light;
A polarization beam splitter through which the k parallel optical signals delayed by one bit by the optical delay unit and the control light pulse of circularly or linearly polarized light pass;
A λ / 4 wavelength plate disposed on the entire surface on one or two output sides of the polarizing beam splitter, or only on a portion through which a central control light pulse passes;
A lens for condensing light transmitted through the polarizing beam splitter and the λ / 4 wavelength plate, a reflection type surface optical switch for receiving the light condensed by the lens, and a light reflected by the surface type optical switch An optical memory device, comprising: a lens array configured by k + 1 lenses for separating and condensing light output from the polarization beam splitter. 13. The device of claim 12, wherein the light-light type serial-parallel converter comprises:
One demultiplexer for demultiplexing each of the L optical packet signals input in parallel into k parallel optical signals;
L optical delay devices for sequentially delaying each of the k optical signals demultiplexed by the demultiplexer by one bit;
A demultiplexer for demultiplexing the control light pulse, which is the input optical pulse train, into L light beams; k × L light signals demultiplexed by the demultiplexer and delayed by the optical delay device; A total of (k + 1) × L optical waveguides for transmitting each of the control light pulses, and a lens array including k + 1 lenses for converting the light output from the optical waveguide into parallel light. ,
A polarization beam splitter through which the parallel optical signal and the control light pulse of circular polarization or linear polarization pass,
A λ / 4 wavelength plate disposed on the entire surface of one or two output sides of the polarization beam splitter or only at a central portion where the control light pulse passes, the polarization beam splitter, and the λ / 4 wavelength plate A lens for condensing the transmitted light of
A reflective surface-type optical switch that receives light collected by the lens;
An optical memory device for separating and condensing light reflected by the surface-type optical switch and output from the polarizing beam splitter, the lens array including k + 1 lenses. 13. The device of claim 12, wherein the electro-optical parallel-to-serial converter comprises:
An optical pulse light source,
A demultiplexer that splits an optical signal output from the optical pulse light source into k signals,
K optical modulators for modulating k separated parallel optical signals with k parallel electric signals read from the k electronic memory arrays;
An optical delay unit that delays k parallel optical signals by one bit at an input side or an output side of the k optical modulators;
An optical memory device, comprising: a multiplexer that multiplexes the delayed k parallel optical signals into one optical pulse train to generate an optical packet signal. 13. The device of claim 12, wherein the electro-optical parallel-to-serial converter comprises:
M (m = k / n) sets of sample-and-hold units for sampling the k parallel electric signals read from the k electronic memory arrays in units of n;
M sets of electric-electric type parallel-serial conversion units for taking out the electric charges sampled and stored in units of n units in the sample and hold unit as one electric pulse train signal,
An optical pulse light source,
A demultiplexer for demultiplexing the optical signal output from the optical pulse light source into m optical signals;
M optical modulators for modulating m parallel optical signals split by the splitter with m parallel electric signals output from the m sets of electric-electric type parallel-serial converters;
An optical delay unit that delays the m parallel optical signals by one bit at an input side or an output side of the m optical modulators;
An optical memory device, comprising: a multiplexer that multiplexes the m parallel optical signals delayed by the optical delay unit into one optical pulse train to form an optical packet signal. 19. The optical memory device according to claim 12, wherein said optical memory device is used for a router. An optical signal processing method that enables high-speed optical packet signal processing,
Each of a plurality of L burst optical packet signals input in one or in parallel is branched into two,
Using a leading bit of one optical packet signal of the two optical packet signals, each generates a single optical pulse,
Using the single optical pulse, part or all of the other optical packet signal that has been branched is converted into k parallel optical signals at a time,
The k or k + L parallel optical signals are converted into k or k + L low-speed parallel electric signals by a low-speed photoelectric conversion element,
Inputting the parallel electric signal to an electronic circuit. 21. The method of claim 20 , wherein converting one optical packet signal of the two branched optical packet signals into the k parallel optical signals comprises:
Irradiating the single light pulse to one point of the surface type optical switch to modulate transmittance or reflectance at that point;
Branching the other optical packet into k pieces, sequentially shifting the phase by one bit, and irradiating the k optical packets to the same point of the surface type optical switch;
Only the optical pulse in the optical packet that has entered the surface-type optical switch at the same timing as the single optical pulse transmits or reflects through the surface-type optical switch, so that part or all of the optical pulse of the optical packet is transmitted. Including the step of converting to parallel,
An optical signal processing method, comprising: converting the parallel light pulse into a low-speed parallel electric signal by a low-speed photoelectric converter, and reading label information of the parallel electric signal by a label recognition circuit. The input burst optical packet signal is split into two,
An optical pulse train having a period k times the bit period of the optical packet signal is generated using one optical packet signal of the branched optical packet signals,
Using the optical pulse train, convert the other branched optical packet signal into k parallel optical signals,
Converting the k parallel optical signals into k parallel electrical signals;
Writing the k parallel electric signals into k electronic memory arrays formed by electronic circuits;
An optical memory comprising a step of converting the k parallel electric signals obtained by simultaneously reading out the k parallel electric signals from the k electronic memory arrays into one optical pulse train and outputting them as an optical packet signal. Method. 23. The method of claim 22 , wherein converting one optical packet signal of the two branched optical packet signals into k parallel optical signals,
Irradiating an optical pulse train generated based on the optical packet to one point of the surface-type optical switch, and modulating transmittance or reflectance at that point;
The other branched optical packet is branched into k pieces, the phase is shifted by one bit, and these k optical packets are irradiated on the same point of the surface type optical switch,
Only the optical pulse in the optical packet incident on the surface type optical switch at the same timing as the optical pulse train is transmitted or reflected by the surface type optical switch, thereby converting the optical packet into k bits in parallel. ,
An optical memory method, comprising: converting the parallel light pulse into a low-speed parallel electric signal by a low-speed photoelectric converter, and writing the parallel electric signal to a silicon-based electronic memory array.

Images