JP3577451B2 - Semiconductor wafer and semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor wafer and a semiconductor device, a sheet material different from the wafer is attached to the surface of the wafer and the back surface of the wafer is thinned, and a metal film is formed on the back surface of the thinned wafer by vapor deposition or the like, The present invention relates to a technique for shielding the front and back surfaces of a semiconductor IC chip from light.
[0002]
[Prior art]
2. Description of the Related Art There has been remarkable progress in making electronic devices smaller, lighter, more functional, and more sophisticated. Mobile phones and the like are the most prominent ones, but all components, including integrated circuits (ICs) mounted on these devices, are required to be similarly reduced in size and weight.
2. Description of the Related Art Conventionally, flip chip mounting is one of the most prominent methods for reducing the size and thickness of an IC mounting structure. This method was developed because as the size of the substrate on which the IC or the like is mounted, the so-called module size, becomes smaller, the IC must be thinner and smaller. It has a structure in which a bump is applied and the bump and the pattern on the substrate are connected face to face. Therefore, flip-chip mounting is also referred to as face-down mounting from this mode.
[0003]
In addition, resin is filled between the chip and the board. The reason is that the connection strength between the bump and the pattern on the board alone is weak, and the connection is poor in reliability tests such as temperature cycle tests and high-temperature high-humidity storage tests. This is to prevent a disconnection failure and to prevent this.
Specifically, FIG. 1 shows an outline of the conventional flip chip mounting structure. In FIG. 1, the IC chip is 1, the bump is 3, the substrate is 7, the resin is 8, and the wiring pattern on the substrate is 9.
A bump 3 is provided on an electrode pad (not shown) of the IC chip 1. The material of the bump 3 is a conductive substance, and usually, solder, gold wire, or the like is used. A method of manufacturing a bump with a gold wire or the like is to bond the chip to an electrode pad of an IC chip, and then cut and tear the wire portion with a clamp of a wire bonder. By connecting the bump 3 and the wiring pattern 9 on the substrate 7, an electric signal is input to the IC chip 1 from the wiring pattern 9 on the substrate 7, processed in the IC chip 1, and processed by another IC chip 1. The signal is output to the wiring pattern 9 as an output signal.
[0004]
As another method of improving the connection durability of the flip-chip mounting structure, a structure in which another material is bonded to a chip is disclosed in Japanese Patent Application Laid-Open No. 1-196442.
This is shown in FIG. In FIG. 2, the IC chip on which the circuit is formed is denoted by 1, the plate member is denoted by 2, the bump is denoted by 3, the substrate is denoted by 7, the resin is denoted by 8, and the wiring pattern is denoted by 9.
In the same manner as described above, the bumps 3 are provided on the electrode pads (not shown) of the IC chip 1. The bump 3 is a conductive material. The bump 3 and the wiring pattern 9 on the substrate 7 are connected. Thus, a signal from the substrate 7 is input to the circuit of the IC chip 1, and an output signal processed in the circuit is output to the output signal wiring pattern 9 of the substrate 7. The resin 8 is bonded between the IC chip 1 and another IC chip. A major difference from the example of FIG. 1 is that a plate 2 is attached to the upper part of the IC chip 1. The reason for this is that the stress generated locally on the bumps 3 on the electrode pads of the IC chip 1 due to the bending and torsion of the substrate 7 is alleviated by bonding with the resin 8 as a whole.
[0005]
In FIG. 1 showing a conventional flip-chip mounting structure, a wiring pattern 9 is also provided at the lower center of the IC chip 1, but this is for shielding the LSI pattern of the IC chip 1 from light. The reason for shading is that when light is applied to the semiconductor, electrons in the charge band and impurity level absorb photon energy, generate photoconductivity inside the semiconductor, and generate photoelectromotive force at the interface. This is to cause a malfunction. This phenomenon is caused especially by infrared rays. In addition, in the case of an LSI such as an EPROM other than the infrared ray, it is necessary to pay attention to erase the internal data when the ultraviolet ray is applied. A resin 8 is filled between the IC chip 1 and the substrate 7. This is to improve the adhesion between the IC chip 1 and the substrate 7 by filling the resin, thereby improving the reliability.
[0006]
[Problems to be solved by the invention]
However, the above prior art has the following problems.
There is an increasing need to mount IC cards and the like thinly. Although mounting on a 0.7 mm card is possible by conventional flip-chip mounting, it is difficult to perform light-shielding processing on the LSI surface of an IC chip that has been flip-chip mounted. This is because the distance between the substrate and the LSI pattern is as thin as 50 μm, which is almost the same as the height of the bump, and it is extremely difficult to perform light shielding on the LSI pattern itself. If the height of the bumps is increased to about 100 μm, it is possible to perform light-shielding processing on the LSI pattern itself. In that case, however, the thickness of the IC chip is set to 200 μm and the IC chip is mounted on the substrate. Assuming that the thickness including the wiring is 230 μm, the total thickness is 530 μm (0.53 mm), which is a very thick module.
[0007]
In order to apply a light-shielding process to the LSI pattern itself and to reduce the module thickness, it is necessary to reduce the wafer thickness to 100 μm or less (0.1 mm). It tends to be even larger. Although it is possible to polish the wafer even thinner, the wafer diameter increases, and the thinner the wafer, the more difficult it becomes to handle, and the IC chip may be broken at the module fabrication stage.
Although the necessity of the light shielding of the IC chip has been described above, the conventional product uses the wiring pattern of the mounting board as shown in FIG. 1 to shield the LSI surface of the IC chip from the light. Even if there is no wiring pattern that shields the LSI surface of the IC chip, light is difficult to enter because there is resin between the LSI surface of the IC chip and the substrate. It is as thin as 50 μm, and light shielding is not perfect.
[0008]
In a package molded with a resin called SOP (Small Outer Package), which is one of the small-sized mountings of an IC, the resin is as thick as 150 μm or more and light is sufficiently shielded. However, in flip-chip mounting, the distance between the LSI surface of the IC chip and the substrate is only about 50 μm, and the thickness required for light shielding cannot be obtained even if resin is filled, so that light is shielded using the metal of the wiring pattern of the substrate. Will do. According to this method, light is shielded because the metal reflects light.
However, in this method, it is necessary to take into consideration that the light-shielding pattern on the mounting board side should be adjusted to the size of the IC chip, should not intersect with the signal pattern on the mounting board, and the like.
[0009]
On the other hand, as it becomes necessary to reduce the thickness of the IC chip to 100 μm or less, light may enter from the surface of the IC chip opposite to the LSI pattern, that is, from the back surface of the IC chip. is necessary.
In the case of Japanese Unexamined Patent Application Publication No. 1-196842 shown in FIG. 2, since the plate member 2 is provided, it is possible to shield the back surface of the IC chip from light by using the plate member 2 as a metal plate. Light from the outside enters the surface of the IC chip 1 having the circuit through the substrate 7. In addition, in the case of the one shown in FIG. 1, the influence of the IC chip is thin, and the back surface of the IC chip is hardly shielded from light. For this reason, light may enter the LSI pattern and malfunction. The material of the substrate, such as a glass cloth base epoxy resin, easily transmits light, and if the light is not blocked by the wiring pattern of the substrate, light enters the LSI surface of the IC chip. Therefore, a light-shielding pattern is provided in the wiring pattern of the substrate. However, it is necessary to provide the wiring pattern in accordance with the size of the LSI, and it is necessary to consider the wiring pattern of the substrate so that signal lines do not cross.
[0010]
Furthermore, the wafer originally has a thickness of about 600 μm, but after completing the so-called wafer process for fabricating an IC, if a thin package is to be formed, the back surface is polished to 200 μm. Normally, the backside polishing is performed mechanically. With this method, it is possible to achieve a thickness of up to 200 μm, but if the thickness is less than that, it is very difficult. In particular, when the thickness is less than 100 μm, mechanical polishing is impossible. If the polishing is about 200 μm, it flows in a mass production apparatus, and there is no problem in handling.
[0011]
[Means for Solving the Problems]
The present invention is a semiconductor wafer including a wafer having a circuit formed on one surface, and a plate made of a material different from the wafer, which is formed immediately above the circuit formation surface of the wafer, and A semiconductor wafer characterized in that a cut is formed at a position corresponding to a scribe line of the wafer on a surface opposite to the surface facing the wafer.
In the present specification, "a position corresponding to a scribe line of the wafer on a surface of the plate material opposite to the surface facing the wafer" means a surface including a scribe line and vertically cutting the wafer. A position formed by intersecting the opposite surface.
In this specification, a wafer refers to a circuit-formed wafer, a semiconductor wafer refers to a wafer obtained by bonding the wafer and a plate material, and an IC chip refers to a semiconductor wafer obtained by dividing the semiconductor wafer. Means a device on which the IC chip is mounted.
[0012]
The semiconductor wafer according to the present invention can shield the circuit forming surface of the wafer from light by attaching a plate material (preferably, a metal plate whose surface is covered with a resist) with a thickness of about 100 μm to the LSI pattern surface of the wafer. Even when the wafer is polished to a thickness of 100 μm or less, the thickness of the plate material is added to the thickness of the wafer, so that the back surface can be polished in the same manner as polishing the wafer to a thickness of about 200 μm. Can be handled in the same manner as a chip having a thickness of 200 μm. Also, the polished surface opposite to the circuit forming surface of the wafer can be shielded from light because it is vapor-deposited with aluminum, gold, copper or the like after polishing. Although light may enter from the side of the IC chip, the thickness of the IC chip is as thin as about 100 μm and does not affect the LSI pattern surface.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 3 is a cross-sectional view illustrating a semiconductor wafer according to one embodiment of the present invention.
FIG. 4 is a diagram showing a mounting structure of an IC chip manufactured by dividing a semiconductor wafer according to one embodiment of the present invention.
5 and 6 are views showing a semiconductor wafer according to one embodiment of the present invention and steps up to the step of dividing the semiconductor wafer and manufacturing an IC chip. 3, 4, 5 and 6, the IC chip 1, the plate material 2, the bumps 3, the resist 4 which is an insulating material covering the surface of the plate material, and the plate material 2 and the wafer are bonded. 5, an adhesive; 6, a metal-deposited film deposited on the surface opposite to the circuit-formed surface of the polished wafer; 6, a mounting substrate; 8, a resin filling between the plate material and the substrate during mounting; The wiring pattern on the substrate is 9, the wafer is 10, the scribe line is 11, the cut is 12, and the semiconductor wafer is 13.
[0014]
First, a cross-sectional view illustrating the semiconductor wafer of one embodiment of the present invention in FIG. 3 will be described.
In this structure, the plate material 2 is adhered to the circuit forming surface of the wafer 10 on which the scribe lines 11 are formed in advance with the adhesive 5 so that the wafer 10 is hardly broken.
The wafer 10 used in the present invention may be any as long as it can form an electric circuit, and the types of the P-type and N-type channels are not limited. The material is mainly silicon wafer, but is not limited to silicon. Alternatively, a glass substrate or a plastic substrate on which a circuit is formed can be used.
Further, the plate material 2 used in the present invention may be any material as long as it can shield the circuit forming surface of the wafer, but is made of a material different from that of the wafer, preferably 42 alloy, stainless steel, nickel, It is made of a metallic material such as cobalt, tungsten, copper, or palladium, and its surface is covered with an insulating resist 4 so that signals of a circuit are not short-circuited after a bump 3 described later is formed. Further, the plate material 2 is preferably a metallic material having an expansion rate within 5 times the expansion rate of the wafer material. When the wafer is silicon, a 42 alloy or the like having an expansion coefficient substantially equal to that of silicon is used. It is preferred to use The expansion coefficient of the 42 alloy is 4.5 × 10 ⁻⁶ / ° C., and the expansion coefficient of silicon is 2.6 × 10 ⁻⁶ / ° C. Further, the plate material 2 has windows opened in accordance with the positions of the electrode pads (not shown) of the circuit pattern of the wafer 10. The window opening size must be larger than the diameter of the bump 3 described later even after the resist 4 is covered. For example, assume that the diameter of the bump 3 is 80 μm and the thickness of the resist 4 is 20 μm. In this case, the size of the window opening needs to be slightly larger than that of 80 μm × 80 μm so that the resist 4 has a thickness of 20 μm at the window opening portion of the plate material 2, and needs to be 120 μm × 120 μm or more. is there. The electrode pad size on the wafer is about 100 μm × 100 μm, and the diameter of the plate 2 is the same as that of the wafer, and 6 inches or 8 inches is usually used. The thickness of the plate material 2 is 60 μm, and becomes 100 μm after being covered with the resist.
[0015]
Further, in this embodiment of the present invention, the bumps 3 are formed on the electrode pads of the circuit pattern. The bumps 3 are provided for taking out signals of the circuit to the outside, and are made of a conductive paste or a metal pin bonded with a conductive paste. The height of the bumps is about 115 μm to 120 μm because the height of the bumps needs to be higher than 100 μm of the thickness of the plate material 2 covered with the resist 4 and 10 μm of the thickness of the adhesive 5. As a result, the portion protruding from the plate material 2 covered with the resist 4 is about 5 μm to 10 μm. As a method for producing the bump, a bump by plating is also possible.
The wafer 10 and the plate 2 are adhered by an adhesive 5. At this time, since the plate 2 itself shields the circuit forming surface of the wafer 10 from light, it is not necessary to provide a wiring pattern for shielding light as shown in FIG. Absent. In addition, the structure is such that evaporation is performed after polishing so that light is also shielded on the polishing surface opposite to the circuit forming surface.
[0016]
FIG. 4 shows a structure in which an IC chip 1 produced by dividing the semiconductor wafer 13 of the present invention shown in FIG. 3 along a scribe line 11 on the wafer and a cut 12 formed in a plate material is mounted on a substrate 7. ing.
The present invention also provides a semiconductor device using such an IC chip. In this semiconductor device, as shown in FIG. 4, a wiring pattern 9 of a substrate 7 is flip-chip mounted with resin. This connection method will be described. The resin 8 is potted in advance at a position where an IC chip is to be mounted. This resin is in the form of a paste or a film. Thereafter, the IC chip is mounted on the mounting position of the substrate 7, the resin is melted while applying temperature and pressure with a tool from the upper surface of the IC chip, and the resin 8 is cured after contacting the bump and the wiring pattern 9 of the substrate 7. Connect with Further, after this, it is possible to coat and coat a mold or a resin on the upper part of the IC chip.
[0017]
Next, steps of manufacturing a semiconductor wafer and an IC chip according to one embodiment of the present invention are shown in steps (1) to (6) of FIGS.
First, in step (1), sulfuric acid or the like is used to place a metal plate 2 having the same diameter as the wafer and having a thickness of about 60 μm at the same position as the chip size (ie, scribe line 11) of the wafer to be used. Half etching of about 30 μm is performed (cut 12), and a window is opened in accordance with the electrode pad portion of the wafer. This window opening size is set to 120 μm × 120 μm when the electrode pad is usually about 100 μm × 100 μm. The reason for setting this size is to secure a region for forming bumps of about 80 μm × 80 μm after covering with a resist described later.
[0018]
Next, in step (2), an epoxy resin-based resist solution is applied to the plate 2 while controlling the thickness to 20 μm with a spin coater, and the resist 4 is cured in an oven at 160 ° C. for 4 hours. Insulate the surface. Thereafter, the back surface is also covered with the resist 4 by the same method. Thereby, the side surface of the window opening of the plate material 2 is also covered with the resist 4. At this time, care should be taken not to clog the opened portion with the resist 4. If the opened portion is clogged with the resist solution, a hole is formed with a probe or the like. As a result, the window opening size becomes 80 μm × 80 μm.
In step (3), the wafer 10 and the plate 2 are bonded together with an adhesive 5 such as an epoxy resin so that the window opening of the plate 2 and the electrode pad of the wafer are aligned. The thickness of the adhesive is about 10 μm. The curing condition of the adhesive varies depending on the material of the adhesive, but in the case of an epoxy resin, it is about 160 ° C. for about 4 hours.
In step (4), the back surface of the wafer 10 is polished until the wafer thickness becomes 100 μm or less. In the case of the semiconductor wafer in this embodiment, the thickness of the metal plate 2 covered with the resist 4 is 100 μm and the thickness of the adhesive is 10 μm, so that the setting of the polishing apparatus is 210 μm. As a result, the wafer 10 is polished to 100 μm. Thereafter, in order to shield the back surface of the polished wafer from light, evaporation is performed using aluminum, gold, copper, or the like. The thickness of the vapor deposition layer 6 is about 0.6 μm.
[0019]
In step (5), bumps 3 are formed on the electrode pads of the wafer. The bump 3 is formed by bonding a conductive paste such as a silver paste or a metal pin with the conductive paste. The height of the bumps 3 is 115 to 120 μm, and the bumps are about 5 to 10 μm from the plate 2 covered with the resist 4.
Finally, in the step (6), a jig such as a plate having a straight side is applied to the half-etched portion (cut) 12 of the plate material 2, and the semiconductor wafer 13 is bent and cut at that portion, and the semiconductor wafer 13 is individually cut. Of the IC chip 1.
[0020]
【The invention's effect】
(1) The front and back surfaces of the chip can be shielded from light.
Assuming that the LSI surface of the wafer is the surface, the surface is shielded from light because the plate material is bonded to the surface. Further, since the back surface is formed by evaporating the wafer with aluminum, gold, copper, or the like, light can be shielded.
(2) The polishing of the wafer can be simplified and cracks can be prevented.
When the wafer is polished to 100 μm or less, unlike when only the wafer is polished, when the plate material is bonded, the polishing is performed in a state where the plate material and the wafer are overlapped. Therefore, the polishing becomes easy as in the case of polishing the wafer to about 200 μm. Also, cracking of the wafer is less likely to occur.
(3) The plate material can be divided by half etching without using a dicing apparatus.
Normally, a scribe line between LSIs is diced to divide a chip. In the present invention, a half-etched portion (cut) of a plate material is formed in advance in accordance with the scribe line, so that a dicing apparatus is not used. It is possible to perform dicing. In this method, a half-etched portion (cut) is bent to cause a chocolate break.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a mounting structure of an IC chip manufactured from a semiconductor wafer according to a conventional technique.
FIG. 2 is a cross-sectional view showing a mounting structure of an IC chip according to another related art.
FIG. 3 is a cross-sectional view of a semiconductor wafer according to one embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a mounting structure of an IC chip manufactured by dividing a semiconductor wafer according to one embodiment of the present invention.
FIG. 5 is a process chart for manufacturing a semiconductor wafer and an IC chip according to one embodiment of the present invention.
FIG. 6 is a process chart for manufacturing a semiconductor wafer and an IC chip according to one embodiment of the present invention.
[Explanation of symbols]
1: IC chip 2: plate material 3: bump 4: resist (insulator)
5: adhesive 6: deposited film 7: substrate 8: resin 9: wiring pattern 10: wafer 11: scribe line 12: cut 13: semiconductor wafer

Claims (9)

A semiconductor wafer including a wafer having a circuit formed on one surface, and a plate made of a material different from the wafer, which is formed immediately above the circuit formation surface of the wafer, and facing the wafer of the plate. A semiconductor wafer, wherein a cut is formed at a position corresponding to a scribe line of the wafer on a surface opposite to the surface. 2. The semiconductor wafer according to claim 1, wherein the surface of the wafer opposite to the circuit forming surface is polished to a thickness of 50 μm to 200 μm. 2. The semiconductor wafer according to claim 1, wherein the plate member formed immediately above the wafer on which the circuit is formed is made of a material having a light-shielding property. 2. The semiconductor wafer according to claim 1, wherein the plate member formed immediately above the wafer on which the circuit is formed has an expansion rate within 5 times the expansion rate of the wafer on which the circuit is formed. 2. The semiconductor wafer according to claim 1, wherein the plate member formed immediately above the wafer on which the circuit is formed is made of a metallic material. 6. The semiconductor wafer according to claim 5, wherein the plate material formed immediately above the wafer on which the circuit is formed is made of 42 alloy. 2. The semiconductor wafer according to claim 1, wherein a plate member formed immediately above the wafer on which the circuit is formed is covered with an insulating material. 8. The semiconductor wafer according to claim 1, wherein a surface of the wafer opposite to the circuit forming surface is covered with a metal film, thereby shielding the wafer surface from light. 9. A semiconductor device using an IC chip obtained by dividing the semiconductor wafer according to claim 1 along a scribe line of the wafer and a cut of a plate material and individualizing the semiconductor wafer.

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