JP3578009B2 - Tape carrier and manufacturing method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a tape carrier used for a package of a semiconductor chip and a method for manufacturing the same, and more particularly, to a tape carrier capable of realizing high electrical reliability and a method for manufacturing the same.
[0002]
[Prior art]
Recently, portable electronic devices such as notebook personal computers, handy video devices, and mobile phones have been widely sold. In these electronic devices, there is an increasing demand for smaller and more sophisticated packages for mounting semiconductor devices.
[0003]
As this type of package, a tape carrier in which wiring is formed on an insulating tape and a semiconductor chip can be mounted is known. When a semiconductor chip is mounted on such a tape carrier, sealed with a resin, and packaged, a semiconductor device mountable on a printed wiring board or the like is manufactured. Such a tape carrier has an advantage that the package can be significantly thinned.
[0004]
Also, in a tape carrier, a lead frame, and the like, a BGA (Ball Grid Array) type in which lands for external connection such as mounting on a printed wiring board are arranged in a lattice shape is known. The BGA type has an advantage that the land spacing can be enlarged by the grid-like land arrangement, and the mounting can be facilitated.
[0005]
Here, a BGA type tape carrier will be described with reference to FIGS. As shown in FIG. 10A, an adhesive 2 is applied to one side of a 25 μm-thick polyimide tape 1, and as shown in FIG. 10B, a GND wiring comprising a plurality of wirings is provided on the adhesive 2. The first copper foil 3 having a thickness of 35 μm to be a layer is attached.
[0006]
Also, as shown in FIG. 10C, the adhesive 4 is applied to the other side of the polyimide tape 1, and thereafter, as shown in FIG. 10D, an opening for mounting the semiconductor chip is formed. 5 (hereinafter referred to as a device hole) is formed by punching using a mold.
[0007]
Subsequently, as shown in FIG. 10E, a 18 μm-thick second copper foil 6 serving as a wiring layer is attached on the adhesive 4 and, as shown in FIG. The copper foil 3 is etched to form a GND (first) wiring layer 3b including a plurality of wirings having a plurality of lands 3a.
[0008]
Further, as shown in FIG. 11 (g), a hole 7 having a depth reaching the second copper foil 6 is formed in the polyimide tape 1 by the excimer laser, and a cleaning process is performed to prevent oxidation after laser processing. Is done.
[0009]
After the washing and drying, the holes 7 are filled by plating of a conductive metal (or printing of a conductive paste), and the second copper foil 6 and the GND wiring layer are filled as shown in FIG. 3b are electrically connected to each other to form a via hole 8.
[0010]
Further, the second copper foil 6 is etched as shown in FIG. 11I to form a second wiring layer 6b having a plurality of semiconductor connection electrodes 6a near the device hole 5. Here, each of the semiconductor connection electrodes 6a is formed in a comb shape continuously from the second wiring layer 6b, and the tip is located inside the periphery of the device hole 5.
[0011]
Further, as shown in FIG. 11 (j), the surfaces of the semiconductor connection electrode 6a and the land 3a are covered with a plating layer 9 or the like by plating with gold or the like.
[0012]
In order to protect these wiring layers 3b and 6b from solder and the like used in a later step, as shown in FIG. 11 (k), a surface protection layer 10 made of a solder resist (SR) is used for each semiconductor connection. It is selectively formed on the surface of each wiring layer 3b, 6b other than the electrode 6a and each land 3a. The surface protection layer 10 may be formed before the plating layer 9.
[0013]
Thereafter, a semiconductor chip is connected to the semiconductor connection electrode 6a (not shown), resin-sealed (not shown), and solder balls 11 are mounted on the lands 3a, respectively, as shown in FIG. Is done. In the insulating tape that has been processed as described above, the tape carrier portion that is actually a product is classified by punching using a die or cutting using a laser or the like. Thus, the tape carrier is completed.
[0014]
Subsequently, in the above manufacturing steps, the plating step of FIG. When plating each land 3a and each semiconductor connection electrode 6a, it is preferable to use electrolytic plating which is inexpensive and has a high plating rate as compared with electroless plating.
[0015]
Specifically, in the electroplating, since it is necessary to conduct each land 3a and each semiconductor connection electrode 6a, as shown in FIG. 12, the inside of each row of sprocket holes 12 and the region to be a final product are surrounded. Each plating lead 14 is formed so as to conduct between the main plating lead 13 formed in a ladder shape and each land (external connection electrode) 3a in the final product.
[0016]
[Problems to be solved by the invention]
However, in the above-described tape carrier and its manufacturing method, when obtaining the area of the final product, when the unnecessary area where each plating lead 14 is located is cut along a broken line portion 14x shown in FIG. Is exposed. Here, the exposure of the cross section of each plating lead 14 causes a possibility that the adjacent plating leads 14 may be short-circuited by contact with the housing or the like, or a foreign substance may adhere to the cross section and short-circuit each other. There is a problem that electrical reliability is reduced.
[0017]
This problem is particularly noticeable in a BGA type tape carrier and a tape carrier whose lead cross section is exposed by punching with a die.
For example, in the case of a BGA-type tape carrier, the plating leads extend from each of the grid-like lands, so that the intervals at the carrier end portions are close to each other, so that a short circuit is likely to occur.
[0018]
In addition, punching using a die is preferred for mass production because of short processing time and easy external processing. However, there is a tendency that the processed cross section is expanded in a burr-like manner, and this tendency is strongly exhibited when the plating lead is easily stretched. Here, the material of the plating lead is preferably copper, which is inexpensive and has excellent conductivity, but copper is easily stretched and its cross section is easily expanded.
[0019]
On the other hand, from the viewpoint of solving the above problems, a lead end processing method for preventing exposure of the cross section of each plating lead 14 has been considered. For example, as shown in FIG. 13A, after the formation of the GND wiring layer 3b, the lands 3a, and the plating leads 14, as shown in FIG. Form a plating resist.
[0020]
Thereafter, as shown in FIG. 13C, a plating layer 9a of Ni, Au or the like is formed on the GND wiring layer 3b, the land 3a, and the plating lead 14 exposed from the plating resist by electrolytic plating. Thereafter, as shown in FIG. 14D, the plating resist is removed.
[0021]
Subsequently, etching is performed again using the plating layer 9a as an etching resist, as shown in FIG. 14E, to remove the plating lead 14 in a portion without the plating layer 9a.
[0022]
Further, as shown in FIG. 14 (f), a solder resist 10 is formed on the entire surface except for the land 3a and the semiconductor connection electrode 6a, and as shown in FIG. And punching with a die.
[0023]
As a result, an inner necessary area including each land 3a and an unnecessary area outside each land 3a are separated from each other at the area where each plating lead 14 is located. However, as shown in FIG. 16, the cross section of the plating lead 14 is not exposed.
[0024]
However, this type of lead end processing method increases the number of steps. Further, when the plating resist 15 is formed, the steps of applying, exposing, and developing the plating resist 15 are performed. Therefore, electrolytic plating may be impossible due to surface contamination of the land 3a, and the reliability is reduced. I will.
[0025]
Further, the plating resist 15 needs to have resistance to a plating solution such as a gold plating solution, and a strong resist such as a rubber-based resist is used. For this reason, the plating resist 15 is difficult to peel off, but cannot be used because a strong peeling liquid may adversely affect a finished product. That is, the peeling step of the plating resist 15 is difficult.
[0026]
Further, in the above-described lead end processing method, there is a possibility that the plating layer 9a formed in the previous step is contaminated with an etchant during re-etching.
[0027]
The present invention has been made in view of the above circumstances, and has as its object to provide a tape carrier that can prevent a short circuit between plating leads at an end portion and can realize high electrical reliability.
[0028]
Another object of the present invention is to provide a method of manufacturing a tape carrier that can manufacture a tape carrier that does not expose the cross section of each plating lead in a simple and highly reliable process.
[0029]
[Means for Solving the Problems]
The invention corresponding to claim 1 is a wiring layer comprising a plurality of wirings selectively formed on at least one surface of the insulating tape, and a plurality of semiconductors formed at one end of each wiring in the wiring layer. A chip connecting electrode, a plurality of lands formed on the other end of each wiring electrically connected to each of the semiconductor chip connecting electrodes, and having a plating layer made of a material different from the wiring layer on the surface; In a tape carrier including a plurality of plating leads formed continuously extending from each land to an end of the insulating tape, and a solder resist for protecting the wiring, the tape carrier at an end of the insulating tape is provided. It is a tape carrier provided with an insulating resin layer covering an end of a plating lead.
[0030]
The invention according to claim 2 is the tape carrier according to claim 1, wherein the lands are arranged in a lattice pattern.
[0031]
Further, according to a third aspect of the present invention, in the tape carrier according to the first or second aspect, an end of the insulating tape and an end of each of the plating leads are formed by punching using a mold. It is a tape carrier.
[0032]
According to a fourth aspect of the present invention, there is provided a conductive foil forming step of forming a conductive foil on at least one surface of an insulating tape, and patterning the conductive foil formed in the conductive foil forming step to form a plurality of wirings. A plurality of semiconductor chip connection electrodes located at one end of each wiring in the wiring layer, a plurality of lands located at the other end of each wiring, and a plurality of continuations extending from each of the lands A patterning step of forming a plating lead, a solder resist forming step of forming a solder resist so as to cover the wirings and the insulating tape, and electrolytic plating using the plating leads, for connecting the semiconductor chips. An electrolytic plating step of forming a plating layer on the surfaces of the electrodes and the lands; and a lead for cutting a region of the insulating tape where the plating leads are located. A cutting step, a manufacturing method of the tape carrier and a lead section covering step of covering with the insulating resin cut surface of each plating lead obtained by the lead cutting step.
[0033]
Further, an invention corresponding to claim 5 is the method for manufacturing a tape carrier according to claim 4, wherein, as the patterning step, the lands are formed so as to be arranged in a grid pattern. .
[0034]
According to a sixth aspect of the present invention, in the method for manufacturing a tape carrier according to the fourth or fifth aspect, the removing step is a method for manufacturing a tape carrier performed by punching using a die. .
[0035]
(Action)
Therefore, in the invention corresponding to claims 1 and 4, by taking the above means, the insulating resin layer covers the end of each plating lead at the end of the insulating tape. A short circuit between the plating leads can be prevented, and high electrical reliability can be realized.
[0036]
According to the second aspect of the present invention, since the lands are arranged in a grid pattern, in addition to the action corresponding to the first aspect, a high-density and easy-to-mount tape carrier can be realized with high reliability. .
[0037]
Further, according to the invention corresponding to claim 3, since the end of the insulating tape and the end of each plating lead are formed by punching using a mold, the effect corresponding to claim 1 or claim 2 is achieved. In addition, a tape carrier suitable for mass production can be realized.
[0038]
Further, the invention corresponding to claim 4 solves the problem of the increase in the number of steps and the surface contamination by the conventional plating resist by the lead section covering step of covering the cut surface of each plating lead obtained in the lead cutting step with an insulating resin. Therefore, a tape carrier that does not expose the cross section of each plating lead can be manufactured by a simple and highly reliable process.
[0039]
Further, in the invention according to claim 5, since the patterning step is performed so that the lands are arranged in a lattice pattern, in addition to the action according to claim 4, a high-density and easy-to-mount tape carrier is manufactured. be able to.
[0040]
In the invention corresponding to claim 6, since the unloading step is performed by punching using a die, high production efficiency can be realized in addition to the action corresponding to claim 4 or claim 5. .
[0041]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0042]
(First Embodiment)
FIG. 1 is a plan view schematically showing a schematic configuration of a tape carrier according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view schematically showing the configuration of the tape carrier. 12 are denoted by the same reference numerals, detailed description thereof will be omitted, and different portions will be mainly described here.
[0043]
The present embodiment can prevent a short circuit between the plating leads 14 at the end and achieve high electrical reliability. Specifically, as shown in FIG. An insulating resin layer 21 covering the end of each plating lead 14 at the end is provided.
[0044]
Here, for the insulating resin layer 21, any insulating resin that is the same as or different from the solder resist that protects the front and back surfaces can be used. As the insulating resin layer 21, an epoxy resin, a polyimide resin, a polyurethane resin, a polyethylene resin, or the like can be used. Commercial products of the insulating resin layer 21 include PSR-4000 (manufactured by Taiyo Ink Manufacturing Co., Ltd.) and UFR-1000 (manufactured by Ajinomoto Co., Inc.).
[0045]
As a method for forming the insulating resin layer 21, various coating methods such as a coater, a dispenser, and screen printing can be used as appropriate.
[0046]
Next, a method for producing the above-described tape carrier and its operation will be described.
[0047]
(Production method)
First, as described above, a first copper foil 3 having a thickness of 35 μm is adhered to one surface of a polyimide (insulating) tape 1 having a thickness of 25 μm via an adhesive 2. As shown in FIG. 3A, a device hole 5 for mounting a semiconductor chip is formed by punching a substantially center of the copper foil 3 with a mold.
[0048]
Subsequently, a second copper foil 6 is adhered on another side of the polyimide tape via an adhesive layer, and thereafter, the first copper foil 3 is patterned to form a GND (No. 1) The wiring layer 3b and each land 3a are formed.
[0049]
In the same manner as described above, as shown in FIG. 3B, the polyimide tape 1 is penetrated from each land 3a side so as to electrically connect the GND wiring layer 3b or each land 3a to the second copper foil 6. Each via hole (interlayer connection member) 8 is selectively formed.
[0050]
Next, the second copper foil 6 is patterned so as not to expose each via hole 8, and a second wiring layer 6b including a plurality of wirings and a semiconductor connection electrode 6a are formed. Thereafter, FIG. As shown in FIG. 6, a plating layer 9 is formed on the surface of each land 3a by electrolytic plating.
[0051]
Here, in the step of forming the plating layer 9, first, a plating electrode (not shown) is connected to the main plating lead 13. Next, a nickel plating layer having a thickness of 5 μm is formed on the surfaces of the GND wiring layer 3b, the second wiring layer 6b, the semiconductor connection electrode 6a, and each land 3a by electrolytic plating. A gold plating layer having a thickness of 0.3 μm is formed on the layer.
[0052]
After the formation of the nickel and gold plating layers 9, a solder resist made of epoxy resin is screen-printed on the front and back surfaces as the surface protection layer 10, and is exposed and developed on the lands 3a and the semiconductor connection electrodes 6a. Parts are exposed.
[0053]
Thereafter, by punching using a mold, the region where each plating lead 14 is located (broken line portion 14x in FIG. 1) is cut as described above. Thereafter, the insulating resin layer 21 is applied and formed on the cross section of the end of the polyimide tape 1, so that the cross section is covered with the insulating resin layer 21.
[0054]
Thereby, a shippable tape carrier having the structure shown in FIG. 2 is completed.
In this tape carrier, as shown in FIG. 4, the semiconductor chip 22 is electrically connected to the semiconductor connection electrode 6a so as to be located inside the peripheral edge of the device hole 5, and thereafter, the lands 3a are exposed. The whole is sealed with the insulating resin 23, and the solder balls 11 are formed on each of the lands 3a.
[0055]
When the solder balls 11 are formed on the chip carrier, a semiconductor device that can be connected to an external element such as a motherboard via the solder balls 11 is completed.
[0056]
As described above, according to the present embodiment, since the insulating resin layer 21 covers the end of each plating lead 14 at the end of the polyimide tape 1, unlike the conventional case, each plating lead is removed from the housing or foreign matter. 14 are protected. Accordingly, short-circuiting between the plating leads 14 at the end can be prevented, and high electrical reliability can be realized.
[0057]
Further, since this insulating resin layer 21 is formed by a lead cross-section covering step of covering the cut surface of each plating lead 14 with an insulating resin, it is possible to solve the problem of increase in the number of steps and surface contamination by the conventional plating resist, In addition, a tape carrier that does not expose the cross section of each plating lead 14 can be manufactured in a simple and highly reliable process.
[0058]
Furthermore, since the lands 3a are arranged in a lattice, a tape carrier that is easy to mount with high density can be realized and manufactured with high reliability.
[0059]
Further, since the end of the polyimide tape 1 and the end of each plating lead 14 are formed by punching using a die, it is possible to realize and manufacture a tape carrier having high production efficiency and suitable for mass production. it can. Also, even if a burr-like spread occurs in the cross section of each plating lead 14 due to the punching process using a die, the cross section of each plating lead 14 is protected by the insulating resin layer, so that the electrical reliability is high. Sex can be obtained.
[0060]
(Second embodiment)
Next, a tape carrier according to a second embodiment of the present invention will be described.
FIG. 5 is a plan view schematically showing a schematic configuration of the tape carrier, and FIG. 6 is a cross-sectional view schematically showing the configuration of the tape carrier. Unlike the first embodiment, the tape carrier has one layer. 1 shows a tape carrier having a single-layer structure having the above-mentioned wiring layer.
[0061]
This tape carrier has an insulating polyimide tape 41 in which a device hole 40 for mounting a semiconductor chip is formed substantially in the center, and a wiring layer composed of a plurality of wirings selectively formed on one surface of the polyimide tape 41. 42, a plurality of lands 43 formed continuously from the wiring layer 42 and having a plating layer 43a on the surface, and electrically connected to external elements; A semiconductor connection electrode 44 having a tip 44a located inside the periphery of the device hole and an insulating resin layer 45 covering the end of each plating lead 46 at the end of the polyimide tape 41 are provided.
[0062]
Each plating lead 46 is the same as each plating lead 14 although the tape carrier has a single-layer structure, and thus the reference numerals of the respective plating leads 14 are re-assigned. Similarly, the main plating lead 47 is similar to the main plating lead 13.
[0063]
Next, a method for producing the above-described tape carrier and its operation will be described.
[0064]
(Production method)
As described above, a device hole 40 for mounting a semiconductor chip is formed by punching out the approximate center of a 25 μm-thick polyimide tape 41 with a mold, and has this device hole 40 as shown in FIG. A conductive foil 42a is adhered to one surface of the polyimide tape 41 via an adhesive 48.
[0065]
Subsequently, as shown in FIGS. 5 and 7B, the attached conductive foil 42a is patterned to form a wiring layer 42 including a plurality of wirings, each land 43, a semiconductor connection electrode 44, and a plating lead 46. And the main plating lead 47 is formed.
[0066]
In the same manner as described above, a 5 μm thick nickel plating layer and a 0.3 μm thick gold plating Plating layers 43a are sequentially formed.
[0067]
Thereafter, as in the first embodiment, a solder resist made of an epoxy resin is applied as a surface protection layer 49 on the front and back surfaces. Subsequently, the region where each plating lead is located is cut by a punching process using a mold as described above.
[0068]
Thereafter, the insulating resin layer 45 is applied and formed on the cross section of the end of the polyimide tape 41, so that the cross section is covered with the insulating resin layer 45.
[0069]
Thus, a shippable tape carrier having the structure shown in FIG. 8 is completed. Further, as described above, when the distal end connection member 45 is removed by the selective etching, the tape carrier is finally completed. It goes without saying that this final product may be shipped.
[0070]
As shown in FIG. 9, the semiconductor chip 51 is electrically connected to the semiconductor connection electrode 44, and the entire tape carrier is sealed with an insulating resin 52 while exposing the lands 43, as shown in FIG. When the solder balls 53 are formed on the respective lands 43, the semiconductor device can be connected to an external element such as a motherboard via the respective solder balls 53.
[0071]
In this embodiment, since the tape carrier has a one-layer structure, a circuit configuration and a manufacturing process can be simplified by eliminating a via hole which is troublesome in manufacturing, and thus, reliability can be improved.
[0072]
As described above, according to the second embodiment, it is possible to realize a single-layer tape carrier having the effects of the first embodiment.
[0073]
(Other embodiments)
In the first embodiment, a two-layer chip carrier having two wiring layers 3b and 6b has been described as an example. However, the present invention is not limited to this, and three or more layers can be manufactured by the same manufacturing process. The same effects can be obtained by implementing the present invention in the same manner even with a chip carrier having a multilayer structure having the above wiring layer.
[0074]
In the first or second embodiment, the case where the surface protection layer 10 is formed after the formation of the plating layers 9 and 43a and the punching process is performed thereafter is described. Even if the plating process is changed to a manufacturing process in which the plating layers 9 and 43a are formed after the formation of 10, and then punching (or cutting) is performed, the same effect can be obtained by implementing the present invention in the same manner.
[0075]
The present invention is not limited to this modification, but may be modified to a manufacturing process of performing punching (or cutting) after forming the plating layers 9 and 43a, and then forming the surface protection layer 10. In this case, in addition to obtaining the same effect by carrying out the present invention in the same manner, the insulating resin layer 21 can be formed on the cross section simultaneously with the formation of the surface protective layer 10, so that the process can be simplified.
[0076]
In the first or second embodiment, the case where the plating layers 9 and 43a on the surface are made of gold has been described. However, the present invention is not limited to this, and good affinity for the solder balls 11 and 53 for external connection is provided. Even if the material having the property is used as the plating layers 9 and 43a, the same effect can be obtained by implementing the present invention in the same manner. Specifically, for example, a material such as tin, nickel, silver, palladium, or solder is preferably used as the plating layer from the viewpoint of affinity and conductivity.
[0077]
Further, in the first or second embodiment, the case where the punching process using the mold is performed has been described. However, the present invention is not limited to this, and may be modified to a manufacturing method in which the cutting process using a laser or the like is performed. Although the processing speed is lower than the punching process using a die, the same effects can be obtained by implementing the present invention in the same manner.
[0078]
Further, in the first or second embodiment, the case of the BGA type tape carrier has been described. However, the present invention is not limited to this. With the configuration, the present invention can be implemented in the same manner and the same effect can be obtained.
[0079]
In addition, the present invention can be variously modified and implemented without departing from the gist thereof.
[0080]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a tape carrier that can prevent a short circuit between the plating leads at the ends and realize high electrical reliability.
[0081]
Further, it is possible to provide a tape carrier manufacturing method capable of manufacturing a tape carrier that does not expose the cross section of each plating lead in a simple and highly reliable process.
[Brief description of the drawings]
FIG. 1 is a plan view showing a schematic configuration of a tape carrier according to a first embodiment of the present invention.
FIG. 2 is a sectional view schematically showing the configuration of the tape carrier according to the embodiment.
FIG. 3 is a process cross-sectional view schematically showing the method of manufacturing the tape carrier according to the embodiment.
FIG. 4 is a cross-sectional view schematically showing a configuration of the semiconductor device in the embodiment.
FIG. 5 is a plan view showing a schematic configuration of a tape carrier according to a second embodiment of the present invention.
FIG. 6 is a sectional view schematically showing the configuration of the tape carrier in the embodiment.
FIG. 7 is a process sectional view schematically showing the method of manufacturing the tape carrier according to the embodiment.
FIG. 8 is a sectional view schematically showing the configuration of the tape carrier according to the embodiment.
FIG. 9 is a cross-sectional view schematically showing a configuration of the semiconductor device in the embodiment.
FIG. 10 is a process sectional view schematically showing a conventional tape carrier manufacturing method.
FIG. 11 is a process cross-sectional view schematically showing a conventional tape carrier manufacturing method.
FIG. 12 is a plan view showing a schematic configuration of a conventional tape carrier.
FIG. 13 is a partial plan view schematically showing a conventional tape carrier manufacturing method.
FIG. 14 is a partial plan view schematically showing a conventional tape carrier manufacturing method.
FIG. 15 is a partial plan view schematically showing a conventional tape carrier manufacturing method.
FIG. 16 is a partial sectional view showing a schematic configuration of an end portion of a tape carrier according to a conventional manufacturing method.
[Explanation of symbols]
1,41 ... polyimide tape
2,4,48 ... adhesive
3. First copper foil
3a, 43 ... Land
3b: GND wiring layer
5,40… Device hole
6 ... second copper foil
6a, 44 ... Semiconductor connection electrode
6b: second wiring layer
7 ... Hole
8 ... Via hole
9 ... Plating layer
10. Surface protective layer
11,53… Solder ball
12 ... Sprocket hole
13, 47… Main plating lead
14, 46 ... Plating lead
15 ... Plating resist
16 ... broken line part (punching area)
21, 45 ... insulating resin layer
22, 51 ... semiconductor chip
23, 52 ... insulating resin

Claims (6)

Insulating tape,
A wiring layer composed of a plurality of wirings selectively formed on at least one surface of the insulating tape,
A plurality of semiconductor chip connection electrodes formed at one end of each wiring in the wiring layer,
A plurality of lands formed on the other end of each wiring electrically connected to each of the semiconductor chip connection electrodes, and having a plating layer on the surface made of a material different from the wiring layer,
A plurality of plating leads formed continuously extending from each land to the end of the insulating tape,
In a tape carrier comprising a solder resist for protecting the wiring,
A tape carrier comprising an insulating resin layer covering an end of each of the plating leads at an end of the insulating tape. The tape carrier according to claim 1,
The respective lands are arranged in a lattice pattern. In the tape carrier according to claim 1 or 2,
An end portion of the insulating tape and an end portion of each of the plating leads are formed by punching using a die. A conductive foil forming step of forming a conductive foil on at least one surface of the insulating tape,
The conductive foil formed in the conductive foil forming step is patterned to form a wiring layer including a plurality of wirings, a plurality of semiconductor chip connection electrodes located at one end of each wiring in the wiring layer, and the other end of each wiring. A plurality of lands, and a patterning step of forming a plurality of plating leads extending continuously from each of the lands,
A solder resist forming step of forming a solder resist so as to cover the wirings and the insulating tape,
An electrolytic plating step of forming a plating layer on the surface of each of the semiconductor chip connection electrodes and each of the lands by electrolytic plating using the plating leads,
A lead cutting step of cutting a region where the plating leads are located in the insulating tape;
A step of covering a cut surface of each plating lead obtained in the lead cutting step with an insulating resin. The method for manufacturing a tape carrier according to claim 4,
The method of manufacturing a tape carrier, wherein the patterning step is performed so that the lands are arranged in a grid pattern. In the method for manufacturing a tape carrier according to claim 4 or claim 5,
The method of manufacturing a tape carrier, wherein the lead cutting step is performed by punching using a die.

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