JP3579820B2 - D-type flip-flop - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a D-type flip-flop in which a master latch is constituted by a differential inverter and a slave latch is constituted by an RS latch, and more particularly to a D-type flip-flop used in a semiconductor integrated circuit.
[0002]
[Prior art]
The D-type flip-flop includes a master latch of a differential inverter and a slave latch of an RS latch, and has a function of holding input data and outputting the held data in synchronization with a clock input signal. The function of the D-type flip-flop is that data input to the data input terminal D during the evaluation period of the clock input signal directly appears at the data output terminal Q. This D-type flip-flop is a basic element for a synchronous semiconductor integrated circuit.
[0003]
Hereinafter, a conventional flip-flop circuit will be described with reference to the drawings.
[0004]
FIG. 5 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration in which the master latch is a differential inverter and the slave latch is an RS latch. In FIG. 5, reference numeral 1 denotes a differential inverter forming a master latch, 2 denotes an RS latch forming a slave latch, TP1, TP2, TP3 and TP4 denote Pch-type MOS transistors, and TN1, TN2, TN3. TN6, TN7 and TN9 are N-channel MOS transistors, NAND1 and NAND2 are two-input NAND circuits, INV1 is an inverter circuit, CLK is a clock input terminal, D is a data input terminal, Q is a data output terminal, QN is an inverted data output terminal, S and R are internal nodes of the D-type flip-flop, which are a set input terminal and a reset input terminal of the RS latch 2, and n1 and n2 are a drain terminal or a source terminal of the transistor TN9.
[0005]
The operation of the D-type flip-flop having the differential-RS latch configuration shown in FIG. 5 will be described. Since the gate of the transistor TN9 is connected to the DC power supply and is fixed at the VDD potential which is the higher potential power supply potential, it is always in a conductive state.
[0006]
First, the operation during the charging period will be described. When the clock input signal input to the clock input terminal CLK is at the VSS potential which is the lower potential power supply potential, the two Pch transistors TP1 and TP2 for charging are turned on, and the Nch transistor TN1 is turned off. Therefore, the set input terminal S of the RS latch 2 is charged to the VDD potential via the Pch transistor TP2, and the reset input terminal R is charged to the VDD potential via the Pch transistor TP1. Since the Nch transistors TN6 and TN7 also become conductive, the connection points n1 and n2 are charged to a potential obtained by subtracting the threshold voltage of the Nch transistor from the VDD potential. Even when the Nch transistors TN6 and TN7 are conductive, the source is connected to the ground and the Nch transistor TN1 fixed to the VSS potential is nonconductive, so that no discharge occurs from the set input terminal S and the reset input terminal R. At this time, since both the set input terminal S and the reset input terminal R of the RS latch 2 have the VDD potential, the RS latch 2 enters the hold state, and keeps holding the data currently held. Regardless of the state of the data input terminal D, in other words, regardless of which of the Nch transistors TN2 and TN3 is conducting and which is not conducting, the Nch transistor TN1 keeps the non-conducting state. The state of the VDD potential of the terminal S and the reset input terminal R does not change. Driving Pch transistors TP3 and TP4 remain non-conductive. Such a state is called a charging period.
[0007]
Next, the operation during the evaluation period will be described. The period during which the clock input signal input to the clock input terminal CLK changes from the VSS potential to the VDD potential is the evaluation period. In the evaluation period, the charging Pch transistors TP1 and TP2 are turned off, and the Nch transistor TN1 is turned on. In this state, a difference in the output state of the D-type flip-flop due to a difference in data input to the data input terminal D will be described below.
[0008]
When the data input terminal D is at the VSS potential, the Nch transistor TN2 is off, and the output of the inverter circuit INV1 is at the VDD potential, so that the Nch transistor TN3 is on. The connection point n2 is connected to the ground of the VSS potential via the transistor TN3 and the transistor TN1, and as a result, the connection potential of the connection point n2 becomes faster than that of the connection point n1. Discharge occurs through TN7, and the set input terminal S becomes the VSS potential. Then, the Nch transistor TN6 whose gate has fallen to the VSS potential is inverted to a non-conductive state, and the driving Pch transistor TP3 whose gate has fallen to the VSS potential is inverted to a conductive state. The reset input terminal R is charged via the Pch transistor TP3 to have the VDD potential. Since the set input terminal S is at the VSS potential, the VDD potential is output to the inverted data output terminal QN. Since the reset input terminal R is at the VDD potential, the VSS potential is output to the data output terminal Q.
[0009]
Conversely, when the data input terminal D is at the VDD potential, the Nch transistor TN2 is conductive and the output of the inverter circuit INV1 is at the VSS potential, so that the Nch transistor TN3 is nonconductive. The connection point n1 is connected to the ground of the VSS potential through the transistor TN2 and the transistor TN1. As a result, the connection potential of the connection point n1 becomes faster than that of the connection point n2. Discharge occurs through TN6, and the reset input terminal R becomes the VSS potential. Then, the Nch transistor TN7 whose gate has fallen to the VSS potential is inverted to a non-conductive state, and the driving Pch transistor TP4 whose gate has fallen to the VSS potential is inverted to a conductive state. The set input terminal S is charged via the Pch transistor TP4 to have the VDD potential. Since the set input terminal S is at the VDD potential, the VSS potential is output to the inverted data output terminal QN. Since the reset input terminal R is at the VSS potential, the VDD potential is output to the data output terminal Q.
[0010]
In the conventional D-type flip-flop having the differential-RS latch configuration shown in FIG. 5, during the evaluation period, which of the set input terminal S and the reset input terminal R is used, as is clear from the above description of the operation. One is at the VSS potential and the other is at the VDD potential.
[0011]
Here, assuming that the charging period starts from a state where the set input terminal S is at the VSS potential and the reset input terminal R is at the VDD potential, the charging Pch transistor TP2 is turned on, and the charging Pch transistor TP2 is turned on. The set input terminal S is charged from the VSS potential to the VDD potential. During the charging period, the other charging Pch transistor TP1 also becomes conductive, but this transistor TP1 is for charging the reset input terminal R and is not connected to the set input terminal S. It does not function for charging the set input terminal S.
[0012]
Conversely, assuming that the charging period starts from a state where the set input terminal S is at the VDD potential and the reset input terminal R is at the VSS potential, the charging Pch transistor TP1 becomes conductive, The reset input terminal R is charged from the VSS potential to the VDD potential via the transistor TP1. During the charging period, the other charging Pch transistor TP2 also becomes conductive. However, this transistor TP2 is for charging the set input terminal S and is not connected to the reset input terminal R. It does not function for charging the reset input terminal R.
[0013]
When the charging period starts, the Pch transistors TP3 and TP4 are turned off.
[0014]
In a D-type flip-flop, a charging period generally requires a longer time than an evaluation period.
[0015]
Now, consider increasing the clock frequency of the D-type flip-flop. When the clock frequency is increased, one cycle is shortened. Therefore, both the evaluation period and the charging period are shortened. If the charging period is short, the charging may be insufficient, and the D-type flip-flop will not operate.
[0016]
In order to operate the D-type flip-flop at a high clock frequency, it is conceivable to increase the gate width of the charging Pch transistors TP1 and TP2. However, when the gate width is increased, since the gates of the transistors TP1 and TP2 are connected to the clock input terminal CLK, the input capacitance of the clock input terminal increases, and if so, the waveform becomes blunted. This is not preferable for synchronous control.
[0017]
In addition, when a function required for designing a semiconductor integrated circuit is added, the amount of charge required for charging the set input terminal S and the reset input terminal R increases, which also causes the D-type flip-flop to operate at a high clock frequency. It will be a hindrance to making it happen. This will be described with reference to FIG.
[0018]
FIG. 4 is a circuit configuration diagram of a scan test-compatible D-type flip-flop with a reset function in the case of the conventional technique. In FIG. 4, TP6, TP10, TP11 and TP20 are P-channel MOS transistors, TN4, TN5, TN10 and TN20 are N-channel MOS transistors, INV2, INV5, INV10, INV20 and INV21 are inverter circuits, DT is a test data input terminal, CKT is a test clock input terminal, and RSTN is a reset signal input terminal. Other symbols are the same as those in FIG.
[0019]
When a function required for designing a semiconductor integrated circuit is added as in the circuit of FIG. 4, the number of transistors connected to the set input terminal S and the reset input terminal R increases, so that the amount of charge that must be charged during the charging period Also increase. Therefore, when operating at a high clock frequency, insufficient charging becomes more serious.
[0020]
On the other hand, if the gate widths of the Pch transistors TP1, TP2, TP10, TP1, and TP6 are increased for high-speed charging, the input capacitance of the clock input terminal increases, which is not preferable for synchronization control.
[0021]
(Prior art)
Therefore, the present inventor has considered a scan test-compatible D-type flip-flop with a reset function having an improvement as shown in FIG. The D-type flip-flop shown in FIG. 3 will be referred to as prior art.
[0022]
Hereinafter, the prior art will be described in detail. The components will be described. In FIG. 3, reference numeral 1 denotes a differential inverter forming a master latch, and reference numeral 2 denotes an RS latch forming a slave latch. TP1, TP2, TP3, TP4, TP6, TP10, TP11, TP20, TP30, and TP31 are Pch-type MOS transistors, and TN1, TN2, TN3, TN4, TN5, TN6, TN7, TN9, TN10, and TN20 are Nch-type MOS transistors. Transistors, NAND1 and NAND2 are 2-input NAND circuits, INV1, INV2, INV5, INV10, INV20 and INV21 are inverter circuits, S and R are internal nodes of flip-flops, and are set input and reset input terminals of RS latch 2; n2 is a drain or source terminal of the transistor TN9, CLK is a clock input terminal, CKT is a test clock input terminal, D is a data input terminal, DT is a test data input terminal, and RSTN is a reset signal. Power terminal, Q is a data output terminal, the QN an inverted data output terminal, each of these elements are connected as shown.
[0023]
The circuit configuration of FIG. 3 differs from that of FIG. 4 in the following point. Two Pch transistors TP30 and TP31 are cascaded between a set input terminal S and a reset input terminal R of the RS latch 2. The gate of the Pch transistor TP30 is connected to the test clock input terminal CKT, and the gate of the Pch transistor TP31 is connected to the clock input terminal CLK.
[0024]
In the scan test-compatible D-type flip-flop with the reset function according to the prior art, the clock input terminal CLK is fixed to the VSS potential which is the lower potential power supply potential during the test operation. The test clock input terminal CKT is fixed at the VSS potential when the test operation is not performed. The reset signal input terminal RSTN is set to the VSS potential when the reset function is executed, and is set to the VDD potential which is the higher potential power supply potential in other cases.
[0025]
Next, the operation of the scan test-compatible D-type flip-flop with the reset function according to the related art having the above configuration will be described. Since the gate of the transistor TN9 is connected to the DC power supply and is fixed at the VDD potential which is the higher potential power supply potential, it is always in a conductive state.
[0026]
In a normal mode other than the test operation, the test clock input terminal CKT is at the VSS potential of the lower potential power supply potential, and the Pch transistors TP10, TP11 and TP30 are in a conductive state. In a state where the reset function is not executed, the reset signal input terminal RSTN is at the VDD potential of the high potential side power supply potential, the Pch transistor TP20 is turned off, and the Pch transistor TP6 is turned on via the inverter circuit INV5. , And the Nch transistor TN20 is non-conductive.
[0027]
Assume that the evaluation period has now come. The clock input signal input to the clock input terminal CLK changes from the VSS potential to the VDD potential, and the evaluation period starts. In the evaluation period, the charging Pch transistors TP1 and TP2 are turned off, and the Nch transistor TN1 is turned on. In this state, a difference in the output state of the D-type flip-flop due to a difference in data input to the data input terminal D will be described below.
[0028]
When the data input terminal D is at the VSS potential, the Nch transistor TN2 is off, and the output of the inverter circuit INV1 is at the VDD potential, so that the Nch transistor TN3 is on. The connection point n2 is connected to the ground of the VSS potential via the transistor TN3 and the transistor TN1, and as a result, the connection potential of the connection point n2 becomes faster than that of the connection point n1. Discharge occurs through TN7, and the set input terminal S becomes the VSS potential. Then, the Nch transistor TN6 whose gate has dropped to the VSS potential is inverted to a non-conductive state, the driving Pch transistor TP3 whose gate has dropped to the VSS potential is inverted to a conductive state, and as a result, the driving Pch transistor TP3 , The reset input terminal R is charged to the VDD potential. Since the set input terminal S is at the VSS potential and the reset input terminal R is at the VDD potential, the VDD potential is output to the output terminal of the RS latch 2, the VSS potential is output to the data output terminal Q, and the inverted data output terminal QN Is supplied with a VDD potential. That is, the state of the data output terminal Q is the same as the state of the data input terminal D, and the state of the inverted data output terminal QN is the state opposite to the state of the data input terminal D.
[0029]
Conversely, when the data input terminal D is at the VDD potential, the Nch transistor TN2 is conductive and the output of the inverter circuit INV1 is at the VSS potential, so that the Nch transistor TN3 is nonconductive. The connection point n1 is connected to the ground of the VSS potential through the transistor TN2 and the transistor TN1. As a result, the connection potential of the connection point n1 becomes faster than that of the connection point n2. Discharge occurs through TN6, and the reset input terminal R becomes the VSS potential. Then, the Nch transistor TN7 whose gate has dropped to the VSS potential is inverted to the non-conductive state, and the driving Pch transistor TP4 whose gate has dropped to the VSS potential is inverted to the conductive state. As a result, the set input terminal S is charged via the driving Pch transistor TP4 to have the VDD potential. Since the set input terminal S is at the VDD potential and the reset input terminal R is at the VSS potential, the VSS potential is output to the output terminal of the RS latch 2, the VDD potential is output to the data output terminal Q, and the inverted data output terminal QN Outputs the VSS potential. That is, the state of the data output terminal Q is the same as the state of the data input terminal D, and the state of the inverted data output terminal QN is the state opposite to the state of the data input terminal D.
[0030]
After the evaluation period, that is, after the clock input terminal CLK changes from the VDD potential to the VSS potential and enters the charging period, even if the state of the data input terminal D is inverted, the set input terminal S and the reset input terminal R remain Since both become the VDD potential, the internal state of the RS latch 2 is preserved, and the states of the data output terminal Q and the inverted data output terminal QN are unchanged.
[0031]
Next, the case of executing the reset function will be described. When the reset signal input terminal RSTN is switched from the VDD potential to the VSS potential, the Pch transistor TP20 is inverted to the conductive state, and the reset input terminal R is connected to the DC power supply of the VDD potential via the transistor TP20. Further, the output terminal of the inverter circuit INV5 becomes the VDD potential, the Nch transistor TN20 is inverted to the conductive state, and the set input terminal S is connected to the VSS potential ground through the transistor TN20. When the set input terminal S is pulled to the VSS potential, the Pch transistor TP3 is turned on, and the Nch transistor TN6 is turned off. Therefore, regardless of the state of the Nch transistors TN1 and TN2, the reset input terminal R Does not occur, and conversely, the reset input terminal R is charged through the Pch transistor TP3. The charging of the reset input terminal R is also performed via the Pch transistor TP20. When the reset input terminal R is pulled to the VDD potential, the Pch transistor TP4 is turned off and the Nch transistor TN7 is turned on, so that the charging of the set input terminal S via the Pch transistor TP4 does not occur, and the set Discharge is performed from the input terminal S via the Nch transistor TN20. As a result, the set input terminal S has the VSS potential and the reset input terminal R has the VDD potential. The VDD potential is output to the output terminal of the RS latch 2, the VSS potential is output to the data output terminal Q, and the VDD potential is output to the inverted data output terminal QN. That is, the D-type flip-flop is reset.
[0032]
Next, an operation at the time of shifting from the evaluation period to the charging period will be described.
[0033]
First, a description will be given of a case where the state is shifted from the state where the set input terminal S is at the VSS potential and the reset input terminal R is at the VDD potential to the charging period. The transition to the charging period means that the clock input terminal CLK switches from the VDD potential to the VSS potential. When the clock input terminal CLK becomes the VSS potential, the Pch transistors TP1, TP2 and TP31 become conductive. Note that, during the evaluation period before switching, the Pch transistors TP6, TP10, and TP11 are in a conductive state. Therefore, the switching of the clock input terminal CLK charges the set input terminal S from the VSS potential to the VDD potential via the Pch transistors TP6, TP11 and TP2. The set input terminal S is also charged through the path of the Pch transistors TP10 → TP1 → TP31 → TP30. Further, since the potential of the gate and the drain of the Pch transistor TP4 become equal, the transistor TP4 is kept conductive, and the set input terminal S is charged via the transistor TP4 until the charging is completed. Note that the state of the VSS potential of the data output terminal Q and the state of the VDD potential of the inverted data output terminal QN are unchanged.
[0034]
Next, a case will be described in which the state is shifted from the state where the set input terminal S is at the VDD potential and the reset input terminal R is at the VSS potential to the charging period. When the clock input terminal CLK switches from the VDD potential to the VSS potential, the Pch transistors TP1, TP2, and TP31 become conductive. Note that, during the evaluation period before switching, the Pch transistors TP6, TP10, and TP11 are in a conductive state. Therefore, the switching of the clock input terminal CLK causes the reset input terminal R to be charged from the VSS potential to the VDD potential via the Pch transistors TP10 and TP1. The reset input terminal R is also charged through the path of the Pch transistors TP6 → TP11 → TP2 → TP30 → TP31. Further, since the gate and the drain of the Pch transistor TP3 have the same potential, the transistor TP3 is kept conductive, and the reset input terminal R is charged through the transistor TP3 until the charging is completed. Note that the state of the VDD potential of the data output terminal Q and the state of the VSS potential of the inverted data output terminal QN are unchanged.
[0035]
In the above, the case of the normal operation mode has been described, but the operation is exactly the same in the test operation mode. The clock input terminal CLK is set to the VSS potential. Thereby, Pch transistors TP1, TP2 and TP31 are turned on. The test clock input terminal CKT is switched between the VSS potential and the VDD potential, and the test data input terminal DT is also switched between the VSS potential and the VDD potential. At the time of this test, both the set input terminal S and the reset input terminal R may be at the VSS potential. If the output of the RS latch 2 is the output terminal of the two-input NAND circuit NAND1 and the output terminal of the two-input NAND circuit NAND2, both outputs become the VDD potential. However, such a combination is originally prohibited. One output and the other output must be different from each other. Therefore, the output terminal of the two-input NAND circuit NAND1 is branched into two from the RS latch 2 as shown in FIG. It is used as an inverted data output terminal QN. By doing so, even if both the set input terminal S and the reset input terminal R are at the VSS potential, the data output terminal Q is at the VSS potential and the inverted data output terminal QN is at the VDD potential, so that the output states are different from each other. Can be.
[0036]
As described above, in the scan test-compatible D-type flip-flop with the reset function according to the prior art shown in FIG. 3 to which the functions necessary for the design of the semiconductor integrated circuit are added, during the charging period switched from the evaluation period, Immediately before the switching, charging is performed simultaneously by a plurality of systems on the input terminal of the set input terminal S and the reset input terminal R of the RS latch 2 which has been at the VSS potential of the low-potential power supply potential. The amount of charge is large and the battery does not fall short. Therefore, quick charging can be performed in a short time without particularly increasing the gate width of the transistor in each system, and the scan test-compatible D flip-flop with the reset function can be operated at a high clock frequency. In particular, do not increase the gate width of the Pch transistors TP1 and TP2 connected to the clock input terminal CLK, the Pch transistors TP10 and T11 connected to the test data input terminal DT, and the Pch transistor TP6 connected to the reset signal input terminal RSTN. Often, the input capacitance of those input terminals is increased and the waveform becomes blunted, so that it is not necessary to cause such a disadvantage that synchronous control becomes difficult.
[0037]
[Problems to be solved by the invention]
However, in the case of the scan test-compatible D-type flip-flop having the reset function according to the prior art shown in FIG. 3, the charging of the set input terminal S and the reset input terminal R of the RS latch 2 is performed when the clock input terminal CLK is connected to the VSS. Due to the time restriction on the charging action, which is performed only during the charging period where the potential is attained, it is not possible to cope with a further increase in the clock frequency, and the charging period is insufficient and the charging is insufficient. It is inevitable to fall into.
[0038]
[Means for Solving the Problems]
A D-type flip-flop according to the present invention, in which the master latch is formed by a differential inverter and the slave latch is formed by an RS latch, has different potentials for two input terminals of the RS latch during the evaluation period. After the low-potential-side power supply potential and the high-potential-side power supply potential have been determined, immediately before the transition to the charging period, an independent charging system is established based on the charging start signal generated due to the determination. Is driven to perform charging. Since charging is started from the evaluation period, the effective charging period is secured longer in accordance with the charging period, and the insufficient charging is eliminated even if the clock frequency becomes considerably high.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
A D-type flip-flop according to a first aspect of the present invention is a D-type flip-flop in which a master latch is constituted by a differential inverter and a slave latch is constituted by an RS latch. A two-input EXNOR circuit and a first switching element are inserted between the input terminal and the input terminal, and a second switching element for charging is connected to at least one of the set input terminal and the reset input terminal. A third switching element is inserted between the first switching element and the ground, and the first to third switching elements are turned on based on a charge start signal from a two-input EXNOR circuit. Here, the EXNOR circuit is an exclusive logic NOR circuit. Immediately after the output state of the RS latch is determined during the evaluation period, charging of the input terminal which is the lower potential power supply potential (VSS potential) of the set input terminal and the reset input terminal of the RS latch starts. In other words, since the effective charging period is lengthened by starting charging from the stage before entering the charging period, even if the charge amount is large and the clock frequency is significantly increased, there is no shortage of charging. Do not fall. Therefore, it is not necessary to particularly increase the size of the gates and the like of the switching elements in each system, that is, rapid charging can be performed in a short time without increasing the input capacitance of the clock input terminal. The operation of the D-type flip-flop at the clock frequency becomes possible. In particular, when a function necessary for designing a semiconductor integrated circuit is added, the required amount of charge increases, but this can be sufficiently dealt with. In this case, since charging can be started by a signal different from the clock input signal, the size of a gate or the like of a switching element for charging may be increased.
[0040]
Hereinafter, specific embodiments of a D-type flip-flop according to the present invention will be described in detail with reference to the drawings.
[0041]
[Embodiment 1]
FIG. 1 is a circuit configuration diagram of a scan test compatible D-type flip-flop with a reset function according to the first embodiment. In FIG. 1, the same reference numerals as those in FIG. 3 of the prior art indicate the same elements in the first embodiment, and therefore detailed description will be omitted. The configuration of the first embodiment is different from that of the prior art as follows. TP50 and TP51 are Pch-type MOS transistors, TN300 is an Nch-type MOS transistor, and XNOR1 is a two-input EXNOR circuit, that is, an exclusive logic NOR circuit. The drain of the Pch transistor TP50 is connected to the set input terminal S, and the source is connected to the reset input terminal R. The drain of the Pch transistor TP51 is connected to the DC power supply having the VDD potential of the high potential side power supply potential, and the source is connected to the set input terminal S. Two input terminals of a two-input EXNOR circuit XNOR1 are connected to a set input terminal S and a reset input terminal R, respectively, and output terminals thereof are connected to gates of Pch transistors TP50 and TP51. The sources of the Nch transistors TN1 and TN10 are connected to each other, the drain of the Nch transistor TN300 is connected to the source, and the source is connected to the ground of the VSS potential of the lower potential side power supply potential. The output terminal of the two-input EXNOR circuit XNOR1 is connected to the gate of the Nch transistor TN300. C is a charge start signal output from the two-input EXNOR circuit XNOR1. There are no Pch transistors TP30 and TP31 in the case of the prior art. The Pch transistor TP50 corresponds to the first switching element according to claim 1, the Pch transistor TP51 corresponds to the second switching element according to claim 1, and the Nch transistor TN300 corresponds to the third switching element according to claim 1. Is equivalent to
[0042]
Next, the operation of the first embodiment will be described. As in the case of the prior art, during the evaluation period, one of the set input terminal S and the reset input terminal R of the RS latch 2 is at the VSS potential, and the other is at the VDD potential. As described above, when one of the potentials becomes the VSS potential and the other becomes the VDD potential, the output state of the D-type flip-flop is determined, and thus charging may be started. During a charging period in which both the set input terminal S and the reset input terminal R are at the VDD potential, the charge start signal C output from the two-input EXNOR circuit XNOR1 is at the VDD potential, and the Pch transistor TP50 is in a non-conductive state. ing. However, when the set input terminal S is at the VSS potential and the reset input terminal R is at the VDD potential during the evaluation period, or when the set input terminal S is at the VDD potential and the reset input terminal R is at the VSS potential, the two-input EXNOR is used. The charge start signal C from the circuit XNOR1 becomes the VSS potential, and the Pch transistor TP50 is turned on. At the same time, the Pch transistor TP51 is also turned on, and the Nch transistor TN300 is turned off.
[0043]
When the set input terminal S is at the VSS potential and the reset input terminal R is at the VDD potential, the transistors TN7, TN3, and TN1 are conducting (therefore, the set input terminal S is brought to the VSS potential by the discharge on this path). However, if the transistor TN300 is omitted and the configuration is the same as that of FIG. 3 or the transistor TN300 is in a conductive state, the set input terminal S is still connected to the ground of the VSS potential, Although the VSS potential is held, the transistor TN300 is inverted to the non-conductive state by the inversion of the charge start signal C from the two-input EXNOR circuit XNOR1 to the VSS potential as described above, and the set input terminal S is connected to the ground. It becomes insulated. Further, since the Pch transistor TP51 is turned on by inverting the charge start signal C to the VSS potential, the set input terminal S is charged from the VSS potential to the VDD potential via the transistor TP51. Further, since the Pch transistor TP50 is turned on, the set input terminal S is charged also on the path from the Pch transistor TP3 to the TP50. This charging operation is performed not in the charging period but in the evaluation period. When the charging period starts, the charging is performed as usual. That is, the charging to the set input terminal S is performed on the path of the Pch transistors TP6 → TP11 → TP2 and the path of the Pch transistors TP10 → TP1 → TP50. When the set input terminal S becomes the VDD potential due to this charging, the charge start signal C from the two-input EXNOR circuit XNOR1 is inverted to the VDD potential, and the transistors TP50 and TP51 are inverted to the non-conductive state and the transistor TN300 is inverted to the conductive state. I do.
[0044]
Conversely, when the set input terminal S is at the VDD potential and the reset input terminal R is at the VSS potential, the transistors TN6, TN2 and TN1 are conducting (therefore, the reset input terminal R Has reached the VSS potential ...), but if the transistor TN300 is omitted and the configuration is the same as that of FIG. 3, or if the transistor TN300 is conductive, the reset input terminal R is still connected to the ground. And the VSS potential is maintained, but as described above, the charge start signal C from the two-input EXNOR circuit XNOR1 is inverted to the VSS potential, so that the transistor TN300 is inverted to the non-conductive state, and the reset input terminal R Is insulated from the ground. Further, since the Pch transistors TP51 and TP50 are turned on when the charge start signal C is inverted to the VSS potential, the reset input terminal R is charged from the VSS potential to the VDD potential via the transistors TP51 and TP50. Will be. Also, charging is performed on the reset input terminal R in the path from the Pch transistor TP4 to the TP50. This charging operation is performed not in the charging period but in the evaluation period. When the charging period starts, the charging is performed as usual. That is, the reset input terminal R is charged through the path of the Pch transistor TP6 → TP11 → TP2 → TP50 and the path of the Pch transistor TP10 → TP1. When the reset input terminal R becomes the VDD potential by this charging, the charge start signal C from the two-input EXNOR circuit XNOR1 is inverted to the VDD potential, and the transistors TP50 and TP51 are inverted to the non-conductive state and the transistor TN300 is inverted to the conductive state. I do.
[0045]
As described above, when the functions necessary for the design of the semiconductor integrated circuit are added, the set input terminal S and the reset input terminal R of the RS latch 2 are connected immediately after the output state of the RS latch 2 is determined during the evaluation period. Since the charging to the input terminal which has been at the VSS potential of the low potential side power supply potential is started, that is, by starting the charging from the stage before the charging period is started, the effective charging period is lengthened. However, the charge amount is large and the battery does not fall short. Therefore, it is possible to charge a sufficient amount of charge without particularly increasing the gate width of the transistor in each system, and to operate a scan test-compatible D-type flip-flop with a reset function at an extremely high clock frequency. Can be. In particular, do not increase the gate width of the Pch transistors TP1 and TP2 connected to the clock input terminal CLK, the Pch transistors TP10 and T11 connected to the test data input terminal DT, and the Pch transistor TP6 connected to the reset signal input terminal RSTN. Often, the inconvenience of increasing the input capacitance of those input terminals and making the waveform blunt does not have to be caused. Further, even if the gate widths of the Pch transistors TP50 and TP51 are increased, there is no particular problem in terms of synchronization. By increasing the gate width, more rapid charging is possible.
[0046]
[Embodiment 2]
The second embodiment relates to a modification of the first embodiment, and has a simple form as in FIG. 5 in the case of the related art. As shown in FIG. 2, similarly to the first embodiment, the two-input EXNOR circuit XNOR1, the Pch transistors TP50 and TP51, and the Nch transistor TN300 are similarly connected. The operation and effect are the same as those in the first embodiment.
[0047]
【The invention's effect】
According to the present invention for the D-type flip-flop, the following effects can be obtained. That is, after the potentials of the two input terminals of the RS latch that are in different states (low-potential-side power supply potential and high-potential-side power supply potential) are determined in the evaluation period, the two independent input terminals are immediately independent at the stage before the transition to the charging period. Since the charging is driven by driving the charging system, that is, charging is started from the evaluation period, a longer effective charging period is secured together with the charging period, and shortage of charging is achieved regardless of the significant increase in clock frequency. To eliminate. Therefore, the size of the gate of the switching element in each charging system does not need to be particularly large, and rapid charging can be performed in a short time without increasing the input capacity of the clock input terminal. The operation of the D-type flip-flop at the frequency becomes possible. In particular, when a function necessary for designing a semiconductor integrated circuit is added, a necessary charge amount increases. However, it is possible to sufficiently cope with this.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a scan test-compatible D-type flip-flop with a reset function according to a first embodiment;
FIG. 2 is a circuit configuration diagram of a D-type flip-flop having a differential-RS latch configuration according to a second embodiment;
FIG. 3 is a circuit configuration diagram of a scan test compatible D-type flip-flop with a reset function according to the prior art.
FIG. 4 is a circuit configuration diagram of a D-type flip-flop corresponding to a scan test with a reset function according to the related art
FIG. 5 is a circuit configuration diagram of a conventional D-type flip-flop having a differential-RS latch configuration.
[Explanation of symbols]
1 ... Differential inverter
2. RS latch
TP1, TP2, TP3, TP4, TP6, TP10,
TP11, TP20, TP50, TP51 ... Pch type MOS transistor
TN1, TN2, TN3, TN4, TN5, TN6, TN7,
TN9, TN10, TN20, TN300 ... N-channel MOS transistor
INV1, INV2, INV5, INV10,
INV20, INV21 ... Inverter circuit
NAND1, NAND2... 2-input NAND circuit
XNOR1 2-input EXNOR circuit
D: Data input terminal
DT: Test data input terminal
CLK: Clock input terminal
CKT: Test clock input terminal
RSTN: Reset signal input terminal
S: Set input terminal
R: Reset input terminal
Q: Data output terminal
QN: Inverted data output terminal

Claims (1)

A master latch is constituted by a differential inverter, and a slave latch is constituted by a D-type flip-flop constituted by an RS latch. A two-input EXNOR circuit and a first A switching element is inserted, a second switching element for charging is connected to at least one of the set input terminal and the reset input terminal, and a third switching element is inserted between the differential inverter and the ground. A D-type flip-flop configured to conduct the first to third switching elements based on a charge start signal from a two-input EXNOR circuit.

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