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JP3580207B2 - Display device - Google Patents
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JP3580207B2 - Display device - Google Patents

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Publication number
JP3580207B2
JP3580207B2 JP2000024872A JP2000024872A JP3580207B2 JP 3580207 B2 JP3580207 B2 JP 3580207B2 JP 2000024872 A JP2000024872 A JP 2000024872A JP 2000024872 A JP2000024872 A JP 2000024872A JP 3580207 B2 JP3580207 B2 JP 3580207B2
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Japan
Prior art keywords
power supply
semiconductor chip
chip mounting
display panel
mounting area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP2000024872A
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Japanese (ja)
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JP2001215892A (en
Inventor
真一 加藤
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2000024872A priority Critical patent/JP3580207B2/en
Priority to US09/772,660 priority patent/US6587177B2/en
Priority to KR1020010004457A priority patent/KR20010078177A/en
Priority to TW090102014A priority patent/TW463140B/en
Priority to CNB011026049A priority patent/CN1162818C/en
Publication of JP2001215892A publication Critical patent/JP2001215892A/en
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Publication of JP3580207B2 publication Critical patent/JP3580207B2/en
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Description

【0001】
【発明の属する技術分野】
この発明は液晶表示装置等の表示装置に関する。
【0002】
【従来の技術】
図5は従来の液晶表示装置の一例の平面図を示したものである。この液晶表示装置はアクティブマトリクス型の液晶表示パネル1を備えている。液晶表示パネル1は、下ガラス基板2と上ガラス基板3とがシール材(図示せず)を介して貼り合わされ、その間に液晶(図示せず)が封入されたものからなっている。この場合、下ガラス基板2の下辺部および右辺部は上ガラス基板3から突出されている。
【0003】
下ガラス基板2の下側の突出部2aの上面の所定の4箇所に直列的に設けられた半導体チップ搭載領域21(図6(a)参照)には半導体チップ4が異方性導電接着剤(図示せず)を介して搭載されている。下ガラス基板2の右側の突出部2bの上面の所定の箇所に設けられた半導体チップ搭載領域には半導体チップ5が異方性導電接着剤(図示せず)を介して搭載されている。半導体チップ4、5は、液晶駆動用のLSI等からなっている。
【0004】
下ガラス基板2の上面において二点鎖線で囲まれた表示領域6には、図示していないが、複数の走査線が行方向(図5の紙面左右方向)に延びて設けられているとともに、複数の信号線が列方向(図5の紙面上下方向)に延びて設けられている。走査線の右端部は、下ガラス基板2の上面の所定の箇所に設けられた出力配線7を介して右側の半導体チップ5に接続されている。したがって、右側の半導体チップ5は複数の走査線に電圧を供給する走査線駆動用のものである。信号線の下端部は、下ガラス基板2の上面の所定の4箇所に設けられた出力配線8を介して下側の半導体チップ4に接続されている。したがって、下側の半導体チップ4は複数の信号線に電圧を供給する信号線駆動用のものである。
【0005】
下ガラス基板2の下側の突出部2aの上面において半導体チップ4搭載領域の外側にはフレキシブル配線基板11の一端部下面が異方性導電接着剤(図示せず)を介して接合されている。フレキシブル配線基板11と下側の半導体チップ4とは、下ガラス基板2の下側の突出部2aおよびその近傍の上面の所定の4箇所に設けられた入力配線12を介して接続されている。フレキシブル配線基板11と右側の半導体チップ5とは、下ガラス基板2の右側の突出部2bおよびその近傍の上面の所定の箇所に設けられた入力配線13を介して接続されている。
【0006】
次に、図6(a)は図5に示す液晶表示パネル1の右下部の一部の分解した状態における透過拡大平面図を示したものである。下ガラス基板2の下側の突出部2aの上面において一点鎖線で囲まれた領域21は、半導体チップ4が搭載される半導体チップ搭載領域である。入力配線12は信号入力用配線と電源用配線とからなっている。信号入力用配線は、半導体チップ搭載領域21内の右上部に設けられた複数の信号入力用接続端子12a(図7(b)参照)と、これらの信号入力用接続端子12aから半導体チップ搭載領域21の右側において下ガラス基板2の下側の突出端近傍まで延ばされた複数の信号入力線12bとからなっている。電源用配線は、半導体チップ搭載領域21内の右下部に設けられた4つの電源用接続端子12c(図7(b)参照)と、これらの電源用接続端子12cから半導体チップ搭載領域21の右下側において下ガラス基板2の下側の突出端近傍まで延ばされた4つの電源線12dとからなっている。
【0007】
ここで、信号入力用配線および電源用配線はITO等の透明金属によって形成されている。そして、電源用配線を信号入力用配線に比較して幅広に形成しているのは、電源用配線には信号入力用配線よりも大きな電流が流れるので、その配線抵抗を低くするためである。なお、入力配線13およびその近傍に設けられたクロス用配線14については、その詳細な説明を省略する。
【0008】
フレキシブル配線基板11は、図5に示すように、帯状部22aおよびこの帯状部22aの下辺の所定の箇所から突出された突出部22bを有するフィルム22を備えている。そして、図6(b)の透過拡大平面図に図示される如く、フィルム22の帯状部22aの下面の各所定の箇所には、4組の入力配線12の信号入力線12bおよび電源線12dに接続される4組の接続端子23a、23b、1組の入力配線13に接続される1組の接続端子24およびクロス用配線14に接続される接続端子25が設けられている。
【0009】
図5および図6(b)において、一番右側の1組の接続端子23a、23bおよび接続端子24、25は、フィルム22の突出部22bの突出端部下面に設けられた接続端子(図示せず)に、フィルム22の帯状部22aおよび突出部22bの下面に設けられた引き回し線(図示せず)を介して接続されている。一方、残りの3組の接続端子23a、23bは、図示しないスルーホールおよびフィルム22の上面に上記接続端子23a、23bを横断して形成された中継配線を介して上記一番右側の1組の接続端子23a、23bの各対応する接続端子に接続されている。すなわち、フレキシブル配線基板11は、接続端子24、25と4組の接続端子23a、23bが下面に形成され、一番右側の1組の接端子23a、23bと残りの3組の接端子23a、23bとを接続する中継配線が上面に形成された両面配線基板となされているものであり、4組の接続端子23a、23bはフィルム22の帯状部22aの下面に並列的に設けられ、そのうちの所定の1組はフィルム22の帯状部22aの下面に設けられた引き回し線に直接接続され、残りの3組はスルーホール等を介して上記引き回し線に接続されているのである。
【0010】
次に、7(a)は図6(a)に示す液晶表示パネル1の半導体チップ搭載領域21に搭載される半導体チップ4の端子位置を示すための透過拡大平面図、図7(b)は図6(a)に示す液晶表示パネル1の半導体チップ搭載領域21の拡大平面図である。半導体チップ搭載領域21内の上辺部には出力配線8の一端部からなる出力用接続端子8aが設けられている。半導体チップ4の下面の右上部には複数の信号入力用バンプ電極31が設けられ、右下部には4組の電源用バンプ電極32が設けられ、上辺部には複数の出力用バンプ電極33が設けられ、下辺部には複数のダミーバンプ電極34が設けられている。上記において、電源用バンプ電極32は、一対毎に図示しないパターンで接続されており、各1組が1本の電源線12dに対応している。
【0011】
そして、半導体チップ4を半導体チップ搭載領域21に異方性導電接着剤を介して搭載した状態では、半導体チップ4の信号入力用バンプ電極31、電源用バンプ電極32および出力用バンプ電極33は、液晶表示パネル1の信号入力用接続端子12a、電源用接続端子12cおよび出力用接続端子8aに接続されている。ダミーバンプ電極34は、半導体チップ4を半導体チップ搭載領域21に異方性導電接着剤を介して熱圧着して搭載するときの圧力が半導体チップ4下の異方性導電接着剤に均一に加わるようにするためのものである。
【0012】
【発明が解決しようとする課題】
ところで、従来のこのような液晶表示装置におけるフレキシブル配線基板11では、フィルム22の帯状部22aの下面に4組の接続端子23a、23bを並列的に設け、所定の3組の接続端子23a、23bをスルーホール等を介して、フィルム22の帯状部22aの下面に設けられた共通の引き回し線に接続しているので、フィルム22の帯状部22aの幅が大きくなり、ひいては全体の占有面積が大きくなり、その上、スルーホールを有する両面配線の複雑な構造となり、したがってコスト高になってしまうという問題があった。
この発明の課題は、フレキシブル配線基板の占有面積を小さくし、且つ、片面配線の簡単な構造とすることである。
【0013】
【課題を解決するための手段】
この発明は、一辺部に配列された複数の半導体チップ搭載領域を有する表示パネルと、該表示パネルの前記各半導体チップ搭載領域に搭載された複数の半導体チップと、前記表示パネルの一辺部であって前記半導体チップ搭載領域の外側に接合されたフレキシブル配線基板とを備えた表示装置において、前記複数の半導体チップ搭載領域の中、一端側に対応する半導体チップ搭載領域に対応して、前記表示パネルの一辺部に沿って、信号入力用配線の一端部と電源線の一端部とを前記表示パネルの一辺部と垂直な方向に延出して配列し、他の半導体チップ搭載領域に対応して電源線の一端部を設け、前記信号入力用配線を、信号入力用配線の一端部から前記各半導体チップ搭載領域内を通過するように設け、前記各電源線を、前記電源線の一端部から前記半導体チップ搭載領域内に設けられた電源接続端子および該電源接続端子を通過して前記半導体チップ搭載領域外に延出された他端部を有する形状とし、前記フレキシブル配線基板の前記表示パネルと対応する面に、前記信号入力用配線の一端部に接続される接続端子、前記電源線の一端部に接続される接続端子および前記電源線の他端部と隣接の電源線の一端部とを接続する電源用中継配線を設けたものである
【0014】
【発明の実施の形態】
図1はこの発明の一実施形態における液晶表示装置の平面図、図2(a)は図1に示す液晶表示パネルの右下部の一部の分解した状態における透過拡大平面図、図2(b)は図2(a)の液晶表示パネルの領域に対応する部分のフレキシブル配線基板の透過拡大平面図、図3(a)は図1に示す液晶表示パネルの右下部の図2(a)とは異なる一部の分解した状態における透過拡大平面図、図3(b)は図3(a)の液晶表示パネルの領域に対応する部分のフレキシブル配線基板の透過拡大平面図、図4(a)は図2(a)に示す液晶表示パネルの半導体チップ搭載領域に搭載される半導体チップの端子位置を示すための透過拡大平面図、図4(b)は図2(a)に示す液晶表示パネルの半導体チップ搭載領域の拡大平面図を示したものである。これらの図において、図5〜図7と同一名称部分には同一の符号を付し、その説明を適宜省略する。
【0015】
この実施形態における液晶表示パネル1の半導体チップ4に入力される入力配線のうち信号入力用配線41は、図4(b)に示すように、半導体チップ搭載領域21内の右上部に設けられた複数の電極接続端子42aを有する。そして、図2(a)において右端側の半導体チップ搭載領域21についてみると、当該半導体チップ搭載領域21内に設けられた電極接続端子42aから当該半導体チップ搭載領域21の右側において下ガラス基板2の下側の突出端近傍まで延びる信号入力用端子42bが設けられている。次に、相隣接する半導体チップ搭載領域21についてみると、右側の半導体チップ搭載領域21内に設けられた電極接続端子42aと左側の半導体チップ搭載領域21内に設けられた電極接続端子42aとを接続する信号入力用中継配線43が、右側の半導体チップ搭載領域21内および右側の半導体チップ搭載領域21と左側の半導体チップ搭載領域21との間に設けられている。つまり、信号入力用配線41は、各半導体チップ4の信号入力用の電極を共通に接続するよう下ガラス基板2に形成されており、この場合、各半導体チップ搭載領域21においては、ほぼその全長に亘りその幅内に収まるように配線され、半導体チップ搭載領域21間では、後述する電源用配線を表示領域6側に迂回する信号入力用中継配線43として配線されている。
【0016】
上記入力配線のうち電源用配線は、図4(b)に示すように、半導体チップ搭載領域21内の右側に設けられた4つの電源用接続端子44と、図4(b)において最も下側の電源用接続端子44から下側に向かって下ガラス基板2の下側の突出端近傍まで延ばされた電源線45と、残りの3つの電源用接続端子44から右下側に向かって下ガラス基板2の下側の突出端近傍まで延ばされた電源線46と、残りの3つの電源用接続端子44から左下側に向かって下ガラス基板2の下側の突出端近傍まで延ばされた電源線47とからなっている。ただし、この場合、図1において最も左側の半導体チップ搭載領域21についてみると、図3(a)に示すように、電源線47は設けられていない。また、所定の電源線の先端部はほぼL字状となっているが、他の電源線と同様に、直線状としてもよい。なお、図4(a)に示すように、半導体チップ4の下面の右側に4組の電源用バンプ電極32が設けられている。
【0017】
フレキシブル配線基板11は、図1に示すように、幅狭の帯状部22aおよびこの帯状部22aの下辺の所定の箇所から突出された突出部22bを有するフィルム22を備えている。そして、図2(b)に示すように、フィルム22の帯状部22aの下面の右側の各所定の箇所には、右側の電源線45、46、信号入力用端子42b、クロス用配線14および入力配線13に接続される接続端子51〜55が設けられている。これらの接続端子51〜55は、フィルム22の突出部22bの突出端部下面に設けられた接続端子(図示せず)に、フィルム22の帯状部22aおよび突出部22bの下面に設けられた引き回し線56を介して接続されている。
【0018】
フィルム22の帯状部22aの下面の他の各所定の箇所には、電源線45、46、47(ただし、図2(a)の右側の電源線45、46を除く)に接続される接続端子57、58、59が設けられている。このうち接続端子57は、フィルム22の帯状部22aの下面に設けられた電源用中継配線61を介して、接続端子51に接続された引き回し線56に接続されている。左側の接続端子58と右側の接続端子59は、フィルム22の帯状部22aの下面に設けられた電源用中継配線62を介して互いに接続されている。
【0019】
次に、フレキシブル配線基板11の一端部下面を下ガラス基板2の下側の突出部2aの上面において半導体チップ搭載領域21の外側に異方性導電接着剤(図示せず)を介して接合した状態の一部について説明する。フレキシブル配線基板11の接続端子53は、信号入力用端子42bを介して図2(a)の右側の半導体チップ搭載領域21内の電極接続端子42aに接続され、さらにその左側の信号入力用中継配線43を介してその左側の半導体チップ搭載領域21内の電極接続端子42aに接続され、さらに同様にして、残りの2つの半導体チップ搭載領域21内の電極接続端子42aに接続されている。
【0020】
フレキシブル配線基板11の接続端子51、57は、電源線45を介して半導体チップ搭載領域21内の図4(b)において最も下側の電源用接続端子44に接続されている。すなわち、図2(a)において右側の半導体チップ搭載領域21内の図4(b)において最も下側の電源用接続端子44は、電源線45および接続端子51を介して、接続端子51に接続された引き回し線56に接続されている。残りの3つの半導体チップ搭載領域21内の図4(b)において最も下側の電源用接続端子44は、電源線45、接続端子57および電源用中継配線61を介して、接続端子51に接続された引き回し線56に接続されている。
【0021】
フレキシブル配線基板11の接続端子52は、図2(a)の右側の電源線46を介して図2(a)の右側の半導体チップ搭載領域21内の残りの3つの電源用接続端子44に接続され、さらにその左側の電源線47、接続端子59、電源用中継配線62、接続端子58および電源線46を介して、その左側の半導体チップ搭載領域21内の残りの3つの電源用接続端子44に接続され、さらに同様にして、残りの2つの半導体チップ搭載領域21内の残りの3つの電源用接続端子44に接続されている。すなわち、4つの半導体チップ搭載領域21内の残りの3つの電源用接続端子44は、最終的には、図2(a)の右側の電源線46および接続端子52を介して、接続端子52に接続された引き回し線56に接続されている。
【0022】
このように、この液晶表示装置では、液晶表示パネル1の4つの半導体チップ搭載領域21内の各右側およびその各近傍に電源用接続端子44を含む電源線45、46、47を設け、フレキシブル配線基板11のフィルム22の帯状部22aの下面に、液晶表示パネル1の各半導体チップ搭載領域21に対して設けられた電源線45、46、47のうち相隣接するもの同士(45と45および46と47)を接続する電源用中継配線61、62を設けている。そして、これにより、液晶表示パネル1の4つの半導体チップ搭載領域21内の各右側に設けられた電源用接続端子44のうち図4(b)の上側の3つの電源用接続端子44を直列的に接続し、残りの1つの電源用接続端子44を並列的に接続している。この結果、フレキシブル配線基板11のフィルム22の帯状部22aの下面の左側には接続端子57、58、59および電源用中継配線61、62を設ければよく、フィルム22の帯状部22aの幅が小さくなり、フレキシブル配線基板11の占有面積を小さくすることができ、また片面配線の簡単な構造とすることができ、ひいてはフレキシブル配線基板11のコストを低減することができる。
【0023】
また、この液晶表示装置では、液晶表示パネル1の下ガラス基板2の下側の突出部2aの上面に信号入力用中継配線43を設けているが、この信号入力用中継配線43を半導体チップ搭載領域21内に設けているので、下ガラス基板2の下側の突出部2aの幅(額縁の幅)が大きくならないようにすることができる。
【0024】
なお、上記実施形態では、液晶表示パネル1の4つの半導体チップ搭載領域21内の各右側に設けられた電源用接続端子44のうち図4(b)の最も下側の電源用接続端子44を並列的に接続しているが、これに限らず、この電源用接続端子44も残りの3つの電源用接続端子44と同様に直列的に接続するようにしてもよい。また、上記実施形態では、信号入力用中継配線43を液晶表示パネル1に設けているが、これに限らず、電源用中継配線61、62等の場合と同様に、フレキシブル配線基板11のフィルム22の帯状部22aの下面に設けるようにしてもよい。
【0025】
以上説明した通り、この発明によれば、フレキシブル配線基板の表示パネルと対応する面に、表示パネルに形成された信号入力用配線の一端部に接続される接続端子、電源線の一端部に接続される接続端子および電源線の他端部と隣接の電源線の一端部とを接続する電源用中継配線を設けるようにしたので、フレキシブル配線基板の占有面積を小さくすることができ、また片面配線の簡単な構造とすることができ、ひいてはフレキシブル配線基板のコストを低減することができる。
【図面の簡単な説明】
【図1】この発明の一実施形態における液晶表示装置の平面図。
【図2】(a)は図1に示す液晶表示パネルの右下部の一部の分解した状態における透過拡大平面図、(b)は図2(a)の液晶表示パネルの領域に対応する部分のフレキシブル配線基板の透過拡大平面図。
【図3】(a)は図1に示す液晶表示パネルの右下部の図2(a)とは異なる一部の分解した状態における透過拡大平面図、(b)は図3(a)の液晶表示パネルの領域に対応する部分のフレキシブル配線基板の透過拡大平面図。
【図4】(a)は図2(a)に示す液晶表示パネルの半導体チップ搭載領域に搭載される半導体チップの端子位置を示すための透過拡大平面図、(b)は図2(a)に示す液晶表示パネルの半導体チップ搭載領域の拡大平面図。
【図5】従来の液晶表示装置の一例を示す平面図。
【図6】(a)は図5に示す液晶表示パネルの右下部の一部の分解した状態における透過拡大平面図、(b)は図6(a)の液晶表示パネルの領域に対応する部分のフレキシブル配線基板の透過拡大平面図。
【図7】(a)は図6(a)に示す液晶表示パネルの半導体チップ搭載領域に搭載される半導体チップの端子位置を示すための透過拡大平面図、(b)は図6(a)に示す液晶表示パネルの半導体チップ搭載領域の拡大平面図。
【符号の説明】
1 液晶表示パネル
2 下ガラス基板
2a 突出部
4 半導体チップ
11 フレキシブル配線基板
22 フィルム
22a 帯状部
22b 突出部
41 信号入力用配線
42a 電極接続端子
42b 信号入力用端子
43 信号入力用中継配線
44 電源用接続端子
45、46、47 電源線
51、52、53 接続端子
57、58、59 接続端子
61、62 電源用中継配線
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display device such as a liquid crystal display device.
[0002]
[Prior art]
FIG. 5 is a plan view showing an example of a conventional liquid crystal display device. This liquid crystal display device includes an active matrix type liquid crystal display panel 1. The liquid crystal display panel 1 is composed of a lower glass substrate 2 and an upper glass substrate 3 bonded together via a sealing material (not shown), and a liquid crystal (not shown) sealed therebetween. In this case, the lower side and the right side of the lower glass substrate 2 project from the upper glass substrate 3.
[0003]
The semiconductor chip 4 is provided with an anisotropic conductive adhesive in a semiconductor chip mounting area 21 (see FIG. 6A) provided in series at predetermined four places on the upper surface of the lower projecting portion 2a of the lower glass substrate 2. (Not shown). A semiconductor chip 5 is mounted via an anisotropic conductive adhesive (not shown) in a semiconductor chip mounting area provided at a predetermined location on the upper surface of the right protrusion 2b of the lower glass substrate 2. The semiconductor chips 4 and 5 are composed of a liquid crystal driving LSI or the like.
[0004]
Although not shown, a plurality of scanning lines are provided in the display area 6 surrounded by the two-dot chain line on the upper surface of the lower glass substrate 2 so as to extend in the row direction (the left-right direction in FIG. 5). A plurality of signal lines are provided so as to extend in the column direction (vertical direction in FIG. 5). The right end of the scanning line is connected to the right semiconductor chip 5 via an output wiring 7 provided at a predetermined position on the upper surface of the lower glass substrate 2. Therefore, the semiconductor chip 5 on the right side is for driving a scanning line for supplying a voltage to a plurality of scanning lines. The lower ends of the signal lines are connected to the lower semiconductor chip 4 via output wirings 8 provided at four predetermined locations on the upper surface of the lower glass substrate 2. Therefore, the lower semiconductor chip 4 is for driving a signal line for supplying a voltage to a plurality of signal lines.
[0005]
The lower surface of one end of the flexible wiring board 11 is bonded to the upper surface of the lower protrusion 2a on the lower side of the lower glass substrate 2 outside the mounting area of the semiconductor chip 4 via an anisotropic conductive adhesive (not shown). . The flexible wiring board 11 and the lower semiconductor chip 4 are connected via the lower protrusion 2a on the lower glass substrate 2 and input wirings 12 provided at four predetermined locations on the upper surface in the vicinity of the lower protrusion 2a. The flexible wiring board 11 and the right semiconductor chip 5 are connected via the right projection 2b of the lower glass substrate 2 and input wiring 13 provided at a predetermined location on the upper surface in the vicinity thereof.
[0006]
Next, FIG. 6A is an enlarged transmission plan view showing a part of the lower right portion of the liquid crystal display panel 1 shown in FIG. 5 in an exploded state. A region 21 surrounded by an alternate long and short dash line on the upper surface of the lower projection 2a on the lower glass substrate 2 is a semiconductor chip mounting region on which the semiconductor chip 4 is mounted. The input wiring 12 includes a signal input wiring and a power supply wiring. The signal input wiring includes a plurality of signal input connection terminals 12a (see FIG. 7B) provided at the upper right portion in the semiconductor chip mounting area 21, and the signal input connection terminals 12a and the semiconductor chip mounting area. 21 and a plurality of signal input lines 12b extending to the vicinity of the lower protruding end of the lower glass substrate 2. The power supply wiring includes four power supply connection terminals 12c (see FIG. 7B) provided at the lower right of the semiconductor chip mounting area 21 and these power supply connection terminals 12c to the right of the semiconductor chip mounting area 21. On the lower side, four power supply lines 12d are extended to the vicinity of the lower protruding end of the lower glass substrate 2.
[0007]
Here, the signal input wiring and the power supply wiring are formed of a transparent metal such as ITO. The reason why the power supply wiring is formed wider than the signal input wiring is to reduce the wiring resistance because a larger current flows through the power supply wiring than the signal input wiring. The detailed description of the input wiring 13 and the cross wiring 14 provided in the vicinity thereof is omitted.
[0008]
As shown in FIG. 5, the flexible wiring board 11 includes a film 22 having a band 22a and a protrusion 22b protruding from a predetermined position on the lower side of the band 22a. Then, as shown in the transmission enlarged plan view of FIG. 6B, the signal input lines 12 b and the power supply lines 12 d of the four input wirings 12 are provided at predetermined positions on the lower surface of the strip 22 a of the film 22. Four sets of connection terminals 23a and 23b to be connected, one set of connection terminals 24 connected to one set of input wirings 13, and connection terminals 25 connected to the cross wiring 14 are provided.
[0009]
In FIG. 5 and FIG. 6B, the rightmost pair of connection terminals 23a and 23b and the connection terminals 24 and 25 are connection terminals (not shown) provided on the lower surface of the projecting end of the projecting portion 22b of the film 22. ) Are connected to each other via a lead wire (not shown) provided on the lower surface of the strip 22a and the protruding portion 22b of the film 22. On the other hand, the remaining three sets of connection terminals 23a and 23b are connected to the rightmost one set via a through hole (not shown) and a relay wire formed across the connection terminals 23a and 23b on the upper surface of the film 22. The connection terminals 23a and 23b are connected to corresponding connection terminals. That is, in the flexible wiring board 11, the connection terminals 24 and 25 and four sets of connection terminals 23a and 23b are formed on the lower surface, and the rightmost set of connection terminals 23a and 23b and the remaining three sets of connection terminals 23a and 23a. The relay wiring for connecting to the wiring 22b is formed as a double-sided wiring board formed on the upper surface, and four sets of connection terminals 23a and 23b are provided in parallel on the lower surface of the strip 22a of the film 22, and One of the predetermined sets is directly connected to a wiring line provided on the lower surface of the strip 22a of the film 22, and the remaining three sets are connected to the wiring lines through through holes and the like.
[0010]
Next, FIG. 7A is a transparent enlarged plan view showing the terminal positions of the semiconductor chip 4 mounted on the semiconductor chip mounting area 21 of the liquid crystal display panel 1 shown in FIG. 6A, and FIG. FIG. 7 is an enlarged plan view of a semiconductor chip mounting area 21 of the liquid crystal display panel 1 shown in FIG. An output connection terminal 8 a formed of one end of the output wiring 8 is provided at an upper side in the semiconductor chip mounting area 21. A plurality of signal input bump electrodes 31 are provided in the upper right portion of the lower surface of the semiconductor chip 4, four power supply bump electrodes 32 are provided in the lower right portion, and a plurality of output bump electrodes 33 are provided in the upper side portion. A plurality of dummy bump electrodes 34 are provided on the lower side. In the above description, the power supply bump electrodes 32 are connected in pairs (not shown) in a pattern, and each set corresponds to one power supply line 12d.
[0011]
When the semiconductor chip 4 is mounted on the semiconductor chip mounting area 21 via an anisotropic conductive adhesive, the signal input bump electrode 31, the power supply bump electrode 32, and the output bump electrode 33 of the semiconductor chip 4 The liquid crystal display panel 1 is connected to the signal input connection terminal 12a, the power supply connection terminal 12c, and the output connection terminal 8a. The dummy bump electrode 34 is designed so that the pressure when the semiconductor chip 4 is mounted on the semiconductor chip mounting area 21 by thermocompression bonding via an anisotropic conductive adhesive is uniformly applied to the anisotropic conductive adhesive under the semiconductor chip 4. It is to make it.
[0012]
[Problems to be solved by the invention]
By the way, in the flexible wiring board 11 in such a conventional liquid crystal display device, four sets of connection terminals 23a and 23b are provided in parallel on the lower surface of the strip 22a of the film 22, and three predetermined sets of connection terminals 23a and 23b are provided. Is connected to a common lead line provided on the lower surface of the band-shaped portion 22a of the film 22 through a through hole or the like, so that the width of the band-shaped portion 22a of the film 22 is increased, and the overall occupied area is increased. In addition, there is a problem that the structure becomes complicated with double-sided wiring having through holes, and thus the cost is increased.
An object of the present invention is to reduce the area occupied by a flexible wiring board and to provide a simple structure of single-sided wiring.
[0013]
[Means for Solving the Problems]
The present invention provides a display panel having a plurality of semiconductor chip mounting areas arranged on one side, a plurality of semiconductor chips mounted on each of the semiconductor chip mounting areas of the display panel, and one side of the display panel. A flexible wiring board bonded to the outside of the semiconductor chip mounting area, the display panel corresponding to a semiconductor chip mounting area corresponding to one end of the plurality of semiconductor chip mounting areas. One end of the signal input wiring and one end of the power supply line are arranged so as to extend in a direction perpendicular to one side of the display panel along one side of the display panel. One end of the power supply line is provided, and the signal input wiring is provided so as to pass from one end of the signal input wiring to the inside of each of the semiconductor chip mounting regions. A portion having a power connection terminal provided in the semiconductor chip mounting region from the portion and the other end portion extending through the power connection terminal and outside the semiconductor chip mounting region; A connection terminal connected to one end of the signal input wiring, a connection terminal connected to one end of the power supply line, and one end of a power supply line adjacent to the other end of the power supply line on a surface corresponding to the panel And a power supply relay wiring for connecting the power supply and the power supply .
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a plan view of a liquid crystal display device according to an embodiment of the present invention, FIG. 2A is an enlarged transmission plan view of a part of the lower right portion of the liquid crystal display panel shown in FIG. 3) is a transparent enlarged plan view of a portion of the flexible wiring board corresponding to the area of the liquid crystal display panel of FIG. 2A, and FIG. 3A is a view of FIG. 2A at the lower right of the liquid crystal display panel shown in FIG. FIG. 3B is an enlarged transmission plan view of a part of a different disassembled state, FIG. 3B is an enlarged transmission plan view of a portion of the flexible wiring board corresponding to the area of the liquid crystal display panel in FIG. FIG. 4A is an enlarged transparent plan view showing a terminal position of a semiconductor chip mounted in a semiconductor chip mounting area of the liquid crystal display panel shown in FIG. 2A, and FIG. 4B is a liquid crystal display panel shown in FIG. 2 is an enlarged plan view of the semiconductor chip mounting area of FIG. . In these figures, the same reference numerals are given to the same parts as those in FIGS. 5 to 7, and the description thereof will be omitted as appropriate.
[0015]
As shown in FIG. 4B, a signal input wiring 41 among input wirings input to the semiconductor chip 4 of the liquid crystal display panel 1 in this embodiment is provided at an upper right portion in the semiconductor chip mounting area 21. It has a plurality of electrode connection terminals 42a. 2A, when looking at the semiconductor chip mounting area 21 on the right end side, the lower glass substrate 2 is located on the right side of the semiconductor chip mounting area 21 from the electrode connection terminals 42a provided in the semiconductor chip mounting area 21. A signal input terminal 42b extending to the vicinity of the lower protruding end is provided. Next, regarding the adjacent semiconductor chip mounting areas 21, electrode connection terminals 42a provided in the right semiconductor chip mounting area 21 and electrode connection terminals 42a provided in the left semiconductor chip mounting area 21 are shown. The signal input relay wiring 43 to be connected is provided in the right semiconductor chip mounting area 21 and between the right semiconductor chip mounting area 21 and the left semiconductor chip mounting area 21. That is, the signal input wiring 41 is formed on the lower glass substrate 2 so as to connect the signal input electrodes of the semiconductor chips 4 in common. The power supply wiring, which will be described later, is routed to the display area 6 side as a signal input relay wiring 43 between the semiconductor chip mounting areas 21.
[0016]
As shown in FIG. 4B, the power supply wiring among the input wirings includes four power supply connection terminals 44 provided on the right side in the semiconductor chip mounting area 21 and the lowermost wiring in FIG. 4B. The power supply line 45 extends from the power supply connection terminal 44 to the vicinity of the lower protruding end of the lower glass substrate 2 downward, and the power supply line 45 extends downward from the remaining three power supply connection terminals 44 to the lower right. The power supply line 46 extends to the vicinity of the lower protruding end of the glass substrate 2, and extends from the remaining three power supply connection terminals 44 to the lower left side to the vicinity of the lower protruding end of the lower glass substrate 2. And a power supply line 47. However, in this case, regarding the leftmost semiconductor chip mounting area 21 in FIG. 1, the power supply line 47 is not provided as shown in FIG. Further, the end of the predetermined power supply line is substantially L-shaped, but may be linear like other power supply lines. As shown in FIG. 4A, four sets of power supply bump electrodes 32 are provided on the right side of the lower surface of the semiconductor chip 4.
[0017]
As shown in FIG. 1, the flexible wiring board 11 includes a film 22 having a narrow band portion 22a and a protruding portion 22b protruding from a predetermined position on the lower side of the band portion 22a. Then, as shown in FIG. 2 (b), the right side power supply lines 45 and 46, the signal input terminal 42b, the cross wiring 14 and the input are provided at predetermined positions on the right side of the lower surface of the strip 22a of the film 22. Connection terminals 51 to 55 connected to the wiring 13 are provided. These connection terminals 51 to 55 are connected to connection terminals (not shown) provided on the lower surface of the protruding end of the protruding portion 22 b of the film 22, and routed on the lower surface of the strip 22 a and the protruding portion 22 b of the film 22. It is connected via a line 56.
[0018]
Connection terminals connected to power supply lines 45, 46, 47 (except for the power supply lines 45, 46 on the right side in FIG. 2A) are provided at other predetermined positions on the lower surface of the strip 22a of the film 22, respectively. 57, 58, and 59 are provided. The connection terminal 57 is connected to a lead wire 56 connected to the connection terminal 51 via a power supply relay wire 61 provided on the lower surface of the strip 22 a of the film 22. The left connection terminal 58 and the right connection terminal 59 are connected to each other via a power supply relay wire 62 provided on the lower surface of the strip 22 a of the film 22.
[0019]
Next, the lower surface of one end of the flexible wiring board 11 is bonded to the outside of the semiconductor chip mounting area 21 on the upper surface of the lower projecting portion 2a of the lower glass substrate 2 via an anisotropic conductive adhesive (not shown). A part of the state will be described. The connection terminal 53 of the flexible wiring board 11 is connected to the electrode connection terminal 42a in the semiconductor chip mounting area 21 on the right side of FIG. 2A via the signal input terminal 42b, and further the signal input relay wiring on the left side. It is connected to an electrode connection terminal 42a in the semiconductor chip mounting area 21 on the left side via 43, and further similarly to an electrode connection terminal 42a in the remaining two semiconductor chip mounting areas 21.
[0020]
The connection terminals 51 and 57 of the flexible wiring board 11 are connected to the power supply connection terminal 44 at the lowermost side in FIG. That is, the lowermost power supply connection terminal 44 in FIG. 4B in the semiconductor chip mounting area 21 on the right side in FIG. 2A is connected to the connection terminal 51 via the power supply line 45 and the connection terminal 51. Connected to the routing line 56. In FIG. 4B, the lowermost power supply connection terminal 44 in the remaining three semiconductor chip mounting areas 21 is connected to the connection terminal 51 via the power supply line 45, the connection terminal 57, and the power supply relay wiring 61. Connected to the routing line 56.
[0021]
The connection terminals 52 of the flexible wiring board 11 are connected to the remaining three power supply connection terminals 44 in the semiconductor chip mounting area 21 on the right side of FIG. 2A via the power supply line 46 on the right side of FIG. The remaining three power supply connection terminals 44 in the semiconductor chip mounting area 21 on the left side are further connected to the left power supply line 47, the connection terminal 59, the power supply relay wiring 62, the connection terminal 58, and the power supply line 46. , And similarly connected to the remaining three power supply connection terminals 44 in the remaining two semiconductor chip mounting areas 21. That is, the remaining three power supply connection terminals 44 in the four semiconductor chip mounting areas 21 are finally connected to the connection terminals 52 via the power supply line 46 and the connection terminals 52 on the right side of FIG. It is connected to the connected routing line 56.
[0022]
As described above, in this liquid crystal display device, the power supply lines 45, 46, 47 including the power supply connection terminals 44 are provided on the right side and in the vicinity of each of the four semiconductor chip mounting areas 21 of the liquid crystal display panel 1, and the flexible wiring On the lower surface of the band portion 22a of the film 22 of the substrate 11, adjacent ones (45, 45 and 46) of the power supply lines 45, 46 and 47 provided for each semiconductor chip mounting area 21 of the liquid crystal display panel 1 are provided. And 47) are provided. Thus, among the power supply connection terminals 44 provided on each right side in the four semiconductor chip mounting areas 21 of the liquid crystal display panel 1, the upper three power supply connection terminals 44 in FIG. 4B are connected in series. , And the remaining one power supply connection terminal 44 is connected in parallel. As a result, the connection terminals 57, 58, 59 and the power supply relay wires 61, 62 may be provided on the left side of the lower surface of the strip 22a of the film 22 of the flexible wiring board 11, and the width of the strip 22a of the film 22 is reduced. As a result, the area occupied by the flexible wiring board 11 can be reduced, and a simple structure with single-sided wiring can be achieved. As a result, the cost of the flexible wiring board 11 can be reduced.
[0023]
In this liquid crystal display device, the signal input relay wiring 43 is provided on the upper surface of the lower projecting portion 2a of the lower glass substrate 2 of the liquid crystal display panel 1. The signal input relay wiring 43 is mounted on a semiconductor chip. Since it is provided in the region 21, it is possible to prevent the width (width of the frame) of the lower protrusion 2 a on the lower glass substrate 2 from increasing.
[0024]
In the above embodiment, among the power supply connection terminals 44 provided on each right side in the four semiconductor chip mounting areas 21 of the liquid crystal display panel 1, the lowest power supply connection terminal 44 in FIG. Although the connection is made in parallel, the invention is not limited to this, and the power supply connection terminal 44 may be connected in series similarly to the remaining three power supply connection terminals 44. In the above-described embodiment, the signal input relay wiring 43 is provided on the liquid crystal display panel 1. However, the present invention is not limited to this. Like the power supply relay wirings 61 and 62, the film 22 of the flexible wiring board 11 is provided. May be provided on the lower surface of the band-shaped portion 22a.
[0025]
As described above, according to the present invention, the connection terminal connected to one end of the signal input wiring formed on the display panel and the connection terminal connected to one end of the power supply line are formed on the surface of the flexible wiring board corresponding to the display panel. The connection terminal and the power supply relay wiring for connecting the other end of the power supply line to one end of the adjacent power supply line are provided, so that the area occupied by the flexible wiring board can be reduced, and the single-sided wiring can be provided. And the cost of the flexible wiring board can be reduced.
[Brief description of the drawings]
FIG. 1 is a plan view of a liquid crystal display device according to an embodiment of the present invention.
2 (a) is an enlarged transmission plan view of a part of the lower right portion of the liquid crystal display panel shown in FIG. 1 in an exploded state, and FIG. 2 (b) is a portion corresponding to the area of the liquid crystal display panel in FIG. 2 (a). FIG. 4 is a transparent enlarged plan view of the flexible wiring board of FIG.
3A is an enlarged transmission plan view of the lower right part of the liquid crystal display panel shown in FIG. 1 in a partially disassembled state different from FIG. 2A, and FIG. 3B is a liquid crystal of FIG. 3A. FIG. 3 is a transparent enlarged plan view of a portion of a flexible wiring board corresponding to a region of a display panel.
FIG. 4A is an enlarged transparent plan view showing a terminal position of a semiconductor chip mounted on a semiconductor chip mounting area of the liquid crystal display panel shown in FIG. 2A, and FIG. FIG. 2 is an enlarged plan view of a semiconductor chip mounting area of the liquid crystal display panel shown in FIG.
FIG. 5 is a plan view showing an example of a conventional liquid crystal display device.
6A is an enlarged transmission plan view of a part of the lower right portion of the liquid crystal display panel shown in FIG. 5 in an exploded state, and FIG. 6B is a portion corresponding to the area of the liquid crystal display panel in FIG. FIG. 4 is a transparent enlarged plan view of the flexible wiring board of FIG.
7A is a transmission enlarged plan view showing a terminal position of a semiconductor chip mounted on a semiconductor chip mounting area of the liquid crystal display panel shown in FIG. 6A, and FIG. FIG. 2 is an enlarged plan view of a semiconductor chip mounting area of the liquid crystal display panel shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 2 Lower glass substrate 2a Projection 4 Semiconductor chip 11 Flexible wiring board 22 Film 22a Strip 22b Projection 41 Signal input wiring 42a Electrode connection terminal 42b Signal input terminal 43 Signal input relay wiring 44 Power supply connection Terminals 45, 46, 47 Power supply lines 51, 52, 53 Connection terminals 57, 58, 59 Connection terminals 61, 62 Relay wiring for power supply

Claims (1)

一辺部に配列された複数の半導体チップ搭載領域を有する表示パネルと、該表示パネルの前記各半導体チップ搭載領域に搭載された複数の半導体チップと、前記表示パネルの一辺部であって前記半導体チップ搭載領域の外側に接合されたフレキシブル配線基板とを備えた表示装置において、前記複数の半導体チップ搭載領域の中、一端側に対応する半導体チップ搭載領域に対応して、前記表示パネルの一辺部に沿って、信号入力用配線の一端部と電源線の一端部とを前記表示パネルの一辺部と垂直な方向に延出して配列し、他の半導体チップ搭載領域に対応して電源線の一端部を設け、前記信号入力用配線を、信号入力用配線の一端部から前記各半導体チップ搭載領域内を通過するように設け、前記各電源線を、前記電源線の一端部から前記半導体チップ搭載領域内に設けられた電源接続端子および該電源接続端子を通過して前記半導体チップ搭載領域外に延出された他端部を有する形状とし、前記フレキシブル配線基板の前記表示パネルと対応する面に、前記信号入力用配線の一端部に接続される接続端子、前記電源線の一端部に接続される接続端子および前記電源線の他端部と隣接の電源線の一端部とを接続する電源用中継配線を設けたことを特徴とする表示装置。A display panel having a plurality of semiconductor chip mounting areas arranged on one side, a plurality of semiconductor chips mounted on the respective semiconductor chip mounting areas of the display panel, and the semiconductor chip being one side of the display panel A display device comprising: a flexible wiring board bonded to an outer side of the mounting area ; wherein the plurality of semiconductor chip mounting areas correspond to a semiconductor chip mounting area corresponding to one end side; One end of the signal input wiring and one end of the power supply line are arranged so as to extend in a direction perpendicular to one side of the display panel, and one end of the power supply line corresponds to another semiconductor chip mounting area. The signal input wiring is provided so as to pass through the semiconductor chip mounting area from one end of the signal input wiring, and the power supply lines are provided from one end of the power supply line. A shape having a power supply connection terminal provided in the conductive chip mounting area and the other end extending outside the semiconductor chip mounting area passing through the power supply connection terminal and corresponding to the display panel of the flexible wiring board A connection terminal connected to one end of the signal input wiring, a connection terminal connected to one end of the power supply line, and the other end of the power supply line to one end of an adjacent power supply line A display device provided with a power supply relay wiring .
JP2000024872A 2000-02-02 2000-02-02 Display device Expired - Lifetime JP3580207B2 (en)

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Application Number Priority Date Filing Date Title
JP2000024872A JP3580207B2 (en) 2000-02-02 2000-02-02 Display device
US09/772,660 US6587177B2 (en) 2000-02-02 2001-01-30 Connection structure of display device with a plurality of IC chips mounted thereon and wiring board
KR1020010004457A KR20010078177A (en) 2000-02-02 2001-01-31 Display device
TW090102014A TW463140B (en) 2000-02-02 2001-02-01 Connection structure of display device with a plurality of IC chips mounted thereon and wiring board
CNB011026049A CN1162818C (en) 2000-02-02 2001-02-02 display device

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JP4826809B2 (en) * 2001-09-13 2011-11-30 セイコーエプソン株式会社 Organic EL display device and electronic device
JP4005410B2 (en) * 2002-05-15 2007-11-07 株式会社 日立ディスプレイズ Image display device
KR100920269B1 (en) 2002-12-31 2009-10-08 하이디스 테크놀로지 주식회사 Pad structure of drive IC package and panel
JP4190998B2 (en) * 2003-10-03 2008-12-03 三菱電機株式会社 Display device
KR20060104088A (en) 2005-03-29 2006-10-09 삼성전자주식회사 Circuit board of display device and display device including same
JP2010026168A (en) * 2008-07-17 2010-02-04 Toshiba Mobile Display Co Ltd Liquid crystal display
US9217888B2 (en) 2012-04-27 2015-12-22 Sharp Kabushiki Kaisha Display device
JP6539214B2 (en) 2016-01-19 2019-07-03 株式会社ジャパンディスプレイ Display with sensor
JP6797970B2 (en) * 2019-06-06 2020-12-09 株式会社ジャパンディスプレイ Display device
JP2021139937A (en) 2020-03-02 2021-09-16 シャープ株式会社 Display device
JP7051982B2 (en) * 2020-11-13 2022-04-11 株式会社ジャパンディスプレイ Display device

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