JP3580726B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device having an erase verify function.
[0002]
[Prior art]
In recent years, nonvolatile semiconductor memory devices have made remarkable progress, and power consumption has been reduced. An example of the nonvolatile semiconductor memory device is IEEE Technical Dig. of IEDM, pp. 921, 1994.
[0003]
FIG. 5 is a main block diagram of a conventional nonvolatile semiconductor memory device.
1 is a well, 2 is a main array in which a plurality of memory cells for storing data are formed in a matrix in the well 1, 3 is a row selection circuit for selecting a row of the memory array in a matrix, 4 is , A column selection circuit for selecting a column of the memory array in a matrix, and 5 (5-1 to 5-k) are blocks including the above-described components 1 to 4, respectively. Reference numeral 6 denotes a block selection circuit for selecting a predetermined block from the blocks 5, and reference numeral 7 denotes a power supply for applying a potential to the well 1 of the block 5 (5-1 to 5-k).
[0004]
FIG. 6 is an internal configuration diagram of the block 5 in FIG.
In the well 1, memory cells M (M00, M10,..., Mnm) are formed in a matrix of (n + 1) rows and (m + 1) columns. The source voltage of the memory cell (Mij) is supplied from the bit line BLj, and the drain voltage is supplied from the bit line MBLj + 1.
[0005]
Then, the gate potential is supplied from the word lines WL (WL0 to WLn). The word lines WL0 to WLn can be selected by the row selection circuit 3. For the bit lines BL (BL0 to BLm), transistors T (T00 to T0m) of a predetermined block selected by SG0 from the block selection circuit 6. Thereby, the source of the memory cell M (M00 to Mnm) is selected by applying the voltage of the bit line BL (BL0 to BLm). The well 1 is common to one block. The memory array configuration of one block includes (n + 1) × (m + 1) memory cells M00 to Mnm selected by (n + 1) word lines WL0 to WLn and (m + 1) bit lines BL0 to BLm. I have.
The data latch / sense circuit 11 and the output buffer 12 are connected in the direction of the bit line BL (BL0 to BLm) of the memory cell M (M00 to Mnm).
FIGS. 7 to 9 are diagrams for explaining the operating principles of erasing (erasing), writing (program), and erasing confirmation (erasing verify) of the nonvolatile semiconductor memory device.
FIG. 7 is a diagram illustrating an erase operation phenomenon of a memory cell of a nonvolatile semiconductor memory device.
In erasing the data of the memory cell, that is, in the operation of increasing the threshold value of the memory cell, the well (WELL) potential (−8 V), the source potential (−8 V), the drain potential (−8 V), This is performed by injecting electrons into the floating gate (FG) by a potential difference (18 V) created by the gate potential (10 V).
[0006]
FIG. 8 is a diagram for explaining a phenomenon of an erase verify operation after erasing a memory cell.
The erase verify operation is based on the well (WELL) potential (0 V), the source potential (1 V), the drain potential (0 V), and the gate potential (3 V). If the height is not high, a channel is formed between the source and the drain, and a current flows, so that it is determined that the erasure is insufficient. Further, the erasure operation is started, and this is repeated until the erasure is completed.
[0007]
FIG. 9 is a diagram illustrating a phenomenon during a write operation of a memory cell.
The write operation is performed by a potential difference (14 V) formed by the potential (0 V) of the well (WELL), the potential of the source (5 V), the potential of the drain (float), and the potential of the gate (-9 V). This is performed by extracting electrons from the FG to the source.
[0008]
FIG. 10 is a timing chart of the potentials of respective parts in the erase operation and the erase verify operation of the conventional nonvolatile semiconductor memory device.
When data is erased from the memory cell, that is, in the operation of increasing the threshold value of the memory cell, the well potential (−8 V), the source potential (−8 V), the drain potential (−8 V), and the gate potential (10 V) are set. Electrons are injected into the floating gate (FG) by a potential difference (18 V) created by these potentials and applied to the data, thereby erasing data.
At the time of erase verification, a well potential (0 V), a source potential (1 V), a drain potential (0 V), and a gate potential (3 V) are applied. If the threshold value of the memory cell is not sufficiently high, a channel is formed. A current flows between the source and the drain, and by detecting this current, it is determined that the erasure is insufficient. Further, the erasure operation is started, and this is repeated until the erasure is completed.
[0009]
[Problems to be solved by the invention]
By the way, in nonvolatile semiconductor memory devices in recent years, further reduction in power consumption has been demanded due to the evolution of portable devices and the like. In the above-described conventional technology, when it is determined that erasing is insufficient, the potential of a well becomes Since -8 V (at the time of erasing) and 0 V (at the time of erasing verification) are repeatedly supplied from the power supply, there is a problem that power consumption increases.
An object of the present invention is to provide a nonvolatile semiconductor memory device capable of performing an erase verify operation capable of suppressing power consumption.
[0010]
[Means for Solving the Problems]
In the nonvolatile semiconductor memory device according to the present invention, a memory cell array constituting a plurality of erase blocks in which a plurality of memory cells for storing data are formed in a matrix in a well, and a bit line of the memory cell array are formed. A column selecting means for selecting, a data latching and sensing means for performing a sensing operation and a rewriting operation provided in a bit line direction of the memory cell array, a row selecting means for selecting a word line of the memory cell array, and a connection to the well A first operation of writing data to the selected memory cell, a second operation of erasing the selected erasure block, and a erasing confirmation of the memory cell after the erasing operation. 3 and each function of the erase verify operation, and the well voltage of the memory cell supplied in the first erase operation is temporarily Storing the auxiliary capacitor, in the erasing operation of the second and subsequent, in which to perform an auxiliary supply of well voltage from the auxiliary capacitor.
[0011]
According to a second aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the memory cell array is a memory cell array of an EEPROM.
According to a third aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the erase block has a well formed for each block.
According to a fourth aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, a block selection circuit for selecting a predetermined block from among the plurality of erase blocks is further provided.
According to a fifth aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, a switching transistor is provided between the well and the auxiliary capacitor.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
(Example)
FIG. 1 is a block diagram showing one embodiment of the nonvolatile semiconductor memory device of the present invention. Components common to those of the conventional nonvolatile semiconductor memory device in FIG. 5 are denoted by the same reference numerals.
In this embodiment, the well 1, the main array 2, the row selection circuit 3, the column selection circuit 4, the block 5, the block selection circuit 6, and the power supply 7 are the same as those of the conventional nonvolatile semiconductor memory device. In addition, the difference is that a switching transistor (ST) 9 is provided between the well 1 and the power supply 7 and a switching transistor (ST) 10 is provided between the well 1 and the auxiliary capacitor 8. The switching transistor (ST) 9 is for setting the voltage of the well to -8 V at the time of erasing, and the switching transistor (ST) 10 is for switching the voltage of the well 1 to be stored in the auxiliary capacitor 8 after erasing. It is a transistor.
FIG. 2 is a circuit diagram near the auxiliary capacitor 8.
Further, the configuration of the main array 2 of the memory cells in the block 5 of the present embodiment is the same as that shown in FIG.
[0013]
FIG. 3 shows the magnitude of the voltage applied during the operation of the nonvolatile semiconductor memory device according to the present embodiment, and FIG. 4 is a time chart of the voltage applied at that time.
Next, an operation of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS.
First, regarding the erasing of the memory cells, the memory cells M to be selected correspond to one block, and all the word lines WL (WL0 to WLn) in the block 5 selected by the block selection circuit 6 are connected by the row selection circuit 3. As for the selection of bit lines, all the bit lines BL (BL0 to BLm) are selected by the column selection circuit 4, and the well 1 is supplied with the well voltage Vwell (= Vers) from the power supply 7.
[0014]
As shown in FIG. 3, 10 V is applied to the word lines WL (WL0 to WLm), and -8 V is applied to the bit lines BL (BL0 to BLn) and the well 1, as shown in FIG. Applied. Thereby, the floating gate FG of the memory cell is connected between the word line WL (WL0 to WLm), the bit line BL (BL0 to BLn), and the well 1.
10V-(-8V) = 18V
Is generated, electrons are injected into the floating gate FG, and the threshold rises to erase.
[0015]
After this erasing operation, the switching transistor 9 is turned off (eraseset = L) and the switching transistor 10 is turned on (eraseset = H) to discharge the -8V electric charge charged to the well 1 at the time of erasing and charge the auxiliary capacitor 8. . At this time, the voltage Vwell of the well and the voltage Vc charged in the auxiliary capacitor 8 become -8 (V) as shown in FIG. -8 (V) is a voltage at which the charge charged in the well 1 flows to the auxiliary capacitor 8 at the time of the erasing, and is balanced.
[0016]
After that, the switching transistor 9 is turned on (eraseset1 = H), the switching transistor 10 is turned off (eraseset2 = L), and 0 V for the erase verify operation is supplied from the power supply 7 to the well 1.
The erase verify of the memory cell M is performed for each word line WL (WL0 to WLn) after the erase. As shown in FIG. 3, 3 V is applied to the selected word line WLi. As illustrated in FIG. 4, for example, when the word line WL0 is selected, 1 V is applied to the bit line BL0, 0 V is applied to the bit line BL1, and 0 V is applied to the well 1 of the memory cell M00. .
[0017]
After the erase operation, when the threshold value of the memory cell M00 is sufficiently high, that is, when the erase operation is completed, no channel is formed in the memory cell M00, and no current flows. It is detected by the sense circuit section of the latch / sense circuit 11.
Then, after the erasing operation, when the threshold value of the memory cell M00 is not sufficiently high, that is, when the erasing is insufficient, a channel is formed between the source and the drain of the memory cell M00, and a current flows. When this is detected by the sense circuit section, the erase operation starts again.
[0018]
At the time of starting the second erase, the voltage supplied to the well 1 is as shown in the time chart of FIG.
First, the switching transistor 9 is turned off (eraseset1 = L) and the switching transistor 10 is turned on (eraset2 = H), and charging is performed from the auxiliary capacitor 8. At this time, the electric charge stored in the auxiliary capacitor 8 after the first erasure is charged into the well 1 again, and the voltage (Vwell) of the well 1 goes to the voltage (Vc) -8 (V) of the auxiliary capacitor 8. Decrease.
[0019]
At that time, since the charge amount is reduced by the capacity of the auxiliary capacitor 8, the well voltage (Vwell) does not reach -8 V as shown in FIG.
Thereafter, the switching transistor 9 is turned on (eraset1 = H) and the switching transistor 10 is turned off (eraset2 = L), and the power supply 7 charges the shortage necessary for the voltage (Vwell) of the well 1 to become −8V. .
This is repeated until the completion of erasure is detected by the sense circuit section of the data latch and sense circuit 11. As described above, when these operations are repeated a plurality of times, the power consumption from the power supply 7 supplied to the well 1 can be suppressed by the amount of charge from the auxiliary capacitor 8.
[0020]
In the above embodiment, the EEPROM is described as the nonvolatile semiconductor memory device. However, the present invention is not limited to this, and it is apparent that the present invention may be applied to any memory.
[0021]
【The invention's effect】
According to the nonvolatile semiconductor memory device of the present invention, at the time of erasing, the row selection circuit for selecting a word line selects all word lines, applies a voltage of 10 V, and the column selection circuit for selecting a bit line includes: All bit lines are selected, -8 V is applied, and -8 V is applied to the wells of the memory cells.
At the time of erase verify after the erase operation, the row selection circuit applies 3 V to the selected predetermined word line, and the column selection circuit applies 1 V to the source of the selected bit line and 0 V to the drain of the selected bit line. Is applied. At this time, -8 V applied in the erasing operation is charged to a separately provided auxiliary capacitor in the well of the memory cell. By setting the auxiliary capacitor to have the same capacity as the well of the memory cell, the amount of charge to be charged is divided. Then, in the next erasing operation, -8 V is supplied from the auxiliary capacitor to the well of the memory cell at the same time as the power supply for normal charging, whereby the charge from the power supply can be reduced.
[0022]
As described above, in the erase verify operation, when a plurality of erasures are performed, the row selection circuit that selects the word line in the first erasure applies 10 V to all the word lines, and the column selection circuit that selects the bit line is -8 V is applied to all the bit lines, -8 V is applied to the well of the memory cell, and the voltage supplied to the well is held in the auxiliary capacitor connected to the well. By performing the application from the auxiliary capacitor to the well, the power consumption due to the application from the power supply can be reduced.
[0023]
Further, in the case of a flash memory in which the memory cell array in the nonvolatile semiconductor memory device is electrically rewritable, an increase in the number of times of rewriting increases the possibility that the threshold value at the time of erasing may deviate from an expected value due to deterioration of an oxide film. Since the number of operations is increased, reduction of power consumption is more effective by applying the present invention.
[Brief description of the drawings]
FIG. 1 is a block diagram of one embodiment of a nonvolatile semiconductor memory device of the present invention.
FIG. 2 is a circuit diagram near an auxiliary capacitor in FIG. 1;
3 is a diagram showing the magnitude of a voltage applied to a memory cell during each operation of the nonvolatile semiconductor memory device in FIG. 1;
FIG. 4 is a time chart of the voltage of each part during the operation of the nonvolatile semiconductor memory device in FIG. 1;
FIG. 5 is a block diagram showing an outline of a conventional nonvolatile semiconductor memory device.
FIG. 6 is a diagram showing an internal configuration of a block in FIG. 5;
FIG. 7 is a diagram showing a state during an erasing operation of a memory cell of the nonvolatile semiconductor memory device.
FIG. 8 is a diagram showing a state during a memory cell erase verify operation of the nonvolatile semiconductor memory device;
FIG. 9 is a diagram showing a state during a write operation of a memory cell of the nonvolatile semiconductor memory device.
10 is a time chart of the voltage of each part during the operation of the nonvolatile semiconductor memory device of FIG. 5;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Well, 2 ... Main array, 3 ... Row selection circuit, 4 ... Column selection circuit, 5-1-5-k ... Block, 6 ... Block selection circuit, 7 ... Power supply, 8 ... Auxiliary capacitor, 9,10 ... Switching transistor, 11: data latch and sense circuit, 12: output buffer.

Claims (5)

A memory cell array constituting a plurality of erase blocks in which a plurality of memory cells for storing data are formed in a matrix in a well; column selecting means for selecting a bit line of the memory cell array; and a bit line of the memory cell array A data latch and sense means for performing a sense operation and a rewrite operation provided in a direction, a row selection means for selecting a word line of the memory cell array, and an auxiliary capacitor connected to the well; , A second operation for erasing the selected erase block, and a third erase verify operation for erasing confirmation of the memory cell after the erasing operation. The well voltage of the memory cell supplied in the erase operation is temporarily stored in the auxiliary capacitor, and the second and subsequent erase operations are performed. Sometimes, the non-volatile semiconductor memory device which is characterized in that an auxiliary supply of well voltage from the auxiliary capacitor. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell array is an EEPROM memory cell array. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a well is formed in each of said erase blocks. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a block selection circuit for selecting a predetermined block from among the plurality of erase blocks. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a switching transistor is provided between said well and said auxiliary capacitor.

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