JP3580956B2 - Reset signal generation circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a reset signal generation circuit that is built in an IC circuit (semiconductor integrated circuit) such as an LSI and resets an internal circuit when power is turned on.
[0002]
[Prior art]
As a reset signal generation circuit built in an IC circuit such as an LIS and used to reset an internal circuit when power is turned on, a circuit having a configuration shown in FIGS. 4 and 5, for example, has conventionally been used.
In the example of FIG. 4, the other end of the capacitor 1 connected to the power supply VDD is grounded via a MOSFET 2 whose gate is controlled by the power supply VDD and has an on-resistance of several MΩ, and the potential of the connection point between the capacitor 1 and the MOSFET 2 is As an input signal, the output of the inverter 4 sharing the capacitor 1 and the power supply VDD is supplied as a reset signal.
[0003]
When the power supply VDD is turned on, the potential at the connection point between the capacitor 1 and the MOSFET 2 rises to the power supply potential, and a low potential reset signal is output from the inverter 4. The potential at this connection point passes through the ON resistance of the MOSFET 2. When the capacitor 1 is charged, the voltage gradually decreases, and when the voltage drops to the threshold voltage of the input transistor of the inverter 4, the output of the inverter 4 is inverted to a high level, and the reset signal is turned off (high potential).
[0004]
Thus, when the power supply of the IC circuit is turned on, a reset signal having a pulse width proportional to a time constant determined by the capacitance of the capacitor 1 and the on-resistance of the MOSFET 2 is supplied.
FIG. 5 shows an example in which the capacitor 1 is connected to the ground side. After the power supply VDD is turned on, the capacitor 1 is gradually charged through the on-resistance of the MOSFET 3, so that the capacitance of the capacitor 1 and the on-resistance of the MOSFET 3 are similar to FIG. A reset signal (high potential) having a pulse width proportional to the determined time constant is obtained.
[0005]
[Problems to be solved by the invention]
However, when the circuit characteristics of the IC circuit itself, the capability of the power supply circuit when incorporated in the system, and the difference in the startup characteristics of the peripheral circuits are taken into consideration, the pulse width must be wide to some extent in order to surely reset the circuit. A reset signal may be required.
In such a case, in the above-described conventional example, it is necessary to increase the capacitance value of the capacitive element capacitor 1 and increase the on-resistance of the MOSFETs (2, 3). When the pulse width is increased by 10 times, the area of the capacitive element must be increased by 10 times in order to increase the capacitance by 10 times, and the gate length must be increased by 10 times in order to increase the on-resistance of the MOSFET by 10 times. In any case, there is a problem that the occupied area of the IC board increases.
[0006]
The present invention has been made in order to solve such a problem, and it is possible to supply a reset signal having a long pulse width in an IC circuit without greatly increasing the area occupied by a substrate and without consuming unnecessary current. It is another object of the present invention to provide a reset signal generating circuit with stable operation.
[0007]
[Means for Solving the Problems]
An input terminal according to the first embodiment of the present invention includes an inverter whose input terminal is grounded via a capacitor, and a charging unit that shares power with the inverter and charges the capacitor. In a reset signal generating circuit that generates a reset signal for turning on the power supply potential side from the output terminal, the charging means includes:
A high-resistance switching element that is controlled to be turned on at power-on,
A bipolar transistor having an emitter connected to a power supply, a collector grounded through the high-resistance switching element, and a current control element controlled by a collector-base voltage of the bipolar transistor;
The capacitor is charged by a base current of the bipolar transistor supplied through the current control element.
[0008]
Further, according to a second embodiment of the present invention, there is provided an inverter having an input terminal connected to a power supply via a capacitor, and charging means for sharing the power with the inverter and charging the capacitor. In a reset signal generating circuit that generates a reset signal for turning on the ground potential side from the output terminal of the inverter at the time,
A high-resistance switching element that is controlled to be turned on at power-on,
A bipolar transistor whose emitter is grounded and whose collector is connected to a power supply via the high-resistance switching element, and a current control element controlled by a collector-base voltage of the bipolar transistor;
The capacitor is charged by a base current of the bipolar transistor supplied through the current control element.
[0009]
The reset signal generating circuit according to the embodiments of the present invention is a second bipolar transistor in which the current control element has a base connected to the collector of the bipolar transistor and an emitter connected to the base of the bipolar transistor. The capacitor is charged by the collector current of the second bipolar transistor.
[0010]
The reset signal generating circuit according to the embodiments of the present invention is a MOSFET in which the current control element has a gate connected to the collector of the bipolar transistor and a source connected to the base of the bipolar transistor. The capacitor is charged by a drain current.
[0011]
Further, in the reset signal generation circuit according to these embodiments of the present invention, the control terminal of the high resistance switching element is connected to the output terminal of the inverter, and after the reset signal ends, the high resistance switching element is controlled to be off. It is characterized by that.
[0012]
The reset signal generating circuit according to the first embodiment of the present invention further includes a second switching element, and connects an input terminal of the inverter to the power supply through the second switching element. By connecting the control terminal of the second switching element to the output terminal of the inverter, it is possible to control the second switching element to be turned on after the reset signal ends and to fix the input potential of the inverter to the power supply potential side. Features.
[0013]
Furthermore, the reset signal generation circuit according to the second embodiment of the present invention further includes a second switching element, and grounds an input terminal of the inverter via the second switching element. By connecting the control terminal of the switching element to the output terminal of the inverter, the second switching element is controlled to be turned on after the end of the reset signal, and the input potential of the inverter is fixed to the ground potential side. I do.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing one embodiment of a reset signal generation circuit according to the present invention, and the same reference numerals as those in FIGS. 4 and 5 indicate the same or corresponding parts. This embodiment corresponds to the preceding example of FIG. 5, and generates a reset signal for turning on a high potential.
[0015]
As shown in FIG. 1, a reset signal generating circuit according to the present embodiment includes a MOSFET 2, a capacitor 1, an inverter 4, a bipolar transistor 10 having an emitter connected to a power supply VDD and a collector grounded via the MOSFET 2, and a bipolar transistor 10. A bipolar transistor 11 has an emitter connected to the base of the transistor 10, a base connected to the collector, and a collector grounded via the capacitor 1, and a potential at a connection point between the collector of the bipolar transistor 11 and the capacitor 1 is set to a power supply VDD. Is input to the common inverter 4 and a reset signal for turning on the high potential is supplied from the output terminal of the inverter 4.
[0016]
Further, in this embodiment, the gate of the MOSFET 2 is controlled by the output signal of the inverter 4, and in a steady state, the output signal is controlled to a low potential, that is, turned off when the reset signal is turned off. Furthermore, in this embodiment, in order to stabilize the input of the inverter 4 to a high potential in a steady state, the input terminal of the inverter 4 is connected to the power supply VDD via the MOSFET 12 which is controlled by the output signal and is turned on when the output signal is at a low potential. It is connected.
[0017]
The operation of the present embodiment will be described with reference to the time chart of FIG. 2 showing the relationship between the potential Vdd of the power supply VDD and the input signal potential V1 and the output signal of the inverter 4, that is, the potential Vr of the reset signal.
When the power supply VDD is at ground potential, all terminal voltages are at ground potential.
When the power supply VDD rises and power is supplied to the inverter 4, the output of the inverter 4 becomes high potential because the input terminal voltage V1 is at the ground potential, and the reset signal Vr rises.
[0018]
As a result, the MOSFET 2 is turned on, and the bipolar transistor 10 is regulated by the on-resistance Ron of the MOSFET 2 and the source-drain voltage, that is, the voltage obtained by subtracting the base-emitter voltage 2Vbe of the bipolar transistors 10 and 11 from the power supply potential Vdd. , A base current Ib of the bipolar transistor 10 corresponding to the collector current expressed by the following equation (1) flows through the collector of the bipolar transistor 11, and the input terminal voltage V1 of the inverter 4 is The capacitor 1 is charged until the voltage reaches the threshold voltage Vth of the transistor.
[0019]
Ib = (Vdd−2Vbe) / (Ron · Hfe) (1)
Here, Hfe is a common emitter current amplification factor of the bipolar transistor 10, and usually has a value of about 50 to 500.
[0020]
As can be seen from equation (1), in the present embodiment, the charging current of the capacitor can be reduced to 1 / Hfe as compared with the above-described prior art, so that a MOSFET having the same capacitance element and the same on-resistance is used. In this case, a reset signal having a pulse width of 50 to 500 times can be generated.
[0021]
When the capacitor 1 is charged and the input terminal voltage V1 reaches the threshold voltage Vth of the input transistor of the inverter 4, the reset signal potential Vr output from the inverter 4 is inverted, and the reset signal is turned off.
At this time, the MOSFET 2 controlled by the output of the inverter 4 is turned off, and the MOSFET 12 is turned on to cut off the collector currents of the bipolar transistors 10 and 11 to suppress unnecessary current consumption and to connect the input terminal of the inverter 4 to the power supply voltage Vdd. To prevent unnecessary rise of the reset signal.
[0022]
FIG. 3 shows a circuit diagram of another embodiment of the present invention in which the capacitor 1 is connected to the power supply VDD. This embodiment corresponds to the preceding example of FIG. 4 that generates a reset signal for turning on a low potential. However, the operation principle and effects are the same as those of the embodiment of FIG.
[0023]
In the embodiments of FIGS. 1 and 3, the power supply VDD is higher than the ground potential, the bipolar transistors 10 and 11 are PNP transistors, the MOSFET 2 is an n-type, the MOSFET 12 is a p-type, Although it has been described that the transistors 13 and 14 are NPN transistors, the MOSFET 3 is a p-type transistor, and the MOSFET 15 is an n-type transistor, even when the power supply potential VDD is lower than the ground potential, they are completely equivalent by inverting the type of each transistor. It goes without saying that a reset circuit having the above effect can be provided.
[0024]
In these embodiments, the base current of the bipolar transistor 10 or 13 is supplied to the capacitor 1 via the bipolar transistor 11 or 14. However, the bipolar transistors 11 and 14 for extracting the base current are, for example, Another current control element controlled by the collector-base voltage of the bipolar transistor 10 or 13 such as a MOSFET having a gate connected to the collector of the bipolar transistor 10 or 13 may be used.
[0025]
When it is not necessary to consider noise and current consumption, the main effects of the present invention can be realized even if the gates of the MOSFETs 2 and 3 are controlled by the power supply VDD and the ground potential, respectively.
[0026]
【The invention's effect】
As described above, according to the reset signal generation circuit at power-on according to the present invention, the capacitance element is charged with the base current of the bipolar transistor that controls the collector current by the MOSFET, so that it is smaller than the prior art. A reset signal having a large pulse width can be easily generated using a capacitance element having a capacitance and a MOSFET having an on-resistance value. By controlling the MOSFET with an output signal, circuit operation can be stabilized and power consumption can be reduced. As a result, reduction in size, high stability, and low power consumption of the IC circuit can be achieved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a time chart for explaining the operation of the embodiment of FIG. 1;
FIG. 3 is a circuit diagram showing another embodiment of the present invention.
FIG. 4 is a circuit diagram showing an example of a conventional reset signal generation circuit.
FIG. 5 is a circuit diagram showing another example of a conventional reset signal generation circuit.
[Explanation of symbols]
1 Capacitors 2, 3, 12, 15 MOSFET
4 Inverters 10, 11, 13, 14 Bipolar transistors

Claims (7)

An inverter whose input terminal is grounded via a capacitor; and a charging means which shares a power supply with the inverter and charges the capacitor, and which turns on a power supply potential side from an output terminal of the inverter when the power is turned on. In a reset signal generating circuit for generating a signal, the charging means includes:
A high-resistance switching element that is controlled to be turned on at power-on,
A bipolar transistor having an emitter connected to a power supply, a collector grounded through the high-resistance switching element, and a current control element controlled by a collector-base voltage of the bipolar transistor;
A reset signal generating circuit for charging the capacitor with a base current of the bipolar transistor supplied through the current control element. An inverter having an input terminal connected to a power supply via a capacitor, and charging means for sharing the power supply with the inverter and charging the capacitor, and turning on the ground potential side from the output terminal of the inverter when the power is turned on. In a reset signal generating circuit that generates a reset signal to
A high-resistance switching element that is controlled to be turned on at power-on,
A bipolar transistor having an emitter grounded and a collector connected to a power supply via the high-resistance switching element, and a current control element controlled by a collector-base voltage of the bipolar transistor;
A reset signal generating circuit for charging the capacitor with a base current of the bipolar transistor supplied through the current control element. The current control element is a second bipolar transistor having a base connected to the collector of the bipolar transistor and an emitter connected to the base of the bipolar transistor. The capacitor is charged by a collector current of the second bipolar transistor. The reset signal generation circuit according to claim 1 or 2, wherein 2. The current control element is a MOSFET having a gate connected to the collector of the bipolar transistor and a source connected to the base of the bipolar transistor, and the capacitor is charged by a drain current of the MOSFET. Or a reset signal generation circuit according to claim 2. The control terminal of the high-resistance switching element is connected to the output terminal of the inverter, and the high-resistance switching element is controlled to be turned off after a reset signal ends. Reset signal generation circuit. A second switching element, the input terminal of the inverter being connected to the power supply through the second switching element, and the control terminal of the second switching element being connected to the output terminal of the inverter; 2. The reset signal generation circuit according to claim 1, wherein the second switching element is controlled to be turned on after termination of the reset signal to fix the input potential of the inverter to the power supply potential. A resetting device that has a second switching element, grounds an input terminal of the inverter through the second switching element, and connects a control terminal of the second switching element to an output terminal of the inverter; 3. The reset signal generating circuit according to claim 2, wherein the second switching element is controlled to be turned on after the signal is completed, and the input potential of the inverter is fixed to the ground potential side.

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