JP3584757B2 - Waveform shaping device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a waveform shaping device for obtaining a low-voltage, high-frequency clock pulse having a 50% duty ratio.
[0002]
[Prior art]
A clock pulse with a duty of 50% is required for a microprocessor or a communication encoder / decoder for clock synchronous operation from the viewpoint of high-speed operation and ease of logic design.
[0003]
Conventionally, to obtain a clock pulse with a duty of 50%, a method of inputting a clock pulse output of a clock oscillator to a flip-flop circuit and dividing the frequency by 1/2, or integrating a duty ratio of the clock pulse output of the clock oscillator is used. A method of performing level conversion and performing negative feedback control on a threshold value of a clock oscillator using a differential amplifier is known.
[0004]
Obtaining a clock pulse having a 50% duty ratio is also described in, for example, JP-A-10-75461 and JP-A-7-30422.
[0005]
[Problems to be solved by the invention]
In the method of dividing the frequency by the flip-flop, both the clock oscillator and the flip-flop circuit have an operation frequency twice as high as the required clock pulse, so that the power consumption increases. If the required frequency of the clock pulse becomes 10 MHz to 1 GHz, Even if the power consumption is increased, it becomes difficult to obtain a pulse having an oscillation frequency twice as high as the above.
[0006]
Further, in the method of performing negative feedback control of the threshold value of the clock oscillator, it becomes difficult to accurately configure the differential amplifier when the frequency becomes as high as 1 GHz at a low voltage of about 1 V.
[0007]
In any case, the conventional technique has a problem that the duty of the low-voltage, high-frequency clock pulse cannot be accurately set to 50%.
[0008]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a waveform shaping circuit capable of accurately setting a duty to 50% even when a clock pulse has a low voltage and a high frequency.
[0009]
[Means for Solving the Problems]
A feature of the present invention resides in that a nonlinear limiter element for limiting the output amplitude to a positive or negative target is provided for input / output of an inverting amplifier (inverter amplifier) which is AC-coupled to a clock pulse generating source. The current limiting impedance is connected between the power supply side terminal and the power supply voltage bus and between the ground side terminal and the ground voltage bus.
[0010]
In the present invention, it is desirable to use an inverting amplifier having a high input impedance, a diode connected in anti-parallel as a nonlinear element, and a constant current circuit as a current limiting impedance.
[0011]
According to the present invention, since the output amplitude of the inverting amplifier that does not pass the DC component is limited so that the output amplitude becomes positive and negative, the threshold value of the output waveform (clock pulse waveform) of the inverting amplifier is always positive. Move to a level where the half cycle and the negative half cycle are equal. In addition, the output waveform of the inverting amplifier has gradients at the rise and fall due to the current-limiting impedance, and there is a rise time and a fall time. As a result, the clock pulse output waveform of the inverting amplifier based on the threshold value shifted so that the positive and negative half cycles are equalized is shaped into a waveform whose duty is closer to 50% than the input clock pulse waveform.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows an embodiment of the present invention.
[0013]
In FIG. 1, a clock pulse output from a clock oscillator 100 is input to a waveform shaping circuit 120a. Clock oscillator 100 is connected between bus 10V of power supply voltage Vcc and bus 10G of ground voltage GND to be supplied with power. The input side of the inverting amplifier 121 constituting the waveform shaping circuit 120a is connected to the clock oscillator 100 via the capacitor C21 which performs AC coupling. The inverting amplifier 121 has an amplification factor of -μ and a high input impedance. As the inverting amplifier 121, a CMOS inverter amplifier is used. A nonlinear limiter element NL20 for limiting positive and negative amplitudes is connected as a feedback element between the input and output of the inverting amplifier 121. As the non-linear limiter element NL20, an element in which diodes are connected in anti-parallel and utilizing the voltage at the bottom of the diodes is used. Assuming that the diodes connected in anti-parallel are D1 and D2, the characteristics are as shown in FIG. In FIG. 2, I on the vertical axis represents current, and V on the horizontal axis represents voltage. The power supply side terminal 12V of the inverting amplifier 121 is connected to the power supply bus 10V via the current limiting impedance Z21, and the ground side terminal 12G is connected to the ground bus 10G via the current limiting impedance Z22.
[0014]
As described above, the waveform shaping circuit 120a includes the inverting amplifier 121, the AC coupling capacitor C21, the nonlinear limiter element NL20, and the current limiting impedances Z21 and Z22.
[0015]
A plurality of such waveform shaping circuits 120 are connected in cascade, and a clock pulse is output from the output terminal 20 of the waveform shaping circuit 120n at the last stage.
[0016]
In this configuration, it is assumed that a clock pulse e0 having a level 1 whose duty ratio deviates from 50% from the clock oscillator 100 as shown by a dashed line in FIG. 3 is output.
[0017]
The amplitude of the clock pulse output from the inverting amplifier 121 is limited by the nonlinear limiter element NL20, and becomes a trapezoidal wave having an amplitude value of 2 Vd. Note that Vd is the oscillating layer voltage of the diode. The inverting amplifier 121 has a high input impedance, and the DC component of the clock pulse input from the clock oscillator 100 is removed by the capacitor C21. Therefore, the threshold value for the clock pulse waveform e0 output from the inverting amplifier 121 automatically shifts to level 2 indicated by a broken line in FIG. 3 so that the positive and negative waveform areas are equal. When the threshold level shifts from level 1 to level 2, the positive-side duty time increases from time t1 to time t2, and the duty ratio approaches 50%.
[0018]
When the waveform shaping circuits 120a to 120n are cascaded in a plurality of stages as in the embodiment of FIG. 1, the duty ratio can be made as close to 50% as possible. Normally, when the waveform shaping circuits 120a to 120n are cascaded in two or three stages, the duty ratio can be made 50%.
[0019]
FIG. 4 shows an example of a simulation result according to the present invention when the clock pulse is 1 V and 1 GHz.
[0020]
When the duty of the output clock pulse from the clock oscillator 100 is set to 42%, the waveform shaping circuit 120 in the first stage has 48.5%, the duty in the second stage is 49.5%, and the duty in the third stage is 50%.
[0021]
Usually, the required duty ratio is 50% ± 2% or less, and a clock pulse having a desired duty can be obtained in one or two stages of the waveform shaping circuit according to the present invention.
[0022]
It is clear from the characteristics of FIG. 4 that the waveform shaping circuit according to the present invention has a large effect of improving the duty ratio even in one stage, and it can be understood that even one stage is practically useful.
[0023]
FIG. 5 is a detailed circuit diagram showing an example of the embodiment of the present invention.
[0024]
In FIG. 5, a clock oscillator 100 is a ring counter composed of a plurality of inverting amplifiers (CMOS inverter amplifiers) AMP1 to AMPn and a plurality of constant current circuits CC31 to CC3n and CC11 to CC1n. The waveform shaping circuits 120a and 120b are cascaded in two stages, and use diodes D1 and D2 connected in anti-parallel as non-linear limiter elements of the waveform shaping circuit 120, and use constant current circuits CC21 and CC22 as current limiting impedance. . The clock pulse having a duty ratio of approximately 50% obtained from the second-stage waveform shaping circuit 120b is output from the output terminal 20 via the output inverting amplifier 125. CMOS inverter amplifiers are also used as the inverting amplifier 121 and the inverting amplifier 125 for output of the waveform shaping circuits 120a and 120b.
[0025]
The constant current circuits CC31 to CC3n and CC11 to CC1n of the clock oscillator 100 and the constant current circuits CC21 and CC22 of the waveform shaping circuits 120a and 120b are each configured by a MOS current mirror circuit. A control current is applied to these constant current circuits CC31 to CC3n, CC11 to CC1n, CC21, and CC22 from a current control terminal 150. When the control current applied to the current control terminal 150 is increased, the oscillating frequency of the clock oscillator 100 increases, and the impedance of the constant current circuits CC21 and CC22 acting as a current limiting impedance decreases.
[0026]
In the embodiment of FIG. 5, a clock pulse having a duty of 50% can be obtained from the output terminal 20 as described with reference to FIG. The simulation results shown in FIG. 4 are characteristics based on the circuit configuration shown in FIG.
[0027]
In the embodiment of FIG. 5, the control currents of the constant current circuits CC31 to CC3n and CC11 to CC1n of the clock oscillator 100 and the control currents of the constant current circuits CC21 and CC22 of the waveform shaping circuits 120a and 120b are controlled in an interlocked manner.
[0028]
When the control current of the constant current circuits CC21 and CC22 is increased, the current limiting impedance value is reduced, and the rising and falling slopes of the clock pulse are increased. On the other hand, the oscillation frequency of the clock oscillator 100 increases as the control current of the constant current circuits CC31 to CC3n and CC11 to CC1n increases.
[0029]
Therefore, as the clock pulse frequency of the clock oscillator 100 increases, the rising and falling gradients of the output clock pulses of the waveform shaping circuits 120a and 120b increase. The waveform shaping circuits 120a and 120b can keep the rise and fall times with respect to the pulse width at a predetermined ratio even if the frequency of the input clock pulse changes greatly. As a result, it is possible to accurately set the duty of the clock pulse of the broadband frequency to 50%.
[0030]
Next, FIGS. 6A to 6D show other examples of the nonlinear limiter element.
[0031]
FIG. 6A shows an example in which MOS diodes D11 and D21 are used as the nonlinear limiter elements. When the MOS diodes D11 and D21 are used, the constant current circuits CC21 and CC22 and the inverter amplifier can also be configured by MOS elements, so that there is an advantage that the configuration can be simplified and the amplitude limit value can be arbitrarily designed.
[0032]
FIG. 6B shows an example in which pn junction diodes D12 and D22 are used as nonlinear limiter elements. The use of the pn junction diodes D12 and D22 improves the positive and negative symmetry of the amplitude limit value.
[0033]
FIG. 6C shows an example in which MOS diodes D11 and D21 are used as non-linear limiter elements to form a source floor. In FIG. 6C, high-speed operation becomes possible in addition to the advantage of FIG.
[0034]
FIG. 6D shows an example in which bipolar followers D13 and D23 are used as nonlinear limiter elements to form an emitter follower. In FIG. 6D, the balance between positive and negative is improved, and high-speed operation is possible.
[0035]
FIG. 7 shows an application example in which the present invention is applied to a phase locked loop (PLL) which is a typical high frequency clock generating means.
[0036]
7, a phase comparator 700 for comparing the phase of a reference signal applied through an input terminal 10 with a feedback signal from a frequency divider 600, a charge pump 800 for converting a phase time difference into a voltage, a voltage-current (V / I) A closed loop control circuit including the converter 900, the current controlled oscillator (CCO) 100, the waveform shaping circuit 120 according to the present invention, and the frequency divider 600 is configured.
[0037]
The phase locked loop PLL shown in FIG. 7 can make the output frequency of the output terminal 20 equal to the frequency of the oscillator 100. Since this PLL does not require 1/2 frequency division, the power consumption of the oscillator 100, the output buffer amplifier 125, and the frequency divider 600, which consume a large amount of power, can be greatly reduced as compared with usual. Further, since it is not necessary to use a 1/2 frequency divider in the output stage, the duty ratio of the waveform at a high frequency is excellent, and the maximum usable frequency can be increased.
[0038]
FIG. 8 shows a configuration diagram of a microprocessor using the phase locked loop PLL of FIG. 7 using the waveform shaping circuit of the present invention.
[0039]
8, a microprocessor MPU 1000 includes a PLL 1001, a logic unit 1003, and an input / output signal interface circuit 1004. In such a microprocessor 1000 having a built-in PLL having a 50% duty waveform shaping circuit according to the present invention, the maximum frequency can be reduced as compared with a normal frequency-multiplied clock generation system, and a low-voltage circuit However, since it can operate, a microprocessor suitable for portable information and communication equipment requiring low-voltage / broadband operation can be realized.
[0040]
FIG. 9 shows a configuration in which the phase locked loop PLL of FIG. 7 using the waveform shaping circuit of the present invention is used in an optical communication (optical fiber communication) module.
[0041]
In FIG. 9, a PLL extracts a clock frequency component from a control-side PLL 1001 (PLL-1) of an output synchronization circuit FF2005 of an encoder 2003 on a transmitter side and a reception signal on a receive side to control the timing of a decoder 2004. Used as a generator PLL 1002 (PLL-2). When a PLL using the waveform shaping circuit according to the present invention is used as such an optical communication module 2000, the required maximum frequency of the oscillator 2003 can be reduced and the oscillator 2003 can operate at a low voltage, so that the power consumption of the optical communication module is reduced. In this case, the clock noise can be reduced and the S / N ratio on the receiving side can be improved.
[0042]
FIGS. 10 to 12 show examples of connection with various ring counters as desirable signal sources to the waveform shaping circuit 120 of the present invention.
[0043]
FIG. 10 shows a ring counter including differential amplifier stages Q31-Q41 and Q3n-Q4n having constant current circuits CC31-CC4n and diode clamps D11-D4n on the load side. The ring counter shown in FIG. 10 is suitable for high frequency and high withstand power noise.
[0044]
The oscillator shown in FIG. 11 controls the power supply voltage of the ring counter including the transistor pairs Q21-Q31-Q2n-Q3n via the source followers Q771-Q77n. Although the variable oscillator shown in FIG. 11 has the advantage of being able to oscillate at a high frequency, the threshold of the oscillation waveform changes instead of Vcc / 2, which makes it difficult to connect with a normal circuit, but the input of the waveform shaping circuit 120 of the present invention is AC-coupled. Is easy to combine. R5 is a resistor, and IV is a constant current circuit.
[0045]
FIG. 12 shows a configuration suitable for low-voltage operation. The inverter of the ring oscillator in FIG. 12 is composed of only two series MOS transistors with respect to the power supply voltage. Therefore, even at this low power supply voltage, the operating current density of the transistor can be designed to be relatively high, so that it is suitable for low voltage broadband operation, and can operate at 1 V and 1 GHz together with the low voltage and high frequency characteristics of the 50% duty waveform shaping circuit 120. It is.
[0046]
FIG. 13 shows another embodiment of the present invention. In the case where the rising and falling of the waveform of the oscillator 100 is fast, the input waveform of the waveform shaping circuit 120 is transformed into an arbitrary rising and falling waveform in advance by the resistor R11 and the capacitor C11. The following shows an example of inputting. By doing so, the rise and fall of the waveform are limited, and the operation of the waveform shaping circuit 120 to a 50% duty can be effectively operated even in a high-speed waveform.
[0047]
【The invention's effect】
As described above, according to the present invention, the duty can be accurately set to 50% even when the clock pulse has a low voltage and a high frequency.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing one embodiment of the present invention.
FIG. 2 is a characteristic diagram showing an example of a nonlinear limiter element used in the present invention.
FIG. 3 is a waveform chart for explaining the operation of the present invention.
FIG. 4 is a characteristic diagram showing a result of a duty ratio improvement according to the present invention.
FIG. 5 is a detailed circuit diagram showing one embodiment of the present invention.
FIG. 6 is a connection circuit diagram of various nonlinear limiter elements used in the present invention.
FIG. 7 is a configuration diagram of a phase locked loop (PLL) to which the present invention is applied.
FIG. 8 is a configuration diagram of a microprocessor using a PLL to which the present invention is applied.
FIG. 9 is a configuration diagram of an optical communication module using a PLL to which the present invention is applied.
FIG. 10 is a circuit diagram showing another example of the oscillator of the present invention.
FIG. 11 is a circuit diagram showing an example of a clock oscillator used in the present invention.
FIG. 12 is another example circuit diagram of a clock oscillator used in the present invention.
FIG. 13 is a connection circuit diagram with a clock oscillator to which the present invention is applied.
[Explanation of symbols]
100: Clock oscillator, 120: Waveform shaping circuit, 121: Inverting amplifier (inverter amplifier), C21: AC coupling capacitor, NL20: Nonlinear limiter element, D1, D2: Diode, Z21, Z22: Current limiting impedance.

Claims (5)

A clock oscillator for generating a clock pulse changes polarity, an inverting amplifier which inputs the clock pulse via the AC coupling capacitors provided between the input and output of the inverting amplifier, the positive-negative symmetrical output amplitude of said inverting amplifier A waveform, comprising: a nonlinear limiter element to be limited; and first and second current-limiting impedances respectively connected between a power supply terminal and a power supply bus of the inverting amplifier and between a ground terminal and a ground bus. Shaping equipment. A clock oscillator that generates a clock pulse that changes between positive and negative, a high input impedance inverting amplifier that inputs the clock pulse via an AC coupling capacitor, and a feedback element provided between the input and output of the inverting amplifier; A diode connected in anti-parallel to limit the output amplitude of the inverting amplifier to positive and negative symmetry, and first and second current-limiting impedances respectively connected to a power supply side terminal and a ground side terminal of the inverting amplifier to limit a supply current. A waveform shaping device characterized by the above-mentioned. A ring counter that generates a clock pulse that changes between positive and negative, an inverter amplifier that inputs the clock pulse via an AC coupling capacitor, and an input / output of the inverter amplifier, wherein the output amplitude of the inverter amplifier is symmetrical between positive and negative. A nonlinear limiter element to be limited, and first and second constant current circuits respectively connected between a power supply side terminal and a power supply bus of the inverter amplifier and between a ground side terminal and a ground bus and whose impedance value can be adjusted by a control current. A waveform shaping device comprising: A ring counter including a plurality of constant current circuits capable of changing the frequency of a clock pulse output by a control current, an inverter amplifier for inputting a positive / negative clock pulse of the ring counter via an AC coupling capacitor, and the inverter amplifier A diode provided as a feedback element between the input and output of the inverter amplifier and connected in anti-parallel to limit the output amplitude of the inverter amplifier to positive / negative symmetry, and between a power supply terminal and a power supply bus of the inverter amplifier and between a ground terminal and a ground bus. And a first and a second constant current circuit, each of which is capable of adjusting an impedance value by a control current, the constant current circuit constituting the ring counter, and the control current of the first and second constant current circuits. The waveform shaping device is characterized in that it is adjusted in conjunction with the waveform shaping. A waveform shaping device comprising a plurality of stages of the waveform shaping device according to claim 1 connected in cascade.

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