JP3585146B2 - ATM cellization / decellulation equipment - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an ATM (Asynchronous Transfer Mode) celling / decellularizing apparatus.
[0002]
This ATM cell forming / de-celling apparatus is an ATM cell which is also called a cladding method for dividing CBR (Constant Bit Rate) data handled in a synchronous transfer mode (STM) network so that the data can be transmitted to the ATM network. And a decellularization method of multiplexing ATM cells received from the ATM network with CBR data for transmission to the STM network.
[0003]
CBR data is a fixed-rate (CBR) service and a fixed-rate (VBR) service that are classified into two types from the viewpoint of communication speed in a service of B-ISDN (Broadband aspects of Integrated Service Digital Network). It is used to realize services.
[0004]
Fixed-rate service is communication in which information flows over a line at a constant rate. The N-ISDN (Narrowband aspects of ISDN) 64-1536 / 1920 / Kbps digital communication service is treated as a CBR service in the B-ISDN. Whether the specific service speed can be set arbitrarily such as 42.195 Kbps or a step such as an integral multiple of 64 Kbps is an issue for the future. It should be noted that the speed of a digital secondary group or the like provided on a conventional leased line basis is also treated as one of the steps of the CBR service.
[0005]
[Prior art]
In the conventional ATM cell system, CBR data sent from the STM network is temporarily stored in a cell buffer, and is read out by the ATM network. Further, when a CBR data frame or multi-frame is abnormal, an alarm signal indicating the abnormality is notified to the ATM network through a line different from the line on which the CBR data is transmitted.
[0006]
In the conventional ATM cell decellularization method, the STM network temporarily stores the ATM cells sent from the ATM network in a decellularization buffer and reads out the ATM cells in accordance with the STM cycle. Has been monitored to monitor the fluctuations of cells in the ATM network moving back and forth and the overflow / underflow of the decellularization buffer caused by disturbances in the STM network.
[0007]
An overflow is a state in which a cell exceeds the buffer storage capacity. In this case, a state occurs in which the cell is not stored in the buffer device, so that proper data cannot be read. An underflow is a state in which the buffer storage amount of a cell becomes zero. In this case, even though the cell is not stored in the buffer device, some data is read out, so that proper data reading is performed. I can't do it.
[0008]
[Problems to be solved by the invention]
By the way, in the above-mentioned conventional ATM cell conversion / de-cell conversion method, if a cycle abnormality occurs in a frame or multi-frame of CBR data, the cycle of writing CBR data to the cell conversion buffer changes, and the ATM cell from the cell conversion buffer changes. Read cycle changes. For this reason, the transmission interval of the ATM cell changes as compared with the normal case, and the data accumulation amount of the decellularization buffer on the receiving side of the ATM cell changes in the overflow or underflow direction, and can be absorbed by the decellularization buffer. There is a problem that the fluctuation absorption width is exceeded.
[0009]
Also, when data composed of CBR data frames or multiframes is out of synchronization, if ATM cells are converted and transmitted with a phase that remains out of synchronization, the out-of-synchronization at the time of the previous transmission is also performed on the receiving side of the ATM cells. As a result, a loss of synchronization occurs, and there is a problem that the decellularized buffer shifts in a buffer overflow or buffer underflow direction.
[0010]
Further, when the frame phase is abnormally restored due to a period abnormality, a case occurs in which the previous phase is different from the newly synchronized phase after the restoration. In this case, data is continuously read from the deceleration buffer with a new phase, but the counter value for counting and monitoring the accumulated data amount of the deceleration buffer is equal to the actually readable data amount. Differently, the remaining data amount does not match, and there is a problem that even if there is no more data to be read out in the decellularization buffer, decellularization continues without generating an underflow alarm.
[0011]
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been made in consideration of such a problem. Even if a data frame loses synchronization, an ATM cell conversion / decellation buffer can be prevented from overflowing / underflowing. It is intended to provide a decelerating device.
[0012]
[Means for Solving the Problems]
FIG. 1 shows a principle diagram of the present invention. The ATM cellization / decellulation apparatus shown in FIG. 1 includes a cellization buffer 1 for storing STM data transmitted from a synchronous transfer mode network, an abnormality monitoring means 2 for detecting an abnormality in a frame pulse cycle of STM data, Writing control means 4 for writing STM data to the cell buffer 1 in synchronization with the frame pulse; Input independently of frame pulse Reads ATM cells from cell buffer 1 in synchronization with cell frame pulse of ATM cells in asynchronous transfer mode network By doing When the abnormality monitoring unit 2 detects an abnormality, the reading control unit 5 reads the ATM cell at a normal reading interval, and when the abnormality monitoring unit 2 detects an abnormality, it reads from the cell buffer 1. Out Alarm cells to assigned ATM cells Thereby, an alarm cell is output at the same interval as a normal ATM cell. It is configured to include the abnormality processing means 3.
[0013]
According to such a configuration, even when the period of the frame pulse of the STM data is abnormal, it is possible to read the ATM cells at the normal reading interval, so that the overflow / underflow of the cell buffer 1 can be prevented. In addition, when a period abnormality occurs, an alarm cell for notifying the abnormality is mapped to the ATM cell, so that the period abnormality can be notified to the asynchronous transfer mode network.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of an ATM cell forming / de-celling apparatus according to the first embodiment of the present invention.
[0015]
In the ATM cell forming / de-cell forming apparatus shown in FIG. 2, reference numeral 1 denotes a cell buffer, 2 denotes a frame pulse period abnormality monitoring unit, 3 denotes an abnormality processing unit, 4 denotes a write control unit, and 5 denotes a read control unit.
[0016]
The cell buffer 1 temporarily stores the CBR data D1 transmitted from an STM network (not shown) in order to convert the data into ATM cells.
The frame pulse period abnormality monitoring unit 2 operates by a clock CK1 synchronized with the STM network, and monitors the period of the frame pulse FP1 of the CBR data D1 to monitor the period of the frame pulse FP1. When an abnormality is detected, an abnormality processing signal S1 is output to the abnormality processing unit 3, the write control unit 4, and the read control unit 5.
[0017]
When the abnormal processing signal S1 is not supplied, that is, when the period of the frame pulse FP1 is normal, the write control unit 4 generates a write address and a write enable signal synchronized with the frame pulse FP1 and the clock CK1, and supplies the write address and the write enable signal to the cell buffer 1. The CBR data D1 is controlled to be written, and a write completion signal S2 is output to the read control unit 5 each time the CBR data D1 is written. When the abnormal processing signal S1 is supplied, that is, when the cycle of the frame pulse FP1 is abnormal, the output of the write completion signal S2 to the read control unit 5 is not performed.
[0018]
When the abnormality processing signal S1 is not supplied, the read control unit 5 sends a read address and a read enable signal synchronized with a cell frame pulse FP2 of the ATM cell C1 and a clock CK2 synchronized with an ATM network (not shown) to a write completion signal S2. Is generated and the ATM cell C1 is controlled to be read from the celling buffer 1.
[0019]
When the abnormality processing signal S1 is supplied, the read address is set to a free run that does not depend on the write completion signal S2. In this case, although the address is not specified, the ATM cell C1 is read from the cell buffer 1 in the same manner as in the normal state, and transmitted to the ATM network.
[0020]
When the abnormal processing signal S1 is not supplied, the abnormal processing unit 3 only passes the ATM cell C1 read from the cell buffer 1, but when the abnormal processing signal S1 is supplied, an alarm is given to the payload of the ATM cell C1. Map and transmit cells.
[0021]
According to such a configuration, even when the period of the frame pulse FP1 of the CBR data D1 is abnormal, it is possible to output the ATM cell C1 at the normal phase before the abnormality, so that the overflow / underflow of the cell buffer 1 is possible. Flow can be prevented. In the event of an abnormality, it is possible to transfer an alarm cell for notifying the abnormality.
[0022]
Further, when the ATM cell receives the alarm cell, the read control unit 5 is forcibly stopped reading the ATM cell C1 from the cell buffer 1 so that the ATM cell receiving the ATM cell C1 is stopped. An underflow is forcibly generated in the decellularization buffer of the network, whereby an alarm transfer can be realized for the lower order.
[0023]
Next, an ATM cell forming / de-celling apparatus according to a second embodiment will be described with reference to FIG. However, in the second embodiment shown in FIG. 3, parts corresponding to the respective parts of the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.
[0024]
In FIG. 3, reference numeral 11 denotes a multiplex synchronization detection unit, and 12 denotes a write control unit, which includes a data bit address generation unit 13 and an address multiplexing unit 14. Reference numeral 15 denotes a read control unit.
[0025]
The multiplex synchronization detecting unit 11 performs a multi-frame configuration among data A and data B multiplexed in the CBR data D1 having different frame configurations according to the frame pulse FP1 of the CBR data D1 and the clock CK1 synchronized with the STM network. Of the data B, and outputs the frame phase information as a data B address AD1 to the data bit address generation unit 13, the address multiplexing unit 14, and the read control unit 15, as shown in FIG. In addition, a frame pattern detection determination unit 18, a synchronization protection stage number counter 19, a first frame counter 20, a second frame counter 21, a multiplex processing memory unit 22 using DPRAM (Dual Port RAM), and a selector ( SEL) 23.
[0026]
Here, with reference to FIG. 5, a description will be given of the ATM cell conversion / de-cell conversion which is the mutual conversion between the CBR data D1 in which the data A and the data B are multiplexed and the ATM cell C1.
[0027]
As shown in FIG. 5, one frame of the CBR data D1 is 125 μs, and k channels CH including a pair of data A and data B are multiplexed therein. That is, the first channel CH1 to the k-th channel CHk are multiplexed. The data A is composed of 125 μs frames, while the data B is multi-frame composed of 125 μs n frames.
[0028]
When such CBR data D1 is converted into ATM cells, k channels multiplexed 125 μs × n frames are considered as one unit, and the number of channels adapted to the speed are mapped into one ATM cell, and k channels are converted into j cells. It is divided into ATM cells # 1 to #j.
[0029]
In the case where the data A and the data B are converted into ATM cells, a plurality of channels are converted into one ATM cell. As shown in FIG. 6, data A is transmitted between time t5 and t10 and between time t10 and t15. As shown, n consecutive frames are mapped to one ATM cell. However, since data B forms a multiframe as indicated by CH1 to CHm, the multiframe synchronization of all the channels CH1 to CHm is The mapping is performed for each of the channels CH1 to CHm, and the phase is controlled and mapped.
[0030]
That is, n frames 1F to nF of CH1 from time t1 to t6, n frames 1F to nF of CH2 from time t2 to t7, n frames 1F to nF of CH3 from time t3 to t8,..., CHm Are mapped to the first cell # 1 in phase with the n frames 1F to nF between times t2 and t7, and between the n frames 1F to nF between times t6 and t11 of CH1 and between times t7 and t12 of CH2. The n frames 1F to nF, the n frames 1F to nF between times t8 to t13 of CH3, and the n frames 1F to nF between times t7 to t12 of CHm are mapped in phase to the second cell # 2. Thereafter, similarly, a process of sequentially mapping n frames 1F to nF of each of CH1 to CHm to cells is performed.
[0031]
In the description with reference to FIGS. 5 and 6, the description has been made with reference to the contents described in the earlier application, Japanese Patent Application No. 7-182864, “Asynchronous Transfer Device”.
Next, the multiplex synchronization detecting section 11 shown in FIG. 4 will be described.
[0032]
The frame pattern detection determination unit 18 detects a frame synchronization pattern of data B having a multi-frame configuration in the CBR data D1 according to the frame pulse FP1 and the clock CK1, and determines whether the synchronization pattern is normal or abnormal. .
[0033]
For example, when one of the multi-frames of the data B has an n-frame configuration, one cycle of the multi-frame is determined to be normal by detecting, for example, two consecutive synchronization patterns 1F to nF of the n-frame. "1" is output, and if 1F to nF are not detected twice consecutively, it is determined that there is an abnormality, and "0" is output at this time.
[0034]
The synchronization protection stage number counter 19 outputs a signal indicating multi-frame synchronization / out-of-synchronization by counting the number of synchronization protection stages according to the frame synchronization pattern detection determination result of the frame pattern detection determination unit 18.
[0035]
This is because a value obtained by counting "1" indicating the normality of the frame synchronization pattern is stored in the synchronization protection stage number count value storage area of the multiplex processing memory unit 22, and the value inputted next to the stored feedback count value is stored. The count value of “1” indicating normality is incremented, and this count value is overwritten in the synchronous protection stage number count value storage area of the memory unit 22.
[0036]
Thereafter, similarly, the count operation is performed until the count value becomes a predetermined number of synchronization protection stages, for example, “2”. When “0” indicating an abnormality (loss of synchronization) is input in the middle of the count, the count value is set to 0.
[0037]
Further, the synchronization protection stage number counter 19 outputs a first selection signal for selecting the first count value output from the first frame counter 20 to the selector 23 during the counting operation. When the state is restored to the second state, a second selection signal for selecting the second count value output from the second frame counter 21 instantaneously is output.
[0038]
The first and second frame counters 20 and 21 count the frame phase of a multi-frame. If the frame synchronization pattern detection determination result of the frame pattern detection determination unit 18 is “1” indicating normality, both counters 20 and 21 both count “1”, and the first frame counter 20 The first count value output from the counter 20 when the synchronizing signal is supplied is stored in the first count value storage area of the multiplex processing memory unit 22 via the selector 23 for selecting the first count value. Is incremented, and the count value is overwritten in the first count value storage area of the memory unit 22 via the selector 23.
[0039]
The second frame counter 21 stores the output second count value in the second count value storage area of the multiplex processing memory unit 22, and indicates the next input normality to the stored feedback count value. The count value of “1” is incremented, and this count value is overwritten in the second count value storage area of the memory unit 22.
[0040]
The first count value that is sequentially incremented and stored in the first count value storage area of the memory unit 22 is output as data B address B1 that is frame phase information.
[0041]
On the other hand, when the frame synchronization pattern detection determination result becomes “0” indicating an abnormality, that is, when an out-of-sync occurs, the first frame counter 20 continues counting with the previous phase, and the second frame counter 21 starts counting. This is for frame counting to synchronize with.
[0042]
For example, if an out-of-synchronization occurs at the timing indicated by time t1 in FIG. 7, the first frame counter 20 continues the counting operation with the previous frame phase, whereby the first count value becomes 1F, 2F,. Output is continued with the frame phase. On the other hand, the second frame counter 21 counts at the frame phase out of synchronization.
[0043]
At this time, since the first selection signal is still output from the synchronization protection stage number counter 19, the selector 23 selects the first count value, and the selected first count value is transmitted via the multiplex processing memory unit 22. It is output as data B address B1. Therefore, the data B address B1 is output at the frame phase before the synchronization is lost.
[0044]
Thereafter, when the first synchronization protection is taken by the synchronization protection stage number counter 19 at the timing shown by the time t2 and the second synchronization protection is taken by the timing shown by the time t3, the synchronization is detected and the synchronization is restored. At this time, the second selection signal is output from the synchronization protection stage number counter 19 to the selector 23 during the time t3 to t4.
[0045]
As a result, the selector 23 selects the second count value 1F and outputs it to the multiplex processing memory unit 22, so that the first count value storage area of the multiplex processing memory unit 22 is overwritten. The count value 1F is output as data B address B1. That is, a phase jump is performed at time t3.
[0046]
In addition, since the second count value 1F is also overwritten in the second count value storage area, the values in the first and second count value storage areas become the same value 1F. Therefore, both counters 20 and 21 perform counting based on the feedback second count value of the memory unit 22 having the same value, so that both count values become equal, and thereafter both counters 20 and 21 similarly perform the counting operation. Do.
[0047]
After time t4, the first selection signal is output again from the synchronization protection stage number counter 19, so that the first count value is output as the data B address B1.
As a result, the first count value having the same phase as the frame phase before the restoration is output from the multiplex processing memory unit 22 as the data B address B1 even after the restoration.
[0048]
Next, the data bit address generator 13 of the write controller 12 shown in FIG. 3 generates the data A address A1 from the CBR data D1 according to the frame pulse FP1 and the clock CK1, and outputs the data A1 to the address multiplexer 14. At the same time, when the data A address A1 is generated, the select signal S3 is output to the address multiplexing unit 14.
[0049]
The address multiplexing section 14 alternately multiplexes the data B address B1 and the data A address A1 output from the multiplex synchronization detecting section 11 and outputs the multiplexed address as a write address of the cell buffer 1, and a select signal S3. , The address A1 for data A is output to the cell buffer 1 when it is supplied, and the address B1 for data B is output when it is not supplied.
[0050]
As described above, the data A and the data B of the CBR data D1 are alternately written to the cell buffer 1 according to the data A address A1 and the data B address B1 output from the write control unit 12.
[0051]
The read control unit 15 outputs an address for reading the data A to the cell buffer 1 in response to the cell frame pulse FP2 and the clock CK2 synchronized with the ATM network, and also outputs the data B when the data B address B1 is input. An address for reading is output, and an ATM cell C1 in which data A and data B are converted into cells is output to the ATM network.
[0052]
According to the second embodiment described above, even when frame synchronization is lost, it is possible to map the CBR data D1 to the ATM cell C1 with the previous frame phase, and transfer the ATM cell with the frame phase before the synchronization is lost. it can.
[0053]
Therefore, when data composed of CBR data frames or multi-frames is out of synchronization as in the related art, if the ATM cells are transmitted with the phase kept out of synchronization and transmitted, the receiving side of the ATM cells also performs the previous transmission. An out-of-synchronization caused by an out-of-synchronization at the time does not occur, and the decellulation buffer does not shift in the buffer overflow or buffer underflow direction.
[0054]
Next, an ATM cell forming / de-celling apparatus according to a third embodiment will be described with reference to FIG. However, in the third embodiment shown in FIG. 8, parts corresponding to the respective parts of the second embodiment shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.
[0055]
8, reference numeral 30 denotes a decellularization buffer, 31 denotes a write address generation unit, 32 denotes a read address generation unit, 33 denotes a read phase latch unit, 34 denotes a capacity monitoring unit, and a two-input type counter control unit 35 and An up / down counter 36 is provided.
[0056]
The deceleration buffer 30 temporarily stores the ATM cell C1 transmitted from the ATM network in order to decelerate it into CBR data D1.
The write address generation unit 31 writes the cell enable signal S5, which is transmitted when the ATM cell C1 is proper, in response to the cell frame pulse FP2 of the ATM cell C1 and the clock CK2 synchronized with the ATM network. The write address W1 and the write enable signal WE at the same time as the write address W1 are output to the decellularization buffer 30, and the write enable signal WE is output to the counter control unit 35 of the capacity monitoring unit 34.
[0057]
When the write enable signal WE and the write address W1 are input to the decellularization buffer 30, the ATM cell C1 is written and stored in the storage area of the address. This writing is instantaneous.
[0058]
When the read enable signal S6 output from the up / down counter 36 of the capacity monitor 34 is input, the read address generator 32 receives the frame pulse (or multi-frame pulse) FP2 of the CBR data D1 and the clock CK1 synchronized with the STM network. And outputs the address of data A described in the second embodiment in response to the data B. When the address B1 for data B is output from the multiplex synchronization detection unit 11 described in the second embodiment, An address B1 is output, and both output addresses are output as read addresses R1 to the decellularization buffer 30. At the same time, a read enable signal RE is output, and the read enable signal RE is output to the counter control unit 35 and the read phase latch. This is output to the unit 33.
[0059]
When read enable signal RE and read address R1 are input to decellularization buffer 30, data A and data B of the ATM cell stored in the storage area of the address are multiplexed and output to the STM network as CBR data D1. It has become so.
[0060]
The time required to read the CBR data D1 from the decellularization buffer 30 requires a predetermined time while the time required to write the ATM cell C1 is instantaneous.
The capacity monitoring unit 34 monitors the storage capacity of the deceleration buffer 30, and the counter control unit 35 of this component counts up / down counter 36 every time only the write enable signal WE is supplied. Each time only the read enable signal RE is supplied, the value is counted down by a predetermined value, and the count is set to an uncounted state when both the write enable signal WE and the read enable signal RE are input or when both are not input. The control is performed.
[0061]
In the up / down counter 36, a count value corresponding to the number of storage cells to be monitored in the decellularization buffer 30 is set in advance, and when the count value reaches the set count value, the read enable signal S6 is output to the read address generation unit 32. I do.
[0062]
As the set count value, for example, since one cell has 48 bytes, 48 counts for one cell are set, and one count value corresponds to one byte.
[0063]
The read phase latch unit 33 compares the phase of the read enable signal RE having the same phase as the read address R1 with the phase of the data B address B1, and when both phases do not match, that is, the data B address B1 is in the second embodiment. As described in the embodiment, when the phase jump occurs when the phase synchronization is restored, a countdown enable signal S7 for clearing the up / down counter 36 is output. At the time of this clearing, the CBR data D1 stored in the deceleration buffer 30 is discarded.
[0064]
The operation of the third embodiment having such a configuration will be described with reference to FIG.
Assume that the initialization of the deceleration buffer 30 is completed between times t0 and t1 shown in FIG. 9 and that the first cell 1C is written into the deceleration buffer 30 at time t1. At this time, the up / down counter 36 counts up under the control of the counter control unit 35 according to the supply of the write enable signal WE.
[0065]
As a result, when the count value of the counter 36 becomes equal to the set count value of 48, the read enable signal S6 is output to the read address generation unit 32, and the read address R1 is sent to the decellularization buffer 30, and as shown at time t2. Of the cell 1C (CBR data D1) written to the memory cell is started.
[0066]
During this reading, the second cell 2C is written into the decellularization buffer 30 as shown at time t3, and the reading of the first cell 1C is completed as shown at time t4, and the reading of cell 2C is stopped. Then, during the reading, the third cell 3C is written into the decellularization buffer 30 as shown at time t5.
[0067]
Here, if there is a phase jump, the phase of the data B address B1 output from the multiplex synchronization detecting section 11 changes, so that the read phase latch section 33 outputs the data B address B1 and the read enable signal RE. , A countdown enable signal S7 is output to the up / down counter 36. As a result, the counter 36 is cleared as shown at time t6, and the cell 3C stored in the decellularization buffer 30 is Discarded.
[0068]
Thereafter, when the fourth cell 1C is written at time t7, the up / down counter 36 counts up. When the count value of the counter 36 becomes equal to the set count value of 48, the read enable signal S6 is output. The read address R1 is output to the read address generation unit 32, and the read address R1 is transmitted to the decellularization buffer 30, and reading of the written cell 4C is started as shown at time t8. Thereafter, processing is performed in the same manner as described above.
[0069]
According to the third embodiment described above, a period abnormality of the frame phase of the CBR data D1 occurs, the frame is restored again, and a case (phase jump) in which the previous phase is different from the newly synchronized phase after the restoration occurs. In such a case, data is read continuously from the deceleration buffer with a new phase as in the past, and the counter value for counting and monitoring the amount of data stored in the deceleration buffer can be actually read. Therefore, even if there is no data to be read out in the decellularization buffer, the decellularization will not be continued without generating an underflow alarm even if there is no data to be read out.
[0070]
That is, it is possible to prevent reading even when data does not exist in the decellularization buffer, and to eliminate the transition in the buffer underflow direction.
Further, in the configuration of the third embodiment shown in FIG. 8, when a phase jump occurs, the up / down counter 36 supplied with the countdown enable signal S7 output from the read-out phase latch unit 33 sets the up / down counter 36 at the time of recovery from the previous phase. The count value corresponding to the number of cell bytes of the phase difference is down-counted, and only the remainder of the cell being read at this time is discarded from the decellularization buffer 30.
[0071]
That is, as shown in FIG. 10 similar to FIG. 9 from time t0 to t5, when there is a phase jump at time t6, the up / down counter 36 to which the countdown enable signal S7 has been input is set to the position indicated by the reference numeral 38. The count value corresponding to the cell byte number of the phase and the phase difference at the time of restoration is down-counted, and the remaining cell 2C being read out in the decellularization buffer 30 is discarded. As a result, as shown at time t6, the cell 3C is read.
[0072]
Therefore, even if a phase jump occurs, the cells stored in the decellularization buffer 30 can be decellularized without being discarded.
[0073]
【The invention's effect】
As described above, according to the ATM cell forming / de-celling apparatus of the present invention, even if the data frame is out of synchronization, the ATM cell forming / de-celling buffer can be prevented from overflowing / underflowing. There is.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a block diagram of an ATM cell forming / de-celling apparatus according to a first embodiment of the present invention.
FIG. 3 is a block diagram of an ATM cell forming / de-celling apparatus according to a second embodiment of the present invention.
FIG. 4 is a block diagram of a multiplex synchronization detecting unit shown in FIG. 3;
FIG. 5 is an explanatory diagram of conversion between ATM cell conversion and decellularization.
FIG. 6 is an explanatory diagram of converting data A and B in CBR data into ATM cells.
FIG. 7 is an explanatory diagram of an operation of the multiplex synchronization detecting unit shown in FIG. 3 when synchronization is restored.
FIG. 8 is a block diagram of an ATM cell forming / de-celling apparatus according to a third embodiment of the present invention.
FIG. 9 is a diagram illustrating the operation of the ATM cell forming / de-celling apparatus shown in FIG. 8;
FIG. 10 is another operation explanatory view of the ATM cell forming / de-celling apparatus shown in FIG. 8;
[Explanation of symbols]
1 Cellular buffer
2 Abnormality monitoring means
3 Error handling means
4 Write control means
5 Read control means

Claims (3)

A cell buffer for storing STM data transmitted from the synchronous transfer mode network;
Detects multi-frame synchronization and out-of-synchronization of the first data of the multi-frame configuration included in the STM data, outputs the first data write address in the same phase as in the previous synchronization at the out-of-synchronization, and recovers from the out-of-synchronization to synchronization Means for outputting the first data write address at the phase at the time of recovery,
Write control means for writing the STM data by alternately outputting the first data write address and the write address of second data other than the first data included in the STM data to the cell buffer; When,
When the first data write address is input, the first data read address is output to the cell buffer in synchronization with the cell frame pulse of the ATM cell in the asynchronous transfer mode network. Read-out control means for reading out the ATM cell in which the first and second data are arranged from the cell buffer by outputting the second data read address in synchronization with the cell frame pulse. Conversion / deceleration equipment. A decellularization buffer for storing ATM cells transmitted from the asynchronous transfer mode network;
Writing control means for writing the ATM cell to the decellularization buffer in synchronization with a cell frame pulse of the ATM cell of the asynchronous transfer mode network;
When the read enable signal is supplied, the first data read address is output in synchronization with the frame pulse of the STM data in the synchronous transfer mode network when the first data address is input, and the frame pulse is output when the first data address is not input. Read control means for multiplexing the first data of the multi-frame configuration and the second data other than the first data from the decellularization buffer and outputting the same as STM data by outputting the second data read address in synchronization with ,
It counts up when only the write enable signal is supplied at the time of writing the ATM cell, counts down when the read enable signal is supplied at the time of reading the STM data, and when both the write and read enable signals are input or not input. A capacity monitoring unit that outputs the read permission signal when it is in an uncounted state and counts up to a count value corresponding to a predetermined capacity of the deceleration buffer;
Detects multi-frame synchronization and loss of synchronization of the first data included in the STM data, outputs the first data address in the same phase as at the time of pre-synchronization at the time of loss of synchronization, and recovers the data when synchronization is restored from the loss of synchronization. Multiplex synchronization detecting means for outputting the first data address at the phase of
Read phase latch means for outputting a count control signal for clearing the count value of the capacity monitoring means when the phase at the time of restoration of the first data address is different from the phase of the read enable signal;
An ATM cell forming / de-celling apparatus characterized in that when the count value is cleared by the count control signal, the stored ATM cells in the de-cell forming buffer are discarded. The count control signal is used to down-count the count value of the capacity monitoring means corresponding to the deceleration buffer capacity of the phase difference between before and after the restoration indicated by the first data address. 3. The apparatus according to claim 2, wherein only the remaining ATM cells being read are discarded.

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