JP3586344B2 - Display device - Google Patents

Description

[0001]
Field of the Invention
The present invention relates to an electronic camera, and more particularly to an imaging device for displaying a color image obtained by a solid-state imaging device by a liquid crystal display device.
[0002]
[Prior Art]
2. Description of the Related Art Conventionally, as an electronic camera, one configured to display a color image obtained by a solid-state imaging device by a liquid crystal display device is known.
[0003]
On the other hand, a delta arrangement filter is known as a color filter provided in a liquid crystal display element used for a monitor device or the like. This filter is configured such that red (R), green (G) and blue (B) color filter elements are disposed at each vertex of a triangle, and is horizontal in the image displayed by the liquid crystal display element. There is an advantage that the resolution is high with respect to the direction, vertical direction and oblique direction.
[0004]
[Problems to be solved by the invention]
There are no solid-state imaging devices provided with color filters of the delta arrangement conventionally, and as the color filters, magenta (Mg), clean (G), yellow (Ye) and yellow (Ye) which are arranged in a grid according to the arrangement of photodiodes A complementary color filter consisting of cyan (Cy) is used. However, when trying to display a color image obtained by a solid-state image sensor having such a complementary color filter with a liquid crystal display element provided with a delta-arranged color filter, the photodiodes of the solid-state image sensor and the dots of the liquid crystal display element In order not to correspond to each other, it is necessary to provide a circuit for performing complementary color-primary color conversion and the like. For this reason, there arises a problem that the circuit scale in the electronic camera is increased and the cost is increased.
[0005]
An object of the present invention is to provide a display device and an imaging device which do not have to increase the size of a circuit in an electronic camera and can suppress the cost.
[0006]
[Means for Solving the Problems]
The display device according to the present invention comprises a display element provided with a first color filter in which three different color filter elements are arranged on each dot according to a delta arrangement, and an integer multiple of the number of dots arranged in a grid. And a solid-state imaging device provided with a second color filter in which any one of the color filter elements of the same type as the display element is disposed on the pixel, the color filter of the second color filter The color of the element is characterized in that it is the same in adjacent two pixels, and the same as the color of the color filter element provided in the dot corresponding to the middle point of these two pixels.
[0007]
The display element is, for example, a liquid crystal display element.
The first and second color filters comprise, for example, color filter elements of three primary colors of red, green and blue.
[0008]
Two adjacent pixels may be disposed along the vertical direction on the solid-state imaging device, or may be disposed along the horizontal direction. When these two pixels are arranged in the horizontal direction, two pixels on the first horizontal line and two pixels on the second horizontal line adjacent to the first horizontal line on the solid-state imaging device. And are configured to be offset by one pixel in the horizontal direction.
[0009]
On the solid-state imaging device, two pixels corresponding to each dot on the first horizontal row of the liquid crystal display device are disposed along the vertical direction, and on the second horizontal row adjacent to the first horizontal row Two pixels corresponding to each dot may be disposed along the horizontal direction. In this configuration, the second horizontal row comprises a first horizontal line and a second horizontal line adjacent thereto, the two pixels on the first horizontal line and two pixels on the second horizontal line. And may be shifted by one pixel in the horizontal direction.
[0010]
Two adjacent pixels may be disposed along the oblique direction on the solid-state imaging device. The adjacent two pixels may be disposed along the horizontal direction and the vertical direction on the solid-state imaging device.
[0011]
An imaging device according to the present invention includes an imaging element having light receiving pixels arranged in a grid, and a color filter provided on the light receiving pixel and including three different color filter elements, and a plurality of adjacent light receiving pixels Are provided with color filter elements of the same color, the color of the plurality of light-receiving pixels regularly changing along the horizontally extending row, and the same in the first row and the second row adjacent to this row A plurality of light receiving pixels provided with color filter elements of color are characterized by being shifted by at least one pixel in the horizontal direction.
[0012]
The row is formed by one row or two rows of light receiving pixels extending in the horizontal direction. The colors of the three different color filter elements are preferably the three primary colors red, green and blue.
[0013]
The imaging device of the present invention preferably includes pixel signal addition means for generating a display signal of one dot by adding pixel signals obtained from light receiving pixels provided with adjacent color filters of the same color. .
[0014]
The pixel signal adding means is, for example, a charge-voltage conversion capacitor connected to a horizontal transfer CCD, a vertical transfer CCD, or a horizontal transfer CCD.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a circuit configuration of an electronic camera provided with an imaging device according to a first embodiment of the present invention.
[0016]
An infrared cut filter 13 and an optical low pass filter 14 are provided between the imaging optical system 11 and the solid state imaging device (CCD) 12. A second color filter to be described later is provided on the light receiving surface of the CCD 12. The CCD 12 is a two-line readout type / all pixel independent readout type. That is, each pixel signal generated in the photodiode is transferred to the horizontal transfer CCD without being added mutually in the vertical transfer CCD, and pixel signals of two horizontal lines are simultaneously output from the CCD 12. The CCD 12 is driven by the CCD driver 15, whereby the pixel signal is read from the CCD 12 and input to the signal processing circuit 16. The CCD driver 15 operates based on the CCD driving timing signal etc. generated by the CCD timing signal generation circuit 31, and the CCD timing signal generation circuit 31 based on the horizontal and vertical synchronization signals output from the synchronization signal generation circuit 32. , Generate timing signals for driving the CCD, and the like.
[0017]
The signal processing circuit 16 includes first and second correlated double sampling (CDS) circuits 16a and 16b, a switch 16c, and an amplifier circuit 16d. Among the pixel signals of two horizontal lines output from the CCD 12, the pixel signal of the first horizontal line is input to the first CDS circuit 16a, and the pixel signal of the second horizontal line is input to the second CDS circuit 16b. It is input. The pixel signal subjected to the processing of correlated double sampling in the CDS circuits 16a and 16b is input to the amplifier circuit 16d via the switch 16c. The switch 16c is switched by a system control circuit 17 having a computer, whereby one of the first and second CDS circuits 16a and 16b is connected to the amplifier circuit 16d.
[0018]
The pixel signal output from the signal processing circuit 16, that is, the amplifier circuit 16 d is converted into a digital signal by the A / D converter 18, temporarily stored in the RAM 19, and then stored in the non-volatile memory 21. The address control in the RAM 19 and the non-volatile memory 21 is performed by the address controller 22 that operates based on the control of the system control circuit 17. The address controller 22 operates based on the synchronization signal output from the synchronization signal generation circuit 32.
[0019]
An analog pixel signal output from the signal processing circuit 16 is directly supplied to the switch 23, while a pixel signal stored in the non-volatile memory 21 is supplied to the switch 23 via the RAM 19 and the D / A converter 27. Be done. The output terminals of the switch 23 are connected to the first to third white balance adjustment circuits 24a, 24b and 24c, and the output terminals of the white balance adjustment circuits 24a, 24b and 24c are connected to the LCD driver 25. That is, the pixel signal output from the signal processing circuit 16 and the pixel signal stored in the non-volatile memory 21 can be supplied to the liquid crystal display element 26 via the LCD driver 25.
[0020]
The switch 23 is switched based on the control of the system control circuit 17, and when the pixel signal output from the signal processing circuit 16 is transferred to the liquid crystal display element 26, the switch 23 is switched to the signal processing circuit 16 side and stored in the non-volatile memory 21. When the pixel signal is transferred to the liquid crystal display element 26, it is switched to the D / A converter 27 side. The first to third white balance adjusting circuits 24a, 24b and 24c are provided to adjust gains for color components of red (R), green (G) and blue (B), respectively. The pixel signals output from the first to third white balance adjustment circuits 24 a, 24 b and 24 c are input to the liquid crystal display element 26 via the LCD driver 25. The liquid crystal display element 26 has a first color filter to be described later, and is controlled based on the horizontal synchronization signal and the vertical synchronization signal output from the LCD timing signal generation circuit 28, whereby a color image is displayed on the liquid crystal display element 26. Displayed on the screen of. The LCD timing signal generation circuit 28 operates based on the synchronization signal output from the synchronization signal generation circuit 32.
[0021]
FIG. 2 shows the arrangement of the color filter elements of the first color filter 51 provided in the liquid crystal display device 26 and the arrangement of the color filter elements of the second color filter 52 provided in the CCD 12.
[0022]
As shown in this figure, the first color filter 51 is configured by arranging color filter elements of three primary colors on each dot according to the delta arrangement. That is, in the first horizontal row A1, color filter elements are disposed in the order of G, R, and B from left to right. In the second horizontal row A2 adjacent to the lower side of the first horizontal row A1, B at a position corresponding to G and R of the first horizontal row A1, and R and B of the first horizontal row A1 G is disposed at a position corresponding to the gap, and R is disposed at a position corresponding to B and G in the first horizontal row A1. In the first horizontal row and the second horizontal row, the color filter elements are shifted in the horizontal direction by one and a half (1.5 dots).
[0023]
On the other hand, in the CCD 12, photodiodes arranged in a lattice form correspond to pixels. That is, these photodiodes are two-dimensionally orthogonally arranged in the horizontal and vertical directions, and are not arranged in accordance with the delta arrangement as in the filter 51.
[0024]
The number of pixels of the CCD 12 is about twice the number of dots of the liquid crystal display element 26 (meaning the display area of the minimum unit corresponding to one cell of the color filter). Above each pixel or photodiode, one of the three primary color filter elements is disposed. In the first and second horizontal lines B1 and B2, color filter elements are disposed in the order of G, R and B from left to right. In the third horizontal line B3, in the order of R, G, G, B, B, R from left to right, and in the fourth horizontal line B4, in the order from left to right, B, B, R, R , G, and G are arranged in this order.
[0025]
In the CCD 12, the first horizontal row A1 of the liquid crystal display element 26 corresponds to the first horizontal line B1 and the second horizontal line B2 adjacent thereto, and the second horizontal row A2 of the liquid crystal display element 26 is the third. , And the fourth horizontal line B4 adjacent thereto.
[0026]
The color of the color filter element of the second color filter 52 is the same in adjacent two pixels. For example, in the first and second horizontal lines B1 and B2, the color filter elements of two pixels indicated by code P1 are both G, the color elements of two pixels indicated by code P2 are both R, and the color elements of two pixels indicated by code P3 Are both B. In the third horizontal line B3, the color filter elements of the two pixels indicated by the code P4 are both G, and the color elements of the two pixels indicated by the code P5 are both B. In the fourth horizontal line B4, the color filter elements of the two pixels indicated by the code P6 are both B, and the color elements of the two pixels indicated by the code P7 are both R.
[0027]
The dots Q1 on the first horizontal row A1 of the liquid crystal display element 26 correspond to the pixels P1 on the first and second horizontal lines B1 and B2 of the CCD 12. Similarly, the dots Q2 on the first horizontal row A1 correspond to the pixels P2 on the first and second horizontal lines B1 and B2 of the CCD 12. That is, on the CCD 12, two pixels corresponding to each dot on the first horizontal row A1 are disposed along the vertical direction. Further, on the CCD 12, one of the two pixels corresponding to each dot on the first horizontal row A1 is included in the first horizontal line B1, and the other of the two pixels is included in the second horizontal line B2.
[0028]
On the other hand, the dot Q4 on the second horizontal row A2 of the liquid crystal display element 26 corresponds to two pixels P4 on the third horizontal line B3 of the CCD 12, and the dot Q5 on the second horizontal row A2 is It corresponds to two pixels P5 on the third horizontal line B3. Similarly, the dot Q6 on the second horizontal row A2 of the liquid crystal display element 26 corresponds to two pixels P6 on the fourth horizontal line B4 of the CCD 12, and the dot Q7 on the second horizontal row A2 is It corresponds to two pixels P7 on the third horizontal line B4. That is, on the CCD 12, two pixels corresponding to each dot on the second horizontal row A2 are arranged along the horizontal direction. Further, on the CCD 12, two pixels on the third horizontal line B3 and two pixels on the fourth horizontal line are shifted by one pixel in the horizontal direction.
[0029]
For example, the dots Q6 of the even-numbered column A2 of the liquid crystal display element 26 are offset by a half pitch (that is, 1/2 dot) in the horizontal direction with respect to the dots Q1 and Q2 of the odd-numbered column A1. In the physical correspondence relationship, although it corresponds to R of pixel P8, G on the left side of two pixels P4, and B of two pixels P6, these four pixels are simply added. Even when the signal of the dot Q6 of the B component is generated, the excess G component and R component are included, and the image quality is deteriorated due to the component mixing. However, in the present embodiment, only the signal for two pixels of the B component of the pixel P6 is read separately from the pixel signals of the other R and G components by transfer control of signal charges in the CCD 12 described later. The color components of the dots of the liquid crystal display element 26 and the color components of the pixels of the CCD 12 used for the dot display are matched to achieve high image quality.
[0030]
In this manner, the color of the color filter element provided in two pixels (for example, two pixels of P1) vertically adjacent to the first and second horizontal lines B1 and B2 corresponds to the midpoint of these two pixels. The color of the color filter element provided on the dot (for example, reference numeral Q1) of the liquid crystal display element 26 is the same. Further, the color of the color filter element provided in two pixels (for example, two pixels of P4) adjacent in the horizontal direction of the third horizontal line B3 is a dot of the liquid crystal display element 26 corresponding to the middle point of these two pixels. It is the same as the color of the color filter element provided in (for example, reference Q4). The same applies to the fourth horizontal line B4.
[0031]
Another way to look at the arrangement of color filters of the CCD 12 is that in three consecutive horizontal lines, color filters of the same color (color filters hatched in horizontal lines B1, B2 and B3) are arranged in a U shape In the next three horizontal lines, color filters of the same color (color filters hatched in horizontal lines B4, B1 and B2) are arranged in an inverted U-shape. Such U-shaped and inverted U-shaped array patterns appear alternately from the top to the bottom of FIG. 2, and by adopting such an array pattern, the color filter of the CCD 12 displays a liquid crystal display It corresponds to the color arrangement pattern of the delta arrangement of elements.
[0032]
FIG. 3 is a diagram showing the configuration of the CCD 12. For the sake of simplicity, only a part of the photodiode, the vertical transfer CCD, etc. is shown.
[0033]
As described above, the CCD 12 is a two-line readout type / all pixel independent readout type. The CCD 12 has first and second horizontal transfer CCDs 41 and 42. Four electrodes V1 to V4 are connected to one photodiode PD, and pixel signals A to P obtained by the respective photodiodes PD are transferred to the horizontal transfer CCDs 41 and 42 independently of each other by the vertical transfer CCD 43. Supplied. In the figure, based on pixel signals A, B, C, D, E, F, G, H generated in the two rows of photodiodes PD1 extending in the horizontal direction, the (n + 1) th row horizontal on liquid crystal display element 26 The dot signals on the column A1 are generated, and the pixel signals I, J, K, L, M, N, O, and P generated in the two horizontally extending photodiodes PD2 are generated on the liquid crystal display element 26. (N) A dot signal of the horizontal column A2 of the line is generated. The order in which the pixel signals are read out from the CCD 12 is the one corresponding to the (n) th line, and the one corresponding to the (n + 1) th line is later, and the order of driving the dots in the liquid crystal display element 26 is also The order is (n) line, (n + 1) line.
[0034]
Each horizontal transfer CCD 41, 42 has first and second electrodes H1, H2 alternately arranged, and a shift gate electrode SG is provided between each horizontal transfer CCD 41, 42. The CCD 12 is configured such that a potential barrier (well) separating the horizontal transfer CCDs 41 and 42 is formed when the shift gate electrode SG is off, and the potential barrier disappears when the shift gate electrode SG is on. It is done. A reset circuit 44, charge / voltage conversion capacitors 45, 46 and output buffers 47, 48 are connected to output terminals of the horizontal transfer CCDs 41, 42. Two pixel signals output from the first horizontal transfer CCD 41 are added by the charge-voltage conversion capacitor 45, and two pixel signals output from the second horizontal transfer CCD 42 are added by the charge-voltage conversion capacitor 46. Be done. The added pixel signal is converted into a voltage by the charge-voltage conversion capacitors 45 and 46, and is input to the CDS circuits 16a and 16b of the signal processing circuit 16 via the output buffers 47 and 48. The charges stored in the charge-voltage conversion capacitors 45 and 46 are reset by the action of the reset circuit 44.
[0035]
FIGS. 4 and 5 are timing charts showing an operation in which the pixel signal is added and output in the CCD 12 and the pixel signal is transferred to the amplifier circuit 16 d in the signal processing circuit 16, and FIG. ₅ ~ T ₆ Operation in greater detail, and FIG. ₈ The following operations are shown in detail. 6 to 13 are each time t ₁ ~ T ₈ FIG. 16 is a diagram showing a transfer state of pixel signals in
[0036]
In the vertical transfer CCD 43 and the horizontal transfer CCDs 41 and 42, when the voltage signals applied to the electrodes V1 to V4, H1 and H2 are high (Hi), a potential well is formed at a portion corresponding to the electrodes, In the case of), potential wells are not formed. In the shift gate electrode SG, when the voltage signal applied thereto is Hi, a potential well is formed at a portion corresponding to the electrode SG.
[0037]
Time t ₁ It is assumed that the pixel signals A to P generated in the photodiode PD are transferred to the vertical transfer CCD 43 and the vertical transfer has already started before reaching. Time t ₁ Then, among the electrodes V1 to V4, the electrodes V4 and V1 are Hi, and the pixel signals A to P are located at the portions corresponding to the electrodes V4 and V1. Time t ₁ ~ T ₂ In this case, the electrodes V1 to V4 change to Hi and Lo at a predetermined timing, whereby the pixel signals A to P are vertically transferred. Time t ₂ Then, the pixel signals A to L are time t ₁ The vertical transfer is performed by one photodiode as compared with the case of. At this time, since the shift gate electrode SG is Hi, the pixel signals M, N, O, and P are held by the shift gate electrode SG. Time t ₃ Then, since the electrodes V1 and V2 become Hi, the pixel signals A to L are transferred to the portion corresponding to the electrodes V1 and V2. In the second horizontal transfer CCD 42, since the electrode H1 is Hi and the shift gate electrode SG is Lo, the pixel signals M, N, O, P are transferred from the shift gate electrode side to the second horizontal transfer CCD 42. Ru.
[0038]
Time t ₃ ~ T ₄ In this case, since the electrode H1 becomes Lo for one pulse and Hi for the electrode H2 for 1 pulse, the pixel signals M to P are horizontally transferred to the part corresponding to the next electrode H1, and the time t ₄ In this case, the pixel signal M is located at a portion corresponding to the electrode H1 closest to the output end. Time t ₄ ~ T ₅ Well, time t ₁ ~ T ₂ Similarly to the above, since the electrodes V1 to V4 change to Hi and Lo at predetermined timing, the pixel signals A to L are vertically transferred. During this time, since the shift gate electrode SG is Lo, the pixel signals I, J, K, and L are supplied to the first horizontal transfer CCD 41 and held there. During this time, horizontal transfer is not performed in the second horizontal transfer CCD 42.
[0039]
Time t ₅ After that, the electrode H1 changes from Hi to Lo, and the electrode H2 changes from Lo to Hi (symbol S1 in FIG. 4), so that the pixel signal M is output from the second horizontal transfer CCD 42, and the output buffer 48 Are input to the CDS circuit 16b of the signal processing circuit 16 (reference numeral S2). By repeating the actions of the electrodes H 1 and H 2, the pixel signal N is output from the second horizontal transfer CCD 42 and transferred to the charge-voltage conversion capacitor 46, and the pixel signal M is transmitted to the charge-voltage conversion capacitor 46. N is added. The added pixel signals M and N are supplied to the CDS circuit 16b via the output buffer 48 (reference S3). Also, although the pixel signal I is output from the first horizontal transfer CCD 41 and supplied to the CDS circuit 16a through the output buffer 47 (reference S4), this pixel signal I is used in the display operation in the liquid crystal display element 26. I will not.
[0040]
The CDS circuits 16a and 16b of the signal processing circuit 16 sample and hold the pixel signal in accordance with the sample and hold signal S / H (symbol S5) output from the CCD timing signal generation circuit 31. That is, the pixel signal I is output from the CDS circuit 16a (reference S6), and the added pixel signals M and N are output from the CDS circuit 16b (reference S7). The switch 16c is switched according to the command signal SW output from the system control circuit 17. When the command signal SW is Lo, the pixel signal I output from the CDS circuit 16a is input to the amplifier circuit 16d (reference S8), When the command signal SW is Hi, the pixel signals M and N output from the CDS circuit 16b are input to the amplifier circuit 16d (reference S9).
[0041]
Note that, after the pixel signals I, M, and N are sampled and held, the reset signal RS (symbol S10) is output from the CCD driver 15, whereby the charges accumulated in the charge-voltage conversion capacitors 45 and 46 are reset. .
[0042]
Similar to the operation described above, the pixel signals J and K output from the first horizontal transfer CCD 41 are added in the charge-voltage conversion capacitor 45 and supplied to the CDS circuit 16a via the output buffer 47 (reference S11 ). Further, the pixel signals O and P output from the second horizontal transfer CCD 42 are added in the charge-voltage conversion capacitor 46 and supplied to the CDS circuit 16 b via the output buffer 48 (reference S12). In the CDS circuits 16a and 16b, the pixel signal is sampled and held according to the sample and hold signal S / H (symbol S13) (symbols S14 and S15), and is input to the amplifier circuit 16d according to the switching control of the switch 16c ( Codes S16 and S17). After the pixel signals J, K, O, P are sampled and held, the reset signal RS (symbol S18) is output to reset the accumulated charge of the charge-voltage conversion capacitors 45, 46.
[0043]
Thus, the pixel signals held in the first and second horizontal transfer CCDs 41 and 42, that is, the pixel signals of the horizontal column A2 of the (n) th row are output from the CCD 12, and the time t ₆ There is no pixel signal in the horizontal transfer CCDs 41 and 42.
[0044]
Time t ₆ ~ T ₇ Well, time t ₁ ~ T ₂ Similarly, since the electrodes V1 to V4 change to Hi and Lo at predetermined timing, the pixel signals A to H are vertically transferred, and the pixel signals E, F, G, and H are transferred to the first horizontal transfer CCD 41. Ru. In the horizontal transfer CCD 41, since the electrode H1 is Hi, the electrode H2 is Lo, and the shift gate electrode SG is Lo, the pixel signals E to H are held at a portion corresponding to the electrode H1. Time t ₇ ~ T ₈ Then, vertical transfer is performed again, and during this time, the voltage level of each electrode of the horizontal transfer CCD 41 does not change. Therefore time t ₈ Then, the pixel signals A, B, C, D are supplied to the horizontal transfer CCD 41 and added to the pixel signals E, F, G, H, respectively.
[0045]
Time t ₈ After that, the charges of the charge-voltage conversion capacitors 45 and 46 are reset by the reset signal RS (symbol S21), then the electrode H1 changes from Hi to Lo, and the electrode H2 changes from Lo to Hi (symbol S22 Thus, the pixel signals A and E added to each other are output from the first horizontal transfer CCD 41, and input to the CDS circuit 16a via the output buffer 47 (reference S23). During this time, nothing is output from the second horizontal transfer CCD 42.
[0046]
In the CDS circuit 16a of the signal processing circuit 16, the pixel signals A and E are sampled and held in accordance with the sample and hold signal S / H (symbol S24) (symbol S25). Since the switch 16c is switched to the CDS circuit 16a side, the sampled and held pixel signals A and E are inputted as they are to the amplifier circuit 16d (reference S26).
[0047]
After the pixel signals A and E are sampled and held, the charges of the charge-voltage conversion capacitors 45 and 46 are reset by the reset signal RS (symbol S27). The pixel signals B and F added to each other are output from the first horizontal transfer CCD 41 according to the voltage change (symbol S28) of the electrodes H1 and H2, and are input to the CDS circuit 16a via the output buffer 47. (Symbol S29). In the CDS circuit 16a, the pixel signals B and F are sampled and held (symbol S31) according to the sample and hold signal S / H (symbol S30), and are input to the amplifier circuit 16d (symbol S32).
[0048]
As described above, with regard to the pixel signals generated in the CCD 12, with respect to the first and second horizontal lines B1 and B2, two pixels adjacent in the vertical direction are added together to form the third and fourth horizontal lines B3, As for B4, two horizontally adjacent pixels are added together and output from the signal processing circuit 16. Therefore, in the present embodiment, since the pixel signals generated in the CCD 12 are added in the CCD 12, there is no need to provide a special arithmetic circuit or the like. Further, in the present embodiment, since the complementary color filter composed of Mg, G, Ye, and Cy is not used, there is no need to provide a circuit for performing complementary color / primary color conversion and the like. Therefore, according to the present embodiment, the circuit configuration is simple, the circuit scale in the electronic camera can be reduced, and the manufacturing cost can be reduced.
[0049]
FIG. 14 is a block diagram showing a circuit configuration of an electronic camera provided with an imaging device according to the second embodiment.
[0050]
The second embodiment is basically different from the first embodiment in that the CCD 12 is a one-line readout type / all pixel independent readout type. That is, each pixel signal generated in the photodiode is transferred to the horizontal transfer CCD without being mutually added in the vertical transfer CCD, and the pixel signal is output from the CCD 12 for each horizontal line. Therefore, the signal processing circuit 16 has a single CDS circuit 16a, and the switch 16c as in the first embodiment is not provided. The other configuration is the same as that of the first embodiment, so the corresponding parts are denoted by the same reference numerals and the description thereof will be omitted.
[0051]
FIG. 15 shows the arrangement of the color filter elements of the first color filter 51 provided on the liquid crystal display element 26 and the arrangement of the color filter elements of the second color filter 52 provided on the CCD 12.
[0052]
As in the first embodiment, the color filter elements of the first color filter 51 follow a delta arrangement. That is, in the first horizontal row A1, color filter elements are arranged in the order of G, R, B from left to right, and the color filter elements of the second horizontal row A2 are the colors of the first horizontal row A1. The pitch is one and a half (1.5 pixels) offset from the filter element.
[0053]
In the CCD 12, the photodiodes are arranged in a grid, and the number of photodiodes or pixels is approximately twice the number of dots of the liquid crystal display element 26. In the first and second horizontal lines B1 and B2, color filter elements are disposed in the order of G, R and B from left to right. The color filter element of the third horizontal line B3 is B at the position corresponding to G of the second horizontal line B2, G at the position corresponding to R of the second horizontal line B2, and the second horizontal line B2. R is provided in the position corresponding to B of each. The color filter element of the fourth horizontal line B4 is R at a position corresponding to B of the third horizontal line B3, B at a position corresponding to G of the third horizontal line B3, and third horizontal line B3. G is provided at a position corresponding to R of.
[0054]
In the CCD 12, the first horizontal row A1 of the liquid crystal display element 26 corresponds to the first and second horizontal lines B1 and B2, and the second horizontal row A2 of the liquid crystal display element 26 is the third and fourth horizontal lines It corresponds to B3 and B4.
[0055]
The color of the color filter element of the second color filter 52 is the same in adjacent two pixels. In the first and second horizontal lines B1 and B2, as in the first embodiment, the color filter elements of two pixels indicated by reference signs P1, P2 and P3 are G, R and B, respectively. In the third and fourth horizontal lines B3 and B4, the color filter elements of two pixels indicated by reference signs P6, P4 and P7 are B, G and R, respectively.
[0056]
The dots Q1 on the first horizontal row A1 of the liquid crystal display element 26 correspond to the pixels P1 on the first and second horizontal lines B1 and B2 of the CCD 12, and the dots Q2 on the first horizontal row A1 are Two pixels corresponding to the dots on the first horizontal row A1 correspond to the pixels P2 on the first and second horizontal lines B1 and B2 of the CCD 12, and are arranged along the vertical direction.
[0057]
The dot Q6 on the second horizontal row A2 of the liquid crystal display element 26 corresponds to the pixel P6 on the third horizontal line B3 of the CCD 12 and the pixel P6 on the fourth horizontal line B4, and the second horizontal row A2 The upper dot Q4 corresponds to the pixel P4 on the third horizontal line B3 of the CCD 12 and the pixel P4 on the fourth horizontal line B4. The dot Q7 on the second horizontal row A2 corresponds to the pixel P7 on the third horizontal line B3 of the CCD 12 and the pixel P7 on the fourth horizontal line B4. That is, on the CCD 12, two pixels corresponding to each dot on the second horizontal row A2 are disposed along the oblique direction.
[0058]
As described above, also in the second embodiment, the color of the color filter element provided in two pixels (for example, two pixels of P1) adjacent to the first and second horizontal lines B1 and B2 in the vertical direction is the same. The color is the same as the color of the color filter element provided on the dot (for example, reference numeral Q1) of the liquid crystal display element 26 corresponding to the middle point of two pixels. In addition, the color of the color filter element provided in two pixels (for example, two pixels of P4) adjacent in the diagonal direction in the third and fourth horizontal lines B3 and B4 is a liquid crystal corresponding to the middle point of these two pixels It is the same as the color of the color filter element provided on the dot (for example, reference Q4) of the display element 26.
[0059]
FIG. 16 schematically shows the structure of the CCD 12.
The CCD 12 has one horizontal transfer CCD 41. Three electrodes V1 to V3 are connected to one photodiode PD, and pixel signals A to P obtained by the respective photodiodes PD are mutually transferred by the vertical transfer CCD 43 and supplied to the horizontal transfer CCD 41. Ru. In the figure, based on pixel signals A, B, C, D, E, F, G, H generated in the two rows of photodiodes PD1 extending in the horizontal direction, the (n + 1) th row horizontal on liquid crystal display element 26 The dot signals on the column A1 are generated, and the pixel signals I, J, K, L, M, N, O, and P generated in the two horizontally extending photodiodes PD2 are generated on the liquid crystal display element 26. (N) A dot signal of the horizontal column A2 of the line is generated.
[0060]
The horizontal transfer CCD 41 has first and second electrodes H1 and H2 arranged alternately. At the output end of the horizontal transfer CCD 41, a reset circuit 44, a charge / voltage conversion capacitor 45, and an output buffer 47 are connected. The operations of these reset circuit 44, charge-voltage conversion capacitor 45, and output buffer 47 are the same as in the first embodiment.
[0061]
FIG. 17 is a timing chart showing an operation in which pixel signals are added and output in the CCD 12. Also, each of FIG. 18 to FIG. ₁ ~ T ₇ FIG. 16 is a diagram showing a transfer state of pixel signals in
[0062]
Time t ₁ Then, among the electrodes V1 to V3, only the electrode V2 is Hi, and the pixel signals A to P generated in the photodiode PD and read out to the VCCD are accumulated in the electrode V2. Time t ₁ ~ T ₂ In this case, the electrodes V1 to V3 change to Hi and Lo at predetermined timing, whereby the pixel signals A to P are vertically transferred. Time t ₂ Then, the pixel signals A to L are time t ₁ The pixel signals M, N, O and P are vertically transferred by one photodiode as compared with the case of the pixel signal M, N, O, P.
[0063]
Time t ₂ ~ T ₃ In this case, since the electrode H1 of the horizontal transfer CCD 41 is Lo for one pulse and the electrode H2 is Hi for one pulse, the pixel signals M to P are horizontally transferred to the part corresponding to the next electrode H1. ₃ In this case, the pixel signal M is located at a portion corresponding to the electrode H1 closest to the output end. Time t ₃ ~ T ₄ Well, time t ₁ ~ T ₂ Similarly, since the electrodes V1 to V4 change to Hi and Lo at predetermined timings, the pixel signals A to L are vertically transferred, and the pixel signals I, J, K, and L are supplied to the horizontal transfer CCD 41. During this time, since the electrodes H1 and H2 of the horizontal transfer CCD 41 are fixed (that is, the electrode H1 is Hi and the electrode H2 is Lo), the pixel signals M to P of the horizontal transfer CCD 41 are stopped. ₄ Then, the pixel signals I, J and K are added to the pixel signals N, O and P, respectively.
[0064]
Time t ₄ ~ T ₅ In this case, the electrode H1 changes to Hi and Lo at a predetermined timing, whereby the pixel signals M, N and I, O and J, P and K, L are horizontally transferred in the horizontal transfer CCD 41. First, the pixel signal M is output from the horizontal transfer CCD 41, transferred to the charge-voltage conversion capacitor 45, and supplied to the CDS circuit 16a of the signal processing circuit 16 via the output buffer 47. After the accumulated charges of the charge-voltage conversion capacitor 45 are reset by the action of the reset circuit 44, the pixel signals N and I are output from the horizontal transfer CCD 41 and transferred to the charge-voltage conversion capacitor 45 and output via the output buffer 47. It is supplied to the CDS circuit 16a. Similarly, pixel signals O and J, P and K, L are output from the horizontal transfer CCD 41. Time t ₅ In the above, the output operation from the horizontal transfer CCD 41 of the pixel signal for one horizontal line is completed.
[0065]
Time t ₅ ~ T ₆ Well, time t ₁ ~ T ₂ Similarly, the electrodes V1 to V3 change to Hi and Lo at predetermined timing, and the pixel signals A to H are vertically transferred, and the time t ₆ Then, the pixel signals E, F, G and H are supplied to the horizontal transfer CCD 41. Time t ₆ ~ T ₇ But vertical transfer is performed, but during this time, since the electrodes H1 and H2 of the horizontal transfer CCD 41 are fixed (that is, the electrode H1 is Hi and the electrode H2 is Lo), the pixel signals E to H of the horizontal transfer CCD 41 are stopped. . Therefore time t ₇ Then, the pixel signals A, B, C, D are added to the pixel signals E, F, G, H respectively.
[0066]
Next, horizontal transfer is performed, and pixel signals E and A, F and B, G and C, H and D are output from the CCD 12.
[0067]
As described above, also in the second embodiment, since it is not necessary to provide a special arithmetic circuit or the like for adding pixel signals, the circuit configuration is simple as in the first embodiment, and the electronic camera Circuit size can be reduced.
[0068]
25 to 27 show a third embodiment. The circuit configuration of the electronic camera of the third embodiment is the same as that of the second embodiment, that is, FIG.
[0069]
FIG. 25 shows the arrangement of color filter elements of the first color filter 51 provided on the liquid crystal display element 26 and the arrangement of color filter elements of the second color filter 52 provided on the CCD 12.
[0070]
As in the first and second embodiments, the color filter elements of the first color filter 51 are arranged according to a delta arrangement.
[0071]
In the CCD 12, the photodiodes are arranged in a grid, and the number of photodiodes or pixels is approximately twice the number of dots of the liquid crystal display element 26. In the first horizontal line B1, color filter elements are disposed in the order of G, G, R, R, B, and B from left to right. In the second horizontal line B2, color filter elements of R, B, B, G, G and R are provided at positions corresponding to G, G, R, R, B and B of the first horizontal line B1. It is done. That is, two filter elements in which the same color is continuous in the first horizontal line B1 and two filter elements in which the same color is continuous in the second horizontal line B2 are shifted by one pixel in the horizontal direction.
[0072]
In the CCD 12, the first horizontal row A1 of the liquid crystal display element 26 corresponds to the first horizontal line B1, and the second horizontal row A2 of the liquid crystal display element 26 corresponds to the second horizontal line B2.
[0073]
The color of the color filter element of the second color filter 52 is the same in two horizontally adjacent pixels. In the first horizontal line B1, color filter elements of each two pixels indicated by reference signs P1, P2, and P3 are G, R, and B, respectively. In the second horizontal line B2, color filter elements of each two pixels indicated by reference signs P6, P4, and P7 are B, G, and R, respectively.
[0074]
The dots Q 1, Q 2, Q 3 on the first horizontal row A 1 of the liquid crystal display element 26 correspond to the pixels P 1, P 2, P 3 on the first horizontal line B 1 of the CCD 12 respectively. The dots Q6, Q4 and Q7 on the second horizontal row A2 correspond to the pixels P6, P4 and P7 on the second horizontal line B2, respectively.
[0075]
As described above, also in the third embodiment, the color of the color filter element provided in two pixels (for example, two pixels of P1) adjacent in the horizontal direction of the first horizontal line B1 is the midpoint of the two pixels Are the same as the color of the color filter element provided on the dot (for example, reference numeral Q1) of the liquid crystal display element 26 corresponding to.
[0076]
FIG. 26 schematically shows the structure of the CCD 12.
The CCD 12 basically has the same configuration as the CCD of the second embodiment, but a liquid crystal display element based on pixel signals A, B, C, D generated in one row of photodiodes PD1 extending in the horizontal direction. Pixel signals of the horizontal column A1 of the (n + 1) th row on the 26th row are generated, and the pixel signals E, F, G, H generated in the photodiode PD2 of one row extending in the horizontal direction The second embodiment differs from the second embodiment in that pixel signals of the horizontal column A2 of the (n) th row of the second embodiment are generated.
[0077]
FIG. 27 is a timing chart showing an operation in which pixel signals are added and output in the CCD 12.
[0078]
In the vertical transfer CCD 43, the electrodes V1 to V3 change to Hi and Lo at a predetermined timing, whereby the pixel signals A to P are vertically transferred, and the pixel signals E, F, G, and H are supplied to the horizontal transfer CCD 41. Next, the pixel signals E, F, G and H are horizontally transferred according to the control of the electrodes H1 and H2 of the horizontal transfer CCD 41, and the pixel signal E reaches the portion corresponding to the electrode H1 closest to the output terminal.
[0079]
In this state, when the electrode H1 changes from Hi to Lo and the electrode H2 changes from Lo to Hi (reference S41), the pixel signal E is output to the CDS circuit 16a of the signal processing circuit 16 via the output buffer 47. And the other pixel signals F, G and H are horizontally transferred. Next, a reset signal RS (symbol S43) is output, whereby the charge stored in the charge-voltage conversion capacitor 45 is reset. Further, the pixel signal F is output to the charge-voltage conversion capacitor 45 in accordance with the control of the electrodes H1 and H2 (reference S44). By repeating the actions of the electrodes H1 and H2, the pixel signal G is transferred to the charge-voltage conversion capacitor 45, and the pixel signals F and G are added in the charge-voltage conversion capacitor 45. The added pixel signals F and G are supplied to the CDS circuit 16a via the output buffer 47 (reference S45).
[0080]
In the CDS circuit 16a, the pixel signal is sampled and held in accordance with the sample and hold signal S / H (symbol S46). That is, the added pixel signals F and G are output from the CDS circuit 16a (symbol S47), and are input to the amplifier circuit 16d. Note that, after the pixel signals F and G are sampled and held, the reset signal RS (symbol S48) is output, whereby the charge stored in the charge-voltage conversion capacitor 45 is reset.
[0081]
Similar to the above-described operation, the pixel signal H output from the horizontal transfer CCD 41 is supplied to the CDS circuit 16a via the output buffer 47 (reference S49). In the CDS circuit 16a, the pixel signal H is sampled and held (symbol S51) according to the sample and hold signal S / H (symbol S50), and is input to the amplifier circuit 16d. After the pixel signal H is sampled and held, the reset signal RS (symbol S52) is output to reset the accumulated charge of the charge-voltage conversion capacitor 45.
[0082]
As described above, in the third embodiment, two horizontally adjacent pixels in the photodiode of the CCD 12 are added in the horizontal transfer CCD 41 and output from the CCD 12. Therefore, also in this configuration, since it is not necessary to provide a special arithmetic circuit or the like for adding pixel signals, the circuit configuration is simple as in the first and second embodiments, and the circuit in the electronic camera The scale can be kept small.
[0083]
28 to 36 show a fourth embodiment. The circuit configuration of the electronic camera of the fourth embodiment is the same as that of the second embodiment, that is, FIG.
[0084]
FIG. 28 shows the arrangement of the color filter elements of the first color filter 51 provided on the liquid crystal display element 26 and the arrangement of the color filter elements of the second color filter 52 provided on the CCD 12.
[0085]
As in the first and second embodiments, the color filter elements of the first color filter 51 are arranged according to a delta arrangement.
[0086]
In the CCD 12, the photodiodes are arranged in a grid, and the number of photodiodes or pixels is about four times the number of dots of the liquid crystal display element 26. In the first and second horizontal lines B1 and B2, color filter elements are disposed in the order of G, G, R, R, B, and B from left to right. In the third and fourth horizontal lines B3 and B4, R, B, B and G are provided at positions corresponding to G, G, R, R, B and B of the first and second horizontal lines B1 and B2. , G, R color filter elements are provided. That is, two filter elements in which the same color is continuous in the first and second horizontal lines B1 and B2 and two filter elements in which the same color is continuous in the third and fourth horizontal lines B3 and B4 are in the horizontal direction Are offset by one pixel.
[0087]
In the CCD 12, the first horizontal row A1 of the liquid crystal display element 26 corresponds to the first and second horizontal lines B1 and B2, and the second horizontal row A2 of the liquid crystal display element 26 is the third and fourth horizontal lines It corresponds to B3 and B4.
[0088]
The color of the color filter element of the second color filter 52 is the same in the horizontally and vertically adjacent four pixels. In the first and second horizontal lines B1 and B2, color filter elements of four pixels indicated by reference numerals P1, P2 and P3 are G, R and B, respectively. In the third and fourth horizontal lines B3 and B4, color filter elements of four pixels indicated by reference signs P6, P4 and P7 are B, G and R, respectively.
[0089]
The dots Q1, Q2, Q3 on the first horizontal row A1 of the liquid crystal display element 26 correspond to the pixels P1, P2, P3 on the first and second horizontal lines B1, B2 of the CCD 12, respectively. The dots Q6, Q4 and Q7 on the second horizontal row A2 correspond to the pixels P6, P4 and P7 on the third and fourth horizontal lines B3 and B4, respectively.
[0090]
FIG. 29 schematically shows the structure of the CCD 12.
The CCD 12 has one horizontal transfer CCD 41. Based on pixel signals A, B, C, D, E, F, G, H generated in two columns of photodiode PD1 extending in the horizontal direction, the (n + 1) th row horizontal column A1 on the liquid crystal display element 26 A dot signal is generated, and the pixel signal I, J, K, L, M, N, O, P generated in the two rows of the photodiode PD2 extending in the horizontal direction is generated on the liquid crystal display element 26 (n) A dot signal of the horizontal row A2 of the line is generated. Two electrodes V1 and V2 or electrodes V3 and V4 are connected to one photodiode PD, and pixel signals A to P obtained by each photodiode PD are transferred by the vertical transfer CCD 43 independently from each other and horizontally The transfer CCDs 41 and 42 are supplied.
[0091]
FIG. 30 is a timing chart showing an operation in which the pixel signal is added and output in the CCD 12 and the pixel signal is transferred to the amplifier circuit 16 d in the signal processing circuit 16. Also, each of FIG. 31 to FIG. ₁ ~ T ₆ FIG. 16 is a diagram showing a transfer state of pixel signals in
[0092]
In the vertical transfer CCD 43, when the voltage signal applied to the electrodes V1 and V3 is Hi, the pixel signal is transferred from the photodiode PD to the vertical transfer CCD 43, and when it is middle (Md), the potential corresponding to the electrode A well is formed, and a potential well is not formed when Lo.
[0093]
Time t ₁ In this case, the pixel signal generated in the photodiode PD has not been transferred to the vertical transfer CCD 43 yet. Time t ₁ ~ T ₂ Since the electrode V1 among the electrodes V1 to V4 becomes Hi, the pixel signals A, B, C, D, I, J, K, and L are transferred from the photodiode PD to the vertical transfer CCD 43. Time t ₂ ~ T ₃ Then, among the electrodes V1 to V4, since the electrode V3 becomes Hi, the pixel signals E, F, G, H, M, N, O, P are transferred from the photodiode PD to the vertical transfer CCD 43.
[0094]
Time t ₄ Then, since the electrode V2 changes from Lo to Md, a potential well is formed at a portion corresponding to the electrodes V1 to V3, and thereby the pixel signals A and E are added. Similarly, pixel signals B and F, pixel signals C and G, pixel signals D and H, pixel signals I and M, pixel signals J and N, pixel signals K and O, and pixel signals L and P are respectively added.
[0095]
Time t ₅ Then, since the electrode V1 changes from Md to Lo and the electrode V4 changes from Lo to Md, a potential well is formed at a portion corresponding to the electrodes V2 to V4. As a result, the added pixel signal corresponds to one electrode Only vertically transferred. At this time, since the electrode H1 of the horizontal transfer CCD 41 is Hi, the potential well of the portion closest to the horizontal transfer CCD 41 among the vertical transfer CCDs 43 is the well of the portion corresponding to the electrode H1 of the horizontal transfer CCD 41. A part of the connected and added pixel signals I and M moves to the horizontal transfer CCD 41. Time t ₅ ~ T ₆ Similarly, vertical transfer is performed between time t and time t ₆ Then, since the electrode V4 becomes Lo, the horizontal transfer CCD 41 is blocked from the vertical transfer CCD 43, and the added pixel signals I and M, J and N, K and O, L and P are held only in the horizontal transfer CCD 41.
[0096]
Time t ₆ After that, the electrodes H1 and H2 change between Hi and Lo, and the reset signal RS and the sample hold signal S / H are output at a predetermined timing, similar to the operation described with reference to FIG. The pixel signal is output from the horizontal transfer CCD 41 and subjected to predetermined processing in the signal processing circuit 16.
[0097]
As described above, according to the fourth embodiment, the same effect as that of the first to third embodiments can be obtained.
[0098]
FIG. 37 is a view showing the correspondence between the dots of the liquid crystal display element 26 and the pixels of the CCD 12 in the fifth embodiment. The dots T1 of the liquid crystal display element 26 have a delta arrangement as in the above embodiments. The pixels T2 of the CCD 12 are arranged in a lattice, and only the pixels corresponding to the dots T1 of the liquid crystal display element 26 are used to display an image. In the fifth embodiment, one pixel T2 of the CCD 12 corresponds to one dot T1 of the liquid crystal display element 26, and addition of pixel signals is not performed. In this configuration, the color filter 52 provided on the CCD 12 is a stripe type as shown in FIG. 38 or 39, and the color filter elements corresponding to the pixel signals to be used are circled. The circuit configuration of the electronic camera provided with the imaging device of the fifth embodiment is the same as that of FIG.
[0099]
FIG. 40 is a view showing the correspondence between the dots of the liquid crystal display element 26 and the pixels of the CCD 12 in the sixth embodiment. The dots T1 of the liquid crystal display element 26 have a delta arrangement as in the above embodiments. The pixels T2 of the CCD 12 are arranged in a lattice, and only the pixels corresponding to the dots T1 of the liquid crystal display element 26 are used to display an image. In the sixth embodiment, two pixels T2 of the CCD 12 correspond to one dot T1 of the liquid crystal display element 26, and the signals of the two pixels T2 are added and output from the CCD 12. The color filter 52 provided on the CCD 12 is a stripe type as shown in FIG. 38 or 39 as in the fifth embodiment. The circuit configuration of the electronic camera provided with the imaging device of the sixth embodiment is also the same as that of FIG.
[0100]
【Effect of the invention】
As described above, according to the present invention, an imaging device having a simple circuit configuration can be obtained. According to this imaging device, the manufacturing cost can be suppressed without increasing the circuit scale in the electronic camera.
Brief Description of the Drawings
FIG. 1 is a block diagram showing a circuit configuration of an electronic camera provided with an imaging device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an arrangement of color filter elements of a color filter on a liquid crystal display element and an arrangement of color filter elements of a color filter on a CCD.
FIG. 3 is a view schematically showing a configuration of a CCD in the first embodiment.
FIG. 4 is a timing chart showing an operation in which a pixel signal is added and output in a CCD, and the pixel signal is transferred to an amplifier circuit in a signal processing circuit.
FIG. 5 is a timing chart showing an operation in which a pixel signal is added and output in a CCD, and the pixel signal is transferred to an amplifier circuit in a signal processing circuit.
[Fig. 6] time t ₁ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 7] time t ₂ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 8] time t ₃ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 9] time t ₄ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 10] time t ₅ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 11] time t ₆ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 12] time t ₇ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 13] time t ₈ FIG. 16 is a diagram showing a transfer state of pixel signals in
FIG. 14 is a block diagram showing a circuit configuration of an electronic camera provided with an imaging device according to a second embodiment.
FIG. 15 is a view showing an arrangement of color filter elements of a color filter on a liquid crystal display element in a second embodiment and an arrangement of color filter elements of a color filter on a CCD.
FIG. 16 is a view schematically showing a configuration of a CCD according to a second embodiment.
FIG. 17 is a timing chart showing an operation in which pixel signals are added and output in a CCD.
[FIG. 18] time t ₁ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 19] time t ₂ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 20] time t ₃ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 21] time t ₄ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 22] time t ₅ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 23] time t ₆ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 24] time t ₇ FIG. 16 is a diagram showing a transfer state of pixel signals in
FIG. 25 is a view showing an arrangement of color filter elements of a color filter on a liquid crystal display element in a third embodiment and an arrangement of color filter elements of a color filter on a CCD.
FIG. 26 is a view schematically showing a configuration of a CCD according to a third embodiment.
FIG. 27 is a timing chart showing an operation in which pixel signals are added and output in a CCD.
FIG. 28 is a view showing an arrangement of color filter elements of a color filter on a liquid crystal display element in a fourth embodiment and an arrangement of color filter elements of a color filter on a CCD.
FIG. 29 schematically shows a configuration of a CCD according to a fourth embodiment.
FIG. 30 is a timing chart showing an operation in which a pixel signal is added and output in a CCD, and the pixel signal is transferred to an amplifier circuit in a signal processing circuit.
[FIG. 31] time t ₁ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 32] time t ₂ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 33] time t ₃ FIG. 16 is a diagram showing a transfer state of pixel signals in
[Fig. 34] time t ₄ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 35] time t ₅ FIG. 16 is a diagram showing a transfer state of pixel signals in
[FIG. 36] time t ₆ FIG. 16 is a diagram showing a transfer state of pixel signals in
FIG. 37 is a view showing the correspondence between dots of the liquid crystal display element and pixels of the CCD in the fifth embodiment.
FIG. 38 is a diagram showing another example of a color filter provided on a CCD.
FIG. 39 is a diagram showing still another example of a color filter provided on a CCD.
FIG. 40 is a diagram showing the correspondence between dots of the liquid crystal display element and pixels of the CCD in the sixth embodiment.
[Description of the code]
12 CCD
26 Liquid Crystal Display Device
51 First color filter
52 Second color filter

Claims (7)

A display element provided with a first color filter comprising three different color filter elements arranged on each dot according to a delta arrangement;
A solid provided with a second color filter arranged in a grid and having pixels that are integral multiples of the number of dots, and any of color filter elements of the same type as the display element are arranged on the pixels And an imaging device,
The color of the second color filter elements of a color filter is the same in two adjacent pixels, and Ri same der color elements of a color filter provided in the dots corresponding to the midpoint of these two pixels The display device according to claim 1, wherein the two pixels are disposed in the vertical direction on the solid-state imaging device. A display element provided with a first color filter comprising three different color filter elements arranged on each dot according to a delta arrangement;
A solid provided with a second color filter arranged in a grid and having pixels that are integral multiples of the number of dots, and any of color filter elements of the same type as the display element are arranged on the pixels And an imaging device,
The color of the color filter element of the second color filter is the same in adjacent two pixels, and the same as the color of the element of the color filter provided in the dot corresponding to the midpoint between these two pixels, Furthermore, on the solid-state imaging device, the two pixels corresponding to each dot on the first horizontal row of the liquid crystal display device are disposed along the vertical direction, and the second pixel adjacent to the first horizontal row is disposed. A display device characterized in that the two pixels corresponding to each dot on the horizontal row are arranged along the horizontal direction. The first horizontal row corresponds to a first horizontal line and a second horizontal line adjacent thereto on the solid-state imaging device, and one of two pixels corresponding to each dot on the first horizontal row. the first included in the horizontal line, the other of the two pixels the display device according to claim 2, characterized in that included in the second horizontal line. The second horizontal row corresponds to the third horizontal line and the fourth horizontal line adjacent thereto on the solid-state imaging device, and the two pixels on the third horizontal line and the fourth The display device according to claim 2 , wherein the two pixels on the horizontal line are shifted by one pixel in the horizontal direction. A display element provided with a first color filter comprising three different color filter elements arranged on each dot according to a delta arrangement;
A solid provided with a second color filter arranged in a grid and having pixels that are integral multiples of the number of dots, and any of color filter elements of the same type as the display element are arranged on the pixels And an imaging device,
The color of the color filter element of the second color filter is the same in adjacent two pixels, and the same as the color of the element of the color filter provided in the dot corresponding to the midpoint between these two pixels, Furthermore, the display device is characterized in that the two pixels are disposed along the oblique direction on the solid-state imaging device. The display device according to any one of claims 1 to 5, wherein the display element is a liquid crystal display element. The display device according to any one of claims 1 to 5, wherein the first and second color filters consist of color filter elements of three primary colors of red, green and blue.

Images