JP3588301B2 - Half-bridge type inverter circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a half-bridge type inverter circuit, and more particularly to a half-bridge type inverter circuit to which a load driven by a high voltage is connected.
[0002]
[Prior art]
FIG. 1 shows a configuration of a half-bridge inverter circuit for lighting. Q1 and Q2 are main switching elements composed of power MOSFETs, and D1 and D2 are commutation diodes of resonance current composed of parasitic diodes between the drain and source of the power MOSFET. In the ballast circuit, L is a resonance reactor, C1 is a DC component cutting capacitor, C2 is a filament preheating capacitor, and the fluorescent lamp has a circuit configuration connected in parallel with the filament preheating capacitor C2.
[0003]
FIG. 2 shows operation waveforms when the lamp is turned on. VGS1 and VGS2 are gate-source voltages of the main switching elements Q1 and Q2. During operation, the main switching elements Q1 and Q2 are alternately turned on and off alternately, and a dead time period during which the main switching elements Q1 and Q2 are both turned off in order to prevent the main switching elements Q1 and Q2 from being turned on at the same time. Have.
[0004]
The high-side main switching element Q1 turns on when VGS1 becomes high, and the drain current indicated by ID1 flows. Thus, a square wave voltage is applied to the ballast circuit composed of L, C1, C2 and the fluorescent lamp, and a sine wave ballast current I1 flows. The ballast current I1 during lamp operation is a combined current of the filament current I2 and the lamp current I3.
[0005]
The low-side main switching element Q2 is turned on when VGS2 becomes high, and the drain current ID2 flows. As a result, the energy stored in the ballast circuit is released, and the ballast current I1, the filament current I2, and the lamp current I3 decrease in the negative direction.
[0006]
A normal half-bridge type inverter circuit is operated at a frequency in a delay region higher than the resonance frequency of the ballast circuit. Therefore, the ballast current I1 can be changed by the switching frequency of the main switching elements Q1 and Q2, so that the brightness can be adjusted.
[0007]
As shown in FIG. 1, the drive circuit 2 converts an input signal from the control circuit 1 into a predetermined drive signal (for example, VGS1, VGS2) and drives the main switching elements Q1, Q2.
[0008]
FIG. 3 shows a specific circuit block of the drive circuit 2. That is, a signal input circuit 21, dead time control circuits 22 and 23 for performing high-side and low-side dead time control, a pulse generation circuit 24, a level shift circuit 25, a pulse filter circuit 26, a storage circuit, , And output circuits 28 and 29 for supplying drive signals for driving the high-side and low-side main switching elements Q1 and Q2.
[0009]
After the drive circuit 2 shapes the output signal from the control circuit 1 by the signal input circuit 21, it is input to the dead time control circuits 22 and 23 for performing the dead time control on the high side and the low side, as shown in FIG. A high-side output signal HO delayed from the input signal (the output signal of the control circuit 1) and a low-side output signal LO that falls before the high-side output signal HO rises are formed. The high-side output signal HO and the low-side output signal LO have a dead time in which both the main switching elements Q1 and Q2 are at a low level so as not to turn on at the same time.
[0010]
In the drive circuit 2 on the high side, since the main switching element Q1 is driven at a voltage of about 600 volts, it is necessary to shift the high side output signal HO to a high voltage of about 600 volts to generate the drive signal VGS1. The output signal PGIN of the dead time control circuit 22 is input to the pulse generation circuit 24 and outputs a set output signal OUT (Set) and a reset output signal OUT (Reset). These signals are input to the next high voltage level shift circuit 25, and are converted into a high voltage set output signal OUT (Set) and a reset output signal OUT (Reset). These signals are passed through a pulse filter circuit 26 to pass a signal having a certain pulse width or more, to set and reset a flip-flop circuit 27, output a high-side output signal HO from an output circuit 28, and output a high-side main signal. The switching element Q1 is driven.
[0011]
FIG. 7 shows the pulse generation circuit 24. In order to output the set output signal OUT (Set) and the reset output signal OUT (Reset) from the input signal PGIN from the dead time control circuit 22 on the high side, the input signal PGIN is inverted by the inverter circuit 241 on the set side. The signal S1 and the input signal PGIN are delayed by a two-stage delay circuit 242 and shaped by an inverter circuit 243 connected in two stages to form a signal S2. Both signals S1 and S2 are input to a NOR gate circuit 244, a set output signal OUT (Set) is obtained, and further shaped via an inverter circuit 245 connected in two stages. The reset side similarly generates a reset output signal OUT (Reset) from the signals R1 and R2.
[0012]
[Problems to be solved by the invention]
In such a half-bridge type inverter circuit, in order to prevent the main switching elements Q1 and Q2 from turning on at the same time, a dead time period in which both drive signals (for example, VGS1 and VGS2) are off is provided.
[0013]
However, when sudden noise is input to the input signal PGIN to the pulse generation circuit 24 of the drive circuit 2, a malfunction occurs, and there is a problem that the main switching elements Q1 and Q2 are simultaneously turned on.
[0014]
As shown in FIG. 8, when the pulse width of the input signal PGIN to the pulse generation circuit 24 is as narrow as 15 ns or less, the signal S2 and the signal R2 are not transmitted by the delay circuit 242, so that the set output signal OUT (Set) becomes the input signal. It has the same waveform as PGIN. On the other hand, the reset output signal OUT (Reset) disappears and is maintained at a low level. For this reason, only the set output signal OUT (Set) eliminates the reset output signal OUT (Reset), so that the high side output signal HO is maintained at a high level. That is, the main switching elements Q1 and Q2 are simultaneously turned on.
[0015]
[Means for Solving the Problems]
The present invention has been made in view of the problem that the main switching elements Q1 and Q2 are in the simultaneous ON mode. In a half-bridge type inverter circuit, the drive circuit includes the high-side main switching element and the low-side main switching element. A high-side output circuit for outputting an output signal for turning on the high-side switching element and having a dead time control circuit for creating a dead time period for preventing the same from being turned on at the same time; A low-side output circuit that has a dead-time control circuit that creates a period and outputs an output signal that turns on a low-side switching element, and outputs the output signal of the dead-time control circuit to the high-side dead time control circuit. Set output A pulse generation circuit that generates a signal and a reset output signal, a pulse filter circuit that passes a pulse having a predetermined pulse width or more among the set output signal and the reset output signal, and the set output signal that has passed through the pulse filter circuit. A high-side output circuit that sets and resets with a reset output signal and outputs the output signal; and when an input signal applied to the drive circuit has a predetermined width or less, a set output signal or a reset output from the pulse generation circuit. A signal is blocked by the pulse filter circuit, an output signal for outputting an output signal for turning on a high-side switching element is deactivated, a high-side main switching element is deactivated, and simultaneous operation of the two main switching elements is performed. The feature is to prevent on.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to FIGS.
[0017]
FIG. 1 shows a configuration of a half-bridge inverter circuit for lighting. Q1 and Q2 are main switching elements composed of power MOSFETs, and D1 and D2 are commutation diodes of resonance current composed of parasitic diodes between the drain and source of the power MOSFET. In the ballast circuit, L is a resonance reactor, C1 is a DC component cutting capacitor, C2 is a filament preheating capacitor, and the fluorescent lamp has a circuit configuration connected in parallel with the filament preheating capacitor C2.
[0018]
FIG. 2 shows operation waveforms, and FIG. 3 shows a circuit block of a drive circuit. The basic operation principle and circuit configuration are the same as those described in the section of the prior art, and thus description thereof is omitted here.
[0019]
FIG. 4 shows the waveforms of the high-side output signal HO delayed from the input signal (the output signal of the control circuit 1) and the low-side output signal LO falling before the high-side output signal HO rises. The high-side output signal HO and the low-side output signal LO have a dead time in which both the main switching elements Q1 and Q2 are at a low level so as not to turn on at the same time.
[0020]
FIG. 7 shows the pulse generation circuit 24. In order to output a set output signal OUT (Set) and a reset output signal OUT (Reset) from an input signal PGIN from the high-side dead time control circuit 22, the input signal IN is inverted by an inverter circuit 241 on the set side. The signal S1 and the input signal IN are delayed by a two-stage delay circuit 242 and shaped by an inverter circuit 243 connected in two stages to form a signal S2. Both signals S1 and S2 are input to a NOR gate circuit 244, a set output signal OUT (Set) is obtained, and further shaped via an inverter circuit 245 connected in two stages. The reset side similarly generates a reset output signal OUT (Reset) from the signals R1 and R2.
[0021]
As shown in FIG. 8, when the pulse width of the input signal PGIN to the pulse generation circuit 24 is as narrow as 12 ns or less, the signal S2 and the signal R2 are not transmitted by the delay circuit 242, so that the set output signal OUT (Set) becomes the input signal. It has the same waveform as PGIN. On the other hand, the reset output signal OUT (Reset) disappears and is maintained at a low level.
[0022]
FIG. 9 shows the pulse input width of the output signal PGIN of the dead time control circuit 22 which is an input to the pulse generation circuit 24, and the set output signal OUT (Set) and the reset output signal OUT (Reset) which are outputs from the pulse generation circuit 24. The relation of the pulse output width is shown.
[0023]
The high-side output signal HO of the drive circuit 2 is configured to be at a high level by the set output signal OUT (Set) of the pulse generation circuit 24 and to be at a low level by the reset output signal OUT (Reset). When the pulse width of the input signal becomes about 12 ns or less due to the operation of the delay circuit 242 of the pulse generation circuit 24, the reset output signal OUT (Reset) becomes an area where it disappears before the set output signal OUT (Set), as shown in FIG. As a result, the high-side output signal HO is maintained at a high level due to the set output signal OUT (Set) remaining in the second stage.
[0024]
FIG. 5 shows a specific circuit diagram of the level shift circuit 25 and the pulse filter circuit 26 to which the set output signal OUT (Set) is applied. Note that the level shift circuit 25 to which the reset output signal OUT (Reset) is applied and the pulse filter circuit 26 have similar circuits.
[0025]
A feature of the present invention resides in the pulse filter circuit 26. The pulse filter circuit 26 is composed of two-stage connected inverter circuits 261 and 262 for performing waveform shaping, a delay circuit 263, and two-stage connected inverter circuits 264 and 265 for performing waveform shaping. The delay circuit 263 includes a resistor R connected between the output terminal of the CMOS inverter circuit and the drain terminal of the P-channel MOS transistor, and a capacitor C connected between the output terminal and the common potential VS. By selecting a time constant formed by the resistor R and the capacitor C, a pulse width that can pass through the pulse filter circuit 26 can be determined. Note that the common potential VS is an intermediate potential between the main switching element Q1 and the main switching element Q2, VB is a high-voltage power supply potential, and COM indicates a ground potential.
[0026]
FIG. 6 shows the relationship between the filter width that causes simultaneous ON and the resistance R (in FIG. 6, represented by a PSD (pulse signal delay) resistance). In the region where the reset output signal OUT (Reset) remains reliably, an operation range in which the filter width is 18 nS or more and the optimum design value is 22 nS to 24 nS is selected. Therefore, in order to make the filter width 18 nS or more, the resistance R needs to be 6.5 KΩ or more. About 9 KΩ is preferable in consideration of manufacturing variations. The capacitance is 2.3 pF.
[0027]
The resistance R of the delay circuit 263 of the pulse filter circuit 26 that outputs the set output signal OUT (Set) is Rs, and similarly, the resistance of the delay circuit (not shown) on the reset output signal OUT (Reset) side. Assuming that R is Rr, by setting Rs> Rr, the set output signal OUT (Set) can be surely eliminated first when the input signal PGIN from the pulse generation circuit 24 is narrow, thereby preventing simultaneous ON. It is valid. Actually, when Rs was 9 KΩ, Rr was 4.7 KΩ.
[0028]
Thus, as is clear from FIG. 9, if the pulse output width from the pulse generation circuit 24 is 18 nS or more, the reset output signal OUT (Reset) does not necessarily disappear, so that the main switching elements Q1 and Q2 are It can be prevented from turning on.
[0029]
【The invention's effect】
According to the present invention, by selecting the time constant of the delay circuit 263 of the pulse filter circuit 26, the set output signal OUT (Set) can be reliably reduced to a region where the reset output signal OUT (Reset) remains without a large circuit change. Is not transmitted, and it is possible to prevent the main switching elements Q1 and Q2 from being simultaneously turned on. This makes it possible to provide a half-bridge type inverter circuit in which a malfunction due to sudden noise is completely avoided.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining the present invention and a conventional half-bridge type inverter circuit.
FIG. 2 is a diagram illustrating operation waveforms of the present invention and a conventional half-bridge type inverter circuit.
FIG. 3 is a diagram illustrating a drive circuit of the present invention and a conventional half-bridge type inverter circuit.
FIG. 4 is a diagram illustrating operation waveforms of a dead time control circuit of the present invention and a conventional half-bridge type inverter circuit.
FIG. 5 is a diagram illustrating a pulse filter circuit of the half-bridge type inverter circuit of the present invention.
FIG. 6 is a diagram illustrating characteristics of the pulse filter circuit of the half-bridge inverter circuit according to the present invention.
FIG. 7 is a diagram illustrating a pulse generation circuit of the present invention and a conventional half-bridge type inverter circuit.
FIG. 8 is a diagram illustrating the operation waveforms of the pulse generation circuit of the present invention and the conventional half-bridge inverter circuit.
FIG. 9 is a diagram illustrating characteristics of a pulse generation circuit of the half-bridge type inverter circuit of the present invention.
[Explanation of symbols]
Q1, Q2 Main switching elements D1, D2 Commutation diode L of resonance current Reactor C1 Capacitor for cutting DC component C2 Capacitor for preheating filament

Claims (4)

Half-bridge inverter circuit comprising a half bridge type switching circuit composed of a main switching element and the low-side main switching element on the high side, and a drive circuit for outputting the output signal you drive the switching circuit At
The drive circuit has a dead time control circuit that creates a dead time period for preventing the high side main switching element and the low side main switching element from being simultaneously turned on, and turns on the high side switching element. A high-side output circuit that outputs an output signal to be turned on, and a low-side output circuit that has a dead time control circuit that creates a dead time period and outputs an output signal that turns on the low-side switching element, as described above. ,
A pulse generating circuit for generating a set output signal and a reset output signal from the output of the dead time control circuit to the high side dead time control circuit; and a pulse having a predetermined pulse width or more among the set output signal and the reset output signal. And a high-side output circuit that sets and resets the set output signal and the reset output signal that have passed through the pulse filter circuit and outputs the output signal,
When the input signal applied to the drive circuit is equal to or smaller than a certain width, the set output signal or the reset output signal from the pulse generation circuit is blocked by the pulse filter circuit and an output signal for turning on a high-side switching element is output. A half-bridge type inverter circuit in which an output circuit is deactivated, a high-side main switching element is deactivated, and the two main switching elements are simultaneously turned off. A flip-flop circuit is connected to the pulse filter circuit on the high side, and an output signal for turning on a high-side switching element is output from the output circuit when the flip-flop circuit is set by the set output signal. half-bridge inverter circuit of claim 1, wherein a. The time constant of the pulse filter circuit for passing the set output signal is made larger than the time constant for passing the reset output signal to prevent transmission of the set output signal to a region where the reset output signal remains. 2. The half-bridge type inverter circuit according to 2. 3. The pulse filter circuit according to claim 2, wherein the pulse filter circuit includes a resistor connected between an output terminal of the CMOS inverter circuit and a drain terminal of the P-channel MOS transistor, and a capacitor connected between the output terminal and a common potential. The half-bridge type inverter circuit according to claim 3.

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