JP3588566B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device in which transistors of a CMOS section and a DRAM memory cell are integrated and integrated on the same semiconductor substrate.
[0002]
[Prior art]
In recent years, in LSI systems, there have been many proposals to integrate and integrate transistors in a CMOS section, a high-density memory such as a DRAM, and other devices. In the case of such an embedded semiconductor device, the memory cell transistors in the DRAM memory cell section and the transistors in the CMOS section have different gate and diffusion layer structures, and therefore are formed in separate steps. For example, in a DRAM memory cell portion, it is common to use a self-aligned contact formation process in order to realize a high density. For this purpose, it is necessary to form a protective insulating film for the self-aligned contact on the gate electrode. is there. On the other hand, in the CMOS section, a dual gate structure is adopted, and it is necessary to lower the resistance of the source / drain diffusion layer and the gate electrode in order to realize high-speed operation. A salicide process is commonly used. When such a DRAM memory cell portion and a CMOS portion are mixedly mounted, it is necessary to prevent formation of a protective insulating film for a self-aligned contact on the gate electrode of the CMOS portion for silicidation. In this case, if the source / drain diffusion layer is silicided, the leakage between the source / drain diffusion layer and the substrate increases, so that it is necessary to prevent the silicidation from occurring. Generally, these layers are formed in separate steps.
[0003]
[Problems to be solved by the invention]
However, in the conventional method of manufacturing a hybrid semiconductor device as described above, since each transistor of the CMOS section and a high-density memory such as a DRAM are separately manufactured, there is a problem that the process is complicated and the cost is high. On the other hand, if the two gates are simultaneously formed, the resist pattern is broken due to the difference in height between the CMOS portion and the DRAM memory cell portion. In particular, the patterning accuracy when forming the gate in the CMOS portion cannot be secured. There were also problems.
[0004]
Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing each gate of a transistor in a CMOS portion and a memory transistor of a high-density memory such as a DRAM by a common process without causing the above-mentioned problems. It is to be.
[0005]
[Means for Solving the Problems]
In the method for manufacturing a semiconductor device according to the present invention, a step (a) of dividing a semiconductor substrate into a first region where a CMOSFET is to be formed by element isolation and a second region where a memory cell transistor of a high density memory is to be formed. A step (b) of forming a first gate insulating film in the first region, a step (c) of forming a second gate insulating film in the second region, (D) forming a first conductive film on the second gate insulating film; and depositing an insulating film for a mask on the first conductive film, and then patterning the insulating film for the mask to form the first conductive film. (E) forming a first gate forming mask on the region where the gate electrode of the region is to be formed; and forming the first conductive film on the first conductive film and the first gate forming mask. Forming a lower resistance second conductor film A step (f), a step (g) of forming a second gate forming mask on the region where the gate electrode of the second region is to be formed on the second conductor film, In the first region, the first conductive film is patterned using the first gate forming mask to form the gate electrode of the CMOSFET, while in the second region, the second gate forming mask is formed. (H) patterning the first and second conductor films by using the above to form a gate electrode of the memory cell transistor; and positioning both sides of each gate electrode in the first and second regions. (I) forming a source / drain diffusion layer of a memory cell transistor and a CMOSFET in a region;After the step (h), removing the first gate forming mask in the first region, and then silicidizing the upper part of the gate electrode of the CMOSFET and the upper part of the source / drain diffusion layer. including.
[0006]
Thus, the gate electrode of each transistor in the CMOS section and the gate electrode of the DRAM memory cell can be manufactured by a common process. In this case, the second conductive film on the gate electrode of the CMOSFET is entirely removed in the initial stage of the step (h), and the first conductive film is directly patterned by the first gate forming mask. The dimensional shift of the determined lower end portion of the gate electrode with respect to the first gate forming mask is suppressed to be small. That is, the dimensional accuracy of the gate electrode of the CMOSFET can be ensured.
[0007]
Also,High-speed operation can be realized by lowering the resistance of the gate electrode and the source / drain diffusion layers of the CMOSFET.
[0008]
In the method of manufacturing a semiconductor device, after the step (h) and before the step of silicidation, the method further includes the step of forming a protective insulating film for silicidation prevention on the second region. The silicidation of the source / drain diffusion layers can be prevented, and the leakage in the memory cells can be suppressed.
[0009]
In the method for manufacturing a semiconductor device, after the step (f) and before the step (g), a step of forming a protective insulating film for self-contact on the second conductor film; and the step (i). After forming an insulator sidewall on both sides of the gate electrode in the second region, an interlayer insulating film is formed on the substrate, and the source / drain of the second region penetrates the interlayer insulating film. Forming a self-aligned contact that reaches the diffusion layer, whereby the density of the DRAM memory cell can be increased.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
First, the structure of the semiconductor device according to the present embodiment will be described.
[0011]
FIG. 1 is a sectional view showing the structure of the semiconductor device according to the present embodiment. In the semiconductor device according to the present embodiment, a DRAM memory cell portion Rm and a CMOS portion Rc are provided on a P-type silicon substrate 1. In the CMOS portion Rc, a PMOSFET portion Rp and an NMOSFET portion Rn are provided. Is provided. The DRAM memory cell portion Rm, the PMOSFET portion Rp, and the NMOSFET portion Rn are separated by a trench type element isolation insulating film 3.
[0012]
In the DRAM memory cell portion Rm, the gate oxide film 6c and the gate electrode 33 of the transistor in the DRAM memory cell portion Rm are sequentially stacked on the P-type well region 4. The gate electrode 33 of the transistor in the DRAM memory cell portion Rm has a structure in which a lower electrode 33a and an upper electrode 33b are sequentially stacked from below, and an upper surface protective film 91 made of a nitride film is formed on the gate electrode. Is provided. Further, on both sides of the gate electrode 33 of the transistor in the DRAM memory cell portion Rm, the nitride film sidewalls 14 are provided. Further, first and second N-type source / drain diffusion layers 35a and 35b are provided in regions located on both sides of the gate electrode 33 of the transistor in the DRAM memory cell portion Rm in the P-type well region 4 serving as a base. Have been. Further, a first interlayer insulating film 60 is provided on the P-type silicon substrate 1, and a bit line contact penetrating through the first interlayer insulating film 60 and reaching the first N-type source / drain diffusion layer 35a. 61 are formed. On the first interlayer insulating film 60, a bit line 62 connected to a bit line contact 61 is provided. On the first interlayer insulating film 60, a second interlayer insulating film 63 is provided. Further, a capacitance storage contact 68 is formed which penetrates the first and second interlayer insulating films 60 and 63 and reaches the second N-type source / drain diffusion layer 35b. A capacitance storage electrode 70 is provided on the capacitance storage portion contact 68. A capacitor insulating film 71 is formed around the capacitor storage electrode 70, and a plate electrode 72 is formed around the capacitor insulating film 71.
[0013]
In the PMOSFET portion Rp, the gate oxide film 6b and the gate electrode 39 are sequentially stacked on the N-type well region 5 from below. The gate electrode 39 has a structure in which a lower electrode 34b made of a polysilicon film and an upper electrode 16a made of a cobalt silicide film are stacked from below. The nitride film sidewalls 14 are provided on both sides of the lower electrode 34b. Further, a P-type source / drain diffusion layer 18b and an LDD diffusion layer 18a are provided in regions located on both sides of the gate electrode 39 in the N-type well region 5 serving as a base. Further, a cobalt silicide film 16b is formed on the P-type source / drain diffusion layer 18b. Further, the P-type source / drain diffusion layer 18b is electrically connected to a contact plug 20 provided on the upper portion thereof through the first interlayer insulating film 60 via a cobalt silicide film 16b. A wiring 64 is provided on the contact plug 20.
[0014]
In the NMOSFET portion Rn, a gate oxide film 6b and a gate electrode 40 are sequentially stacked on the P-type well region 4 from below. The gate electrode 40 has a structure in which a lower electrode 34a made of a polysilicon film and an upper electrode 16c made of a cobalt silicide film are stacked from below. The nitride film sidewalls 14 are provided on both sides of the lower electrode 34a. Further, N-type source / drain diffusion layers 17b and LDD diffusion layers 17a are provided in regions located on both sides of the lower electrode 34a in the P-type well region 4 serving as a base. On the N-type source / drain diffusion layer 17b, a cobalt silicide film 16d is formed. Further, the N-type source / drain diffusion layer 17b is electrically connected to a contact plug 20 provided on the upper portion thereof through the first interlayer insulating film 60 via a cobalt silicide film 16d. A wiring 64 is provided on the contact plug 20.
[0015]
Next, a manufacturing process of the semiconductor device according to the present embodiment will be described. 2 (a), 2 (b), 3 (a), 3 (b), 4 (a), 4 (b), 5 (a) and 5 (b) FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment.
[0016]
First, in a step shown in FIG. 2A, a protective oxide film 2 having a thickness of about 20 nm is formed on a P-type silicon substrate 1 by thermal oxidation at 900 ° C. Here, the specific resistance of the P-type silicon substrate 1 is 10 to 20 Ω · cm, and the main surface of the P-type silicon substrate 1 is a (100) plane.
[0017]
Next, a protective nitride film is deposited on the protective oxide film 2 to a thickness of about 100 nm by a low pressure CVD method. Thereafter, the protective nitride film and the protective oxide film 2 in the field region are etched by dry etching using the resist film in which the field region is opened as a mask, and further, the dry etching is performed on the P-type silicon substrate 1 in the field region. Then, a trench having a depth of about 400 nm is formed.
[0018]
Next, after a protective oxide film is formed on the inner wall of the trench by thermal oxidation at 900 ° C. to a thickness of about 20 nm, a silicon oxide film is formed on the substrate including the trench by CVD at 800 nm from the bottom of the trench. Deposition is performed until the film thickness becomes about the same. Next, the silicon oxide film is polished by the CMP method until the surface of the protective nitride film is exposed, so that the silicon oxide film is embedded in the trench, and the DRAM memory cell portion Rm, the PMOSFET portion Rp, and the NMOSFET portion Rn are mutually connected. An isolation insulating film 3 to be separated is formed. Thereafter, the protective nitride film is entirely removed using hot phosphoric acid.
[0019]
Next, in the step shown in FIG. 2B, boron ions are implanted into the NMOSFET portion Rn. That is, ion implantation for controlling the threshold voltage (implantation energy: 10 keV, dose: 6 × 10¹²cm^-2), Ion implantation for forming a channel stopper (implantation energy: 200 keV, dose: 6 × 10¹²cm^-2), And ion implantation for forming the P-type well region 4 (implantation energy: 400 keV, dose: 1 × 10 4)^Thirteencm^-2)I do. In addition, boron ions are implanted into the DRAM memory cell portion Rm. That is, ion implantation for controlling the threshold voltage (implantation energy: 10 keV, dose: 3 × 10¹²cm^-2), Ion implantation for forming a channel stopper (implantation energy 200 keV, dose 3 × 10¹²cm^-2), And ion implantation for forming the P-type well region 4 (implantation energy: 400 keV, dose: 1 × 10 4)^Thirteencm^-2)I do. Next, phosphorus ions are implanted into the PMOSFET portion Rp. That is, ion implantation for controlling the threshold voltage (implantation energy: 50 keV, dose: 6 × 10¹²cm^-2), Ion implantation for forming a channel stopper (implantation energy 400 keV, dose 6 × 10¹²cm^-2) And ion implantation for forming the N-type well region 5 (implantation energy: 800 keV, dose: 1 × 10 4)^Thirteencm^-2)I do. Next, a heat treatment (at 900 ° C. for about 30 minutes) is performed to diffuse and activate the impurities in the P-type well region 4 and the N-type well region 5. Further, after removing the protective oxide film 2 by wet etching, a gate oxide film 6 is formed by thermal oxidation at 850 ° C. until the thickness becomes about 5 nm.
[0020]
Next, in a step shown in FIG. 3A, a polycrystalline silicon film 7 is deposited on the entire surface of the gate oxide film 6 by a CVD method until the film thickness becomes about 150 nm. The polycrystalline silicon film 7 becomes a part of the gate electrode of each transistor in the CMOS portion Rc and a part of the gate electrode of the transistor in the DRAM memory cell portion Rm by the steps described below. Next, using a resist film as a mask in the NMOSFET portion Rn and the polycrystalline silicon film 7 in the DRAM memory cell portion Rm, ion implantation of phosphorus as an N-type impurity (implantation energy: 15 keV, dose: 7 × 10^Fifteencm^-2), And using a resist film as a mask in the polycrystalline silicon film 7 of the PMOSFET portion Rp, ion implantation of boron as a P-type impurity (implantation energy: 8 keV, dose: 4 × 10 4).^Fifteencm^-2)I do. Next, after a heat treatment (at 800 ° C. for about 30 minutes) for diffusing the implanted impurities is applied, a gate electrode pattern in each transistor of the CMOS part Rc is formed over the entire surface of the polycrystalline silicon film 7. A nitride film 8 used as a mask is grown by CVD to a thickness of about 50 nm. Next, a resist film Pr1 is formed on the nitride film 8 to cover a region where a gate electrode is to be formed in the CMOS portion Rc.
[0021]
Next, in the step shown in FIG. 3B, the nitride film 8 is dry-etched using the resist film Pr1 as a mask, thereby forming an NMOSFET gate formation mask 31a and a PMOSFET gate formation mask 31b.
[0022]
Next, in the step shown in FIG. 4A, a part of the gate electrode of the transistor in the DRAM memory cell portion Rm is formed on the polycrystalline silicon film 7, the NMOSFET gate forming mask 31a and the PMOSFET gate forming mask 31b. A tungsten silicide film 32 is deposited to a thickness of about 150 nm by a CVD method. Next, a nitride film 11 for a contact etching stopper is deposited on the entire surface of the tungsten silicide film 32 by a CVD method until the film thickness becomes about 150 nm. Thereafter, a resist film Pr2 is formed on the nitride film 11 to form a gate electrode of the transistor in the DRAM memory cell unit Rm.
[0023]
Next, in the step shown in FIG. 4B, after the nitride film 11 is patterned by dry etching using the resist film Pr2 as a mask, the resist film Pr2 is removed. Next, tungsten silicide film 32 and polycrystalline silicon film 7 are etched using upper protective film 91 made of the patterned nitride film as a mask. Thus, the gate electrode 33 of the transistor of the DRAM memory cell portion Rm having the structure in which the lower electrode 33a and the upper electrode 33b are stacked is formed. Further, at this time, the NMOSFET gate forming mask 31a and the PMOSFET gate forming mask 31b serve as a mask for the dry etching of the polycrystalline silicon film 7, whereby the lower electrode 34a of the NMOSFET and the lower electrode 34b of the PMOSFET are simultaneously formed. You.
[0024]
Next, arsenic ion implantation (implantation energy: 10 keV, dose: 1 × 10 4) is performed by using a resist film and a gate electrode in the opening of the NMOSFET portion Rn for forming the LDD diffusion layer 17 a of the NMOSFET portion Rn as a mask.¹⁴cm^-2)I do. Further, in order to form a punch-through stopper of the NMOSFET portion Rn, boron ion implantation (implantation energy of 30 keV, dose of 1 × 10 4) is performed using a resist film having an opening in a region where the punch-through stopper is to be formed as a mask.^Thirteencm^-2)I do. Further, the BF is formed using a resist film and a gate electrode for forming the LDD diffusion layer 18a of the PMOSFET portion Rp as a mask.₂ ⁺Ion implantation (implantation energy 20 keV, dose amount 1 × 10^Thirteencm^-2)I do. Further, in order to form a punch-through stopper of the PMOSFET portion Rp, phosphorus ions are implanted (with an implantation energy of 80 keV and a dose of 1 × 10 4) using a resist film as a mask.^Thirteencm^-2)I do. Further, in order to form the first and second N-type source / drain diffusion layers 35a and 35b of the DRAM memory cell portion Rm, ion implantation of phosphorus (implantation energy 50 keV, dose 1 ×) is performed using a resist film as a mask. 10^Thirteencm^-2)I do.
[0025]
Thereafter, in the step shown in FIG. 5A, a nitride film for a sidewall is deposited on the entire surface of the substrate by a CVD method until the film thickness becomes about 100 nm, and then a nitride film sidewall 14 is formed by dry etching. I do. At this time, the NMOSFET gate forming mask 31a, the PMOSFET gate forming mask 31b and the extra gate oxide film 6 are simultaneously removed by dry etching.
[0026]
Next, arsenic ion implantation (implantation energy: 50 keV, dose: 3 × 10 3) is performed using a resist film for forming the N-type source / drain diffusion layers 17 b of the NMOSFET portion Rn as a mask.^Fifteencm^-2)I do. Further, in order to form the P-type source / drain diffusion layers 18b of the PMOSFET portion Rp, boron ions are implanted (implantation energy 10 keV, dose amount 2 × 10 4) using the resist film as a mask.^Fifteencm^-2)I do. Thereafter, as a heat treatment for activating the impurities, rapid thermal annealing (1000 ° C., 10 seconds) is performed, so that the N-type source / drain diffusion layers 17b of the NMOSFET portion Rn and the P-type of the PMOSFET portion Rp are formed. A source / drain diffusion layer 18b is formed.
[0027]
Next, a protective oxide film 15 is deposited on the entire surface of the substrate by the CVD method to a thickness of about 50 nm, and then a silicide film is formed by wet etching using a resist film in which a region to be silicided is opened as a mask. A part of the protective oxide film 15 in the region to be converted is removed. Next, a cobalt film is deposited on the entire surface of the substrate to a thickness of about 10 nm by a sputtering method, and a short-time heat treatment (600 ° C. for 30 seconds or 800 ° C. for 30 seconds) is performed. To silicide. After that, the unreacted cobalt film is removed by wet etching. Thus, the cobalt silicide films 16d and 16b are formed on the N-type source / drain diffusion layers 17b and the P-type source / drain diffusion layers 18b, and the upper electrodes 16c made of a cobalt silicide film are formed on the lower electrodes 34a and 34b. 16a is formed. By this step, a silicide layer is provided in the source / drain diffusion layer and the gate electrode in the CMOS section Rc. That is, the structure of the PMOSFET portion Rp and the structure of the NMOSFET portion Rn are so-called salicide structures. The protective oxide film 15 prevents the first and second N-type source / drain diffusion layers 35a and 35b from being silicided in the DRAM memory cell portion. Therefore, the junction leak between the P-type well region 4 and the first and second N-type source / drain diffusion layers 35a and 35b can be suppressed.
[0028]
Next, in a step shown in FIG. 5B, the protective oxide film 15 is removed. Next, after depositing the first interlayer insulating film 60 to a thickness of about 1000 nm by the CVD method, the first N-type source / drain diffusion layer 35a of the DRAM memory cell portion Rm is formed by dry etching. Contact holes are formed to reach the N-type source / drain diffusion layers 17b of the NMOSFET section Rn and the P-type source / drain diffusion layers 18b of the PMOSFET section Rp. At this time, in the DRAM memory cell portion, since the upper surface protective film 91 and the nitride film sidewall 14 on the gate electrode serve as stoppers when the first interlayer insulating film 60 is etched, the first N-type source is self-aligned. A self-aligned contact portion 36 is formed by realizing the contact to the drain diffusion layer 35a. Next, tungsten is buried in each contact hole by a CVD method and a CMP method to form a contact plug 20 and a bit line contact 61. Next, after depositing an aluminum alloy film on the first interlayer insulating film 60, this is patterned to form bit lines 62 and wirings 64.
[0029]
Next, a second interlayer insulating film 63 is deposited by a CVD method. Next, after forming the capacitance storage portion contact 68 by the CVD method and the CMP method, the capacitance storage electrode 70 is formed by etching. Next, after depositing a nitride film by a CVD method, a capacitive insulating film 71 is formed by thermal oxidation. Next, a plate electrode 72 is formed by depositing non-doped polysilicon. In this way, a composite LSI including the transistors in the CMOS section Rc and the transistors in the DRAM memory cell section Rm is manufactured.
[0030]
In the present embodiment, the mask 31a for forming the NMOSFET gate and the mask 31b for forming the PMOSFET gate are nitride films, but may be an oxide film or a stacked film of an oxide film and a nitride film.
[0031]
In the present embodiment, the gate electrode 33 of the transistor in the DRAM memory cell portion Rm is a laminated film of a tungsten silicide film and a polycrystalline silicon film, but instead of the tungsten silicide film, a high melting point metal or a high melting point metal silicide is used. It may be a film, a laminated film of a high melting point metal and a high melting point metal nitride film, or a laminated film of a high melting point metal silicide film and a high melting point metal nitride film.
[0032]
In the present embodiment, the resist film Pr2 and the upper surface protection film 91 are used as masks when etching the gate electrode of the transistor in the DRAM memory cell portion Rm. However, the upper surface protection film 91, which is a nitride film, is oxidized. It may be a film or a laminated film of a nitride film and an oxide film.
[0033]
Further, in the present embodiment, only the upper protective film 91 is used as a mask when the lower electrode 33a and the upper electrode 33b serving as the gate electrode 33 of the transistor in the DRAM memory cell portion Rm are formed by etching. Pr2 and the upper surface protection film 91 may be used as a mask.
[0034]
Further, in the present embodiment, the sidewall of the transistor is the nitride film sidewall 14, but instead of the nitride film, an oxide film or a stacked film of an oxide film and a nitride film may be used.
[0035]
Further, in the present embodiment, the lower electrodes 33a, 34b, 34a are made of a polycrystalline silicon film, but may be made of an amorphous silicon film instead of the polycrystalline silicon film.
[0036]
In this embodiment, the gate oxide film 6 may be a nitrided oxide film.
[0037]
In this embodiment, the gate oxide films 6b of the transistors in the CMOS section Rc and the gate oxide films 6c of the transistors in the DRAM memory cell section Rm have the same film type and the same film type, but have different film thicknesses and different films. It may be a seed.
[0038]
The following effects can be obtained by forming a semiconductor device equipped with the transistors of the CMOS unit Rc and the transistors of the DRAM memory cell unit Rm having the above structure.
[0039]
In the present embodiment, the gate electrode of each transistor of the CMOS section Rc and the gate electrode of the DRAM memory cell section Rm can be manufactured on the same substrate by a common process.
[0040]
Further, the tungsten silicide film 32 in the CMOS portion Rc is entirely removed by etching, and the polycrystalline silicon film 7 is directly patterned by the NMOSFET gate forming mask 31a and the PMOSFET gate forming mask 31b, so that the gate length of the CMOSFET is reduced. The dimensional shift of the determined lower electrodes 34a, 34b at the lower ends with respect to the NMOSFET gate forming mask 31a and the PMOSFET gate forming mask 31b is suppressed to a small value. That is, the dimensional accuracy of the gate electrode of the CMOSFET can be ensured.
[0041]
In the present embodiment, the gate electrode of the transistor in the DRAM memory cell portion Rm and the gate electrode of each transistor in the CMOS portion Rc are simultaneously deposited on the film configuration of the gate electrode and the film thickness thereof, which are different from each other. And by etching at the same time. Therefore, unlike the case where the gate electrodes are separately deposited and etched, no extra polysilicon film remains on the side surfaces of the gate electrodes. Therefore, the distance between the gate electrodes is not reduced, and the increase in the density of the memory cell portion is not hindered.
[0042]
In addition, in the present embodiment, in the step shown in FIG. 5A, since the gate electrode 33 of the DRAM memory cell portion Rm is completely covered by the upper surface protective film 91 made of a nitride film and the nitride film sidewall 14, In forming a contact to the first N-type source / drain diffusion layer 35a in the DRAM memory cell portion, a self-aligned contact can be applied. Therefore, the density of the DRAM memory cell can be increased.
[0043]
Further, in each transistor section of the CMOS section Rc, since the lower electrodes 34a and 34b are formed after removing the nitride film 11, the lower electrode 34a of the NMOSFET, the lower electrode 34b of the PMOSFET, and the N-type source / drain diffusion layer 17b are formed. And a salicide process for simultaneously siliciding the P-type source / drain diffusion layers 18b. Therefore, the gate electrodes 39, 40 and the source / drain diffusion layers 17b, 18b of the CMOSFET have low resistance, and high-speed operation can be realized.
[0044]
Further, the protective oxide film 15 prevents the first and second N-type source / drain diffusion layers 35a and 35b from being silicided in the DRAM memory cell portion. Therefore, the junction leak between the P-type well region 4 and the first and second N-type source / drain diffusion layers 35a and 35b can be suppressed.
In order to obtain this effect, only one mask is required compared to the step of forming only the DRAM memory cell portion Rm. Therefore, the gate electrode of the DRAM memory cell and the transistors of the CMOS portion Rc are separately provided. The number of steps and the cost can be greatly reduced as compared with the case where the gate electrode and the gate electrode are deposited and formed.
[0045]
In this embodiment, in the step shown in FIG. 4A, the polycrystalline silicon film 7, the extremely thin NMOSFET gate forming mask 31a and the extremely thin PMOSFET gate forming mask 31b are After depositing the tungsten silicide film 32, a nitride film 11 is further deposited thereon. At this time, since the film thickness of the NMOSFET gate forming mask 31a and the film thickness of the PMOSFET gate forming mask 31b are extremely small, the tungsten silicide film 32 and the nitride film 11 can be uniformly and substantially uniformly deposited on the substrate. it can. Therefore, a resist film Pr2 having substantially the same dimensional accuracy can be formed on the nitride film 11. Therefore, since the accuracy of the photolithography does not decrease, there is no problem such as dimensional variation and lack of pattern when forming the gate pattern of the transistor in the fine DRAM memory cell portion Rm. Therefore, according to the manufacturing method of the present embodiment, even if the gate electrode of each transistor of the CMOS section Rc and the gate electrode of the DRAM memory cell section Rm are manufactured on the same substrate by a common process, high precision and high density can be achieved. The transistors of the DRAM memory cell section Rm and the transistors of the CMOS section Rc with high precision, high performance and high density can be formed.
[0046]
【The invention's effect】
As described above, according to the present invention, the gate electrode of each transistor in the CMOS section Rc and the gate electrode of the DRAM memory cell can be manufactured by a common process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment.
FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment;
FIG. 3 is a sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment;
FIG. 4 is a sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment;
FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the embodiment.
[Explanation of symbols]
1 P-type silicon substrate
2 Protective oxide film
3 Insulating film for element isolation
4 P-type well area
5 N-type well region
6 Gate oxide film
6b Gate oxide film
6c Gate oxide film
7 Polycrystalline silicon film
8 nitride film
11 Nitride film
14 Nitride film sidewall
15 Protective oxide film
16a Upper electrode
16b Cobalt silicide film
16c upper electrode
16d cobalt silicide film
17a LDD diffusion layer
17b N-type source / drain diffusion layer
18a LDD diffusion layer
18b P-type source / drain diffusion layer
20 Contact plug
31a Mask for forming NMOSFET gate
31b PMOSFET gate formation mask
32 Tungsten silicide film
33 Gate electrode
33a lower electrode
33b upper electrode
34a lower electrode
34b lower electrode
35a First N-type source / drain diffusion layer
35b Second N-type source / drain diffusion layer
36 Self-aligned contact part
39 Gate electrode
40 Gate electrode
51 P-type semiconductor substrate
60 First interlayer insulating film
61 bit line contacts
62 bit line
63 Second interlayer insulating film
64 wiring
68 Capacitive storage contact
70 capacitance storage electrode
71 Capacitive insulation film
72 plate electrode
91 Top protective film
Pr1 resist film
Pr2 resist film
Rm DRAM memory cell part
Rc CMOS section
Rp PMOSFET section
Rn NMOSFET section

Claims (3)

(A) dividing the semiconductor substrate into a first region in which a CMOSFET is to be formed and a second region in which a memory cell transistor of a high-density memory is to be formed by element isolation;
(B) forming a first gate insulating film in the first region;
(C) forming a second gate insulating film in the second region;
Forming a first conductor film on the first gate insulating film and the second gate insulating film (d);
After depositing a mask insulating film on the first conductive film, the mask insulating film is patterned to form a first gate forming mask on a region of the first region where a gate electrode is to be formed. (E)
(F) forming a second conductor film having a lower resistance than the first conductor film on the first conductor film and the first gate forming mask;
(G) forming a second gate forming mask on the region where the gate electrode of the second region is to be formed on the second conductor film;
In the first region, the first conductor film is patterned using the first gate formation mask in the first region to form the gate electrode of the CMOSFET, while in the second region, the second electrode is formed. (H) patterning the first and second conductor films using a gate forming mask to form a gate electrode of the memory cell transistor;
Forming (i) a memory cell transistor and a source / drain diffusion layer of a CMOSFET in regions on both sides of each gate electrode in the first and second regions ;
After the step (h), after removing the first gate formation mask in the first region, a step of silicidizing the upper part of the gate electrode and the upper part of the source / drain diffusion layer of the CMOSFET is included. A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 1 ,
After the step (h), before the step of silicidation, a method of manufacturing a semiconductor device, further comprising the step of forming a protective insulating film for silicidation prevention on the second region. The method for manufacturing a semiconductor device according to claim 1 , wherein
After the step (f) and before the step (g), forming a protective insulating film for self-contact on the second conductor film;
After the step (i), after forming an insulator sidewall on both sides of the gate electrode in the second region, an interlayer insulating film is formed on the substrate, and the second insulating film is formed through the interlayer insulating film. Forming a self-aligned contact reaching the source / drain diffusion layer in the region.

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