JP3588951B2 - Microcomputer program change device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer program changing apparatus which can correct a program fixedly stored in a ROM incorporated in a microcomputer after a semiconductor integrated circuit is manufactured, and can operate normally.
[0002]
[Prior art]
2. Description of the Related Art In recent years, microcomputers are often used in electronic devices in order to cope with higher functions and higher performance. Generally, programs that determine the operation of these microcomputers are stored in a read-only memory (hereinafter abbreviated as ROM). In particular, when used in mass-produced equipment such as consumer equipment, a mask ROM in which a program is fixedly installed in a semiconductor integrated circuit manufacturing process is often used because of its low unit price. However, since the mask ROM has a fixed program installed during the manufacturing process, it is not possible to modify the program for reasons such as the occurrence of specification changes or the detection of program errors after manufacturing. I had to discard it. Further, there is a problem in that the only way to add a modification to the program is to manufacture the microcomputer again, which wastes cost and time.
[0003]
In order to solve these problems, some program change devices have conventionally been devised, and by incorporating these devices in a microcomputer, it is possible to correct a program in a microcomputer after manufacturing.
[0004]
FIG. 8 shows a first embodiment of a conventional program change device.
In the figure, 1 is a program counter, 2 is a ROM for storing a program, 31 is a correction address register, 32 is a comparison circuit, 33 is a correction instruction register, 4 is a selection circuit, and 5 is an instruction decoder.
[0005]
Usually, the microcomputer sequentially reads out the instructions on the ROM 2 indicated by the program counter 1 and decodes them by the instruction decoder 5, and then performs the basic operation by executing the microinstructions and the like.
[0006]
In the conventional program changing apparatus, the address where the instruction requiring correction is stored in the correction address register 31 and the corrected instruction is stored in the correction instruction register. The correction address register 31 and the value of the program counter 1 are always compared by the comparison circuit 32. When a match is detected, the selection circuit 4 is switched to the correction instruction register side, and the instruction code stored in the correction instruction register instead of the ROM is read. Instructions are corrected by supplying them to the decoder. The program change device 3a composed of the correction address register 31, the comparison circuit 32, and the correction instruction register 33 is necessary for correcting one instruction stored in one address. A plurality of sets of program change devices 3a to 3n are mounted for correction.
[0007]
FIG. 9 shows a second embodiment of the conventional program change device.
In the figure, 1 is a program counter, 2 is a ROM in which a program is stored, 31 is a modified address register, 32 is a comparison circuit, 34 is an interrupt vector register, 5 is an instruction decoder, and 6 is a RAM.
[0008]
In the conventional program changing apparatus, an address at which an instruction requiring correction is stored is stored in the correction address register 31, a series of correction programs are stored in the RAM 6, and a start address of the correction program is stored in the interrupt vector register 34. The value of the modified address register 31 and the value of the program counter 1 are always compared by the comparing circuit 32, and when a match is detected, an interrupt request signal is generated. When the CPU receives the interrupt request signal, the CPU saves the current program counter value and the like on the stack, reads the address of the interrupt branch destination from the interrupt vector register 34, and sets it in the program counter 1. In this case, the start address of the correction program stored in the RAM is stored in the interrupt vector register, and the correction program is executed as the interrupt processing program.
[0009]
FIG. 10 shows a third embodiment of the conventional program changing apparatus.
In the figure, 1 is a program counter, 2 is a ROM storing a program, 31 is a modified address register, 32 is a comparison circuit, 35 is a branch address register, 4 is a selection circuit, 5 is an instruction decoder, and 36 is a branch instruction generation circuit. It is.
[0010]
In the conventional program changing apparatus, an address at which an instruction requiring correction is stored in the correction address register 31, a series of correction programs is stored in the RAM 6, and a start address of the correction program is stored in the branch address register 35. The value of the modified address register 31 and the value of the program counter 1 are always compared by the comparison circuit 32. When a match is detected, the selection circuit 4 is switched to the branch instruction generation circuit side, and the branch instruction generated by the branch instruction generation circuit instead of the ROM. Supply the code to the instruction decoder. The branch instruction generating circuit generates an instruction operation code of the branch instruction and a value stored in the branch address register as an operand following the instruction operation code. That is, the CPU decodes and executes the branch instruction to the start address of the correction program, and as a result, executes the correction program.
[0011]
[Problems to be solved by the invention]
However, the conventional program changing apparatus has the following problems.
[0012]
In the first conventional example, an instruction that can be corrected by a set of program change devices including a comparison circuit 32, a correction address register 31, and a correction instruction register 33 is an instruction code (for example, in an 8-bit microcomputer) corresponding to one address. 1-byte instruction code). Since the program change device and the correction instruction code have a one-to-one correspondence, it is necessary to implement a plurality of sets of program change devices in order to make it possible to correct a plurality of instruction codes. Usually, about 8 to 16 sets are mounted in many cases. A general 8-bit microcomputer has 16-bit to 24-bit address lines, and a 16-bit microcomputer has 24-bit to 32-bit address lines. That is, the comparison circuit and the correction address register of the program change device need to have the same bit width as the address line, and the same number of correction instruction registers (the bit width per set is generally an 8-bit microcomputer). (8 bits, 16 bits in the case of a 16-bit microcomputer), and the problem of increasing the circuit scale occurs when a plurality of sets are provided. On the contrary, there is also a problem that the size of the correction program is limited by the number of sets of the program change device to be mounted.
[0013]
In the second conventional example, since the correction program is executed using a general interrupt, the program counter 1 and a program status word PSW (not shown) are saved on a stack. Therefore, it is necessary to secure a stack area for this, and there is a problem that the RAM is wasted. Also, time is required for the evacuation operation to the stack, which causes a time loss until execution. This can be fatal for speedy processes. Further, in recent microcomputers, a technique of prefetching an instruction is generally used to increase the processing speed, and a prefetch address for reading a ROM and an instruction for executing an instruction actually executed by a CPU are generally used. It is different from the address. Therefore, the prefetch address and the value of the correction address register 31 are compared by the comparison circuit 32, and if they match, an interrupt is generated, and even if the correction program is executed, the instruction is not correctly corrected. Is generated. This is because, for example, if the instruction being executed when a match is detected is a branch instruction, the instruction specified by the correction address register may not be executed. Therefore, in a microcomputer using the instruction prefetching technique, comparison with an execution address is necessary. However, in general, a register holding an instruction execution address is often not mounted, and the execution of the program is not performed because of a program change device. Providing the address register causes a problem of increasing the circuit scale.
[0014]
In the third conventional example, the correction address register 31 and the program counter 1 are compared by a comparison circuit 32, and a branch instruction is generated when they match, and a branch instruction generation circuit 36 for generating a specific branch instruction is used. However, there is a problem that the circuit scale is increased. Further, the following problem occurs.
[0015]
In recent microcomputers, the basic unit of the bit length of the instruction code may be smaller than the bit width read from the ROM in order to reduce the code size of the instruction. FIG. 7 shows an example of the format of the reduced instruction code. For example, assume that the figure is a 16-bit microcomputer. In a general 16-bit microcomputer, the basic unit of the bit length of the instruction code is 16 bits, and the total bit length of the instruction including the instruction operation code and the subsequent operand is a multiple of 16 bits. In a general 16-bit microcomputer, instructions are read from the ROM with a 16-bit width, so that a boundary between consecutive instructions cannot exist in the middle of the read ROM data. However, in a microcomputer with a reduced instruction code, the instruction operation code is 16 bits (2 bytes M0 to M1) and the operand is 24 bits (3 bytes M2 to M4) as shown by the instruction n in FIG. There are certain cases. In this case, the total bit length of the instruction code is 40 bits (5 bytes of M0 to M4) and is not an integral multiple of 16 bits (2 bytes). In such a case, if the reading from the ROM is 16 bits wide, there may be a case where a boundary between consecutive instructions exists in the middle of the read ROM data as shown in FIG. 7B. The same can be said for an 8-bit microcomputer or a 32-bit microcomputer. In the conventional method in which only the instruction fetch address in the ROM is compared and the instruction code is replaced with the code of the branch instruction, it is impossible to generate the branch instruction using the middle of the read data as the instruction boundary. This is because the final code of the instruction immediately before the correction instruction bundled with the branch instruction cannot be uniquely determined.
[0016]
The present invention solves the aforementioned problems,
(1) Minimize the increase in circuit scale,
(2) Relax the size limit of the patch,
(3) Minimize the time delay before starting the execution of the correction program,
(4) Even a microcomputer using the instruction prefetching technique can directly specify an address of a correction portion,
(5) By providing a microcomputer program changing device that can directly specify the address of a correction point even in a microcomputer using a reduced instruction, if the instruction fixedly stored in the ROM can be corrected after the microcomputer is manufactured. The purpose is to tighten.
[0017]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, a program changing apparatus according to the present invention includes a corrected address register, a comparing circuit, and a coincidence detecting means, compares a ROM fetch address with a value of the corrected address register by a comparing circuit, and decodes the result. When the match is detected by the match detector by the match detector, the instruction decoder obtains the start address of the correction program from a predetermined address on the RAM by executing a microinstruction, and executes the program in the RAM. Is branched to the start address of the correction program. This
(1) Minimize the increase in circuit scale,
(2) Relax the size limit of the patch,
(3) Minimize the time delay before starting the execution of the correction program,
(4) Even a microcomputer using the instruction prefetching technique can directly specify an address of a correction portion,
(5) It is possible to obtain a microcomputer program changing device that can directly specify the address of a correction portion even with a microcomputer using a reduction instruction.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
The invention according to claim 1 of the present invention comprises a corrected address register, a comparing circuit, and coincidence detecting means, compares the ROM fetch address with the value of the corrected address register by the comparing circuit, and sends the result to the instruction decoder. In the instruction decoder, when a match is detected in the comparison circuit by the match detection means, the start address of the correction program is obtained from a predetermined address on the RAM by executing the microinstruction by executing the microinstruction, and the execution of the program is executed by the correction The branch is made to the start address, and has the effect of minimizing the circuit scale required for realizing the program change device.
[0019]
According to a second aspect of the present invention, the coincidence signal from the comparison circuit is held until the timing at which the instruction is decoded. In the microcomputer using the instruction prefetching technique, the execution address is different from the ROM read address. Even in such a case, there is an effect that correction can be performed at the time of execution of the corresponding instruction simply by comparing with the ROM read address.
[0020]
The invention according to claim 3 of the present invention includes a plurality of sets of corrected address storage means and comparison circuits, and has an effect that a program at a plurality of locations can be corrected.
[0021]
According to a fourth aspect of the present invention, a plurality of sets of corrected address storage means and a comparison circuit are provided, and a signal obtained by decoding a coincidence output signal of the comparison circuit is held until the instruction decoding timing. In addition to the effects of claims 1 to 3, there is an effect that the circuit scale required for holding the coincidence signal can be minimized even when a plurality of correction points are provided.
[0022]
The invention described in claim 5 of the present invention transfers the coincidence signal in synchronization with the transfer of the instruction code, and has an effect that the transfer timing of the coincidence signal and the instruction code transfer timing can be shared.
[0023]
The invention according to claim 6 of the present invention is such that the coincidence signal is directly input to the command decoder, and has an effect that the coincidence can be easily detected.
[0024]
According to a seventh aspect of the present invention, a specific value is set in an instruction register and a micro address pointer input to an instruction decoder as a means for detecting coincidence, and an input signal to the instruction decoder is set. Has the effect that coincidence can be detected without increasing the
[0025]
According to an eighth aspect of the present invention, the decoded value of the coincidence signal is directly used as a part of the RAM address, and the circuit size of the address generation circuit as the start address acquisition means of the correction program is increased. It has the effect that it can be easily realized without causing it.
[0026]
According to the ninth aspect of the present invention, a match is detected at the timing of decoding an instruction requiring correction. Even in a microcomputer using a reduced instruction code, a ROM read address and Has the effect that the corresponding instruction can be modified.
[0027]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing one embodiment of the present invention, wherein 1 is a program counter, 2 is a ROM storing a program, 31 is a modified address register, 32 is a comparison circuit, 5 is an instruction decoder, and 6 is an instruction decoder. RAM and 7 are coincidence signals. A plurality of sets of the program change device including the correction address register 31 and the comparison circuit 32 are mounted to correct a plurality of instructions (3a to 3n). The program counter 1 and the ROM 2, the comparison circuit 32 and the RAM 6 are connected by an address bus, and the ROM 2 and the command decoder 5 and the RAM 6 are connected by a data bus.
[0028]
The correction address register 31 stores an address of a correction portion (a defect portion) of a series of instruction codes stored in the ROM 2. When the corrected portion extends over a plurality of lines, the address where the first instruction code of the corrected portion is stored is stored.
[0029]
The comparison circuit 32 compares the address value stored in the corrected address register with the address value output from the program counter 1 to the address bus in order to read the instruction code stored in the ROM 2, and detects a match between the two address values. The coincidence signal 7 is output.
[0030]
Normally, the microcomputer sequentially reads data addressed by the program counter 1 from the ROM 2, decodes the instruction operation code in the read data with the instruction decoder 5, and activates the microinstruction to execute various operations. In a general microcomputer, the ROM 2 and the RAM 6 are often arranged in the same memory space, and information necessary for execution of a CPU (not shown) is stored and held in a RAM built in the microcomputer. In many cases, the instruction code on the RAM 6 can be executed by the program counter 1 indicating an address on the RAM 6.
[0031]
Next, a method for correcting an instruction fixedly stored in the ROM by the present program changing apparatus will be described.
(1) When a program fixedly stored in the ROM 2 needs to be corrected due to a defect or a change in specifications, an address where the corrected instruction code or the first instruction code of a series of corrected programs is stored. The value is stored in the correction address register 31.
(2) The correction program is stored in the RAM 6.
(3) The start address of the correction program stored in the RAM 6 is stored at a predetermined address on the RAM 6.
[0032]
The above operation is performed by reading necessary data from an external nonvolatile memory or the like at the time of reset start of the microcomputer via a serial interface or a parallel interface generally provided in the microcomputer.
[0033]
These operations are performed in an initialization program which is started after a reset start of the microcomputer, depending on the state of data previously stored at a specific address of the external nonvolatile memory on the ROM 2 and the state of the terminals of the microcomputer. What is necessary is just to incorporate the program which is started.
[0034]
If the operation of reading the instruction code to be corrected is performed during the operation of the microcomputer having the above setting, the comparison circuit 32 detects the coincidence with the address value stored in the modified address register, and outputs a coincidence signal.
[0035]
The coincidence signal is input to the instruction decoder 5, the coincidence is detected by the coincidence signal detecting means provided in the instruction decoder 5 at the timing of decoding the instruction operation code, and the instruction operation code to be decoded is the corrected instruction code. When it detects something, it activates a micro instruction that performs the following operation.
(1) Obtain the start address value of the correction program from a predetermined address on the RAM 6.
(2) Unconditionally branch to the acquired start address value and set the address value in the program counter 1.
[0036]
Thereafter, the correction program stored in the RAM 6 is read and executed by sequentially incrementing (or decrementing) the program counter 1.
[0037]
A series of program corrections is completed by executing a branch instruction to an address on the ROM 2 at the end of the correction program.
[0038]
A program change device including a correction address register 31 and a comparison circuit 32 can correct one program per set. Therefore, by providing a plurality of sets (3a to 3n) of program change devices, it is possible to correct programs at a plurality of locations. Usually, it is sufficient to mount about 2 to 4 sets.
[0039]
In general, as the number of sets of program change devices increases, the number of coincidence signals also increases, and the circuit size of the coincidence signal holding means and the coincidence detection means in the instruction decoder increases. Therefore, the following measures are taken to minimize the increase in the circuit scale.
[0040]
FIG. 2 is a block diagram showing the program change device and the coincidence signal output means according to the present invention. In this figure, three sets of program change devices (2 ² -1), the number of sets of program change devices is the maximum (2 ⁿ -1) The same applies to the case of a set.
[0041]
In FIG. 2A, 3a to 3c are three sets of program change devices, 31a to 31c are modified address registers, 32a to 32c are comparison circuits, 7a to 7c are match signals, 8 is a decoder, 81 and 82 are match decode signals. It is.
[0042]
The addresses of the ROMs where the instruction codes requiring modification are stored are set in the modification address registers 31a and 31b, and the comparison with the instruction fetch addresses output on the address bus is performed using the comparison circuits 32a to 32c. . When the value of the instruction fetch address matches the value of the correction address register, the comparison circuits 32a to 32c output match signals 7a to 7c. It goes without saying that data can be written to and read from the correction address register by executing instructions from the microcomputer.
[0043]
The decoder 8 receives the match signals 7a to 7c and converts them into match decode signals 81 and 82 according to a truth table shown in FIG. Specifically, when no comparison circuit outputs a coincidence signal, (coincidence decoding signal 82, coincidence decoding signal 81) = (0, 0) as a coincidence decoding signal, and the comparison circuit 32a outputs a coincidence signal. (0, 1) when the comparison circuit 32b is outputting a coincidence signal, and (1, 1) when the comparison circuit 32c is outputting a coincidence signal. I do. Although the truth table does not assume that the same correction address is specified in the plurality of correction address registers 31a to 31c due to the nature of the program changing device, a plurality of coincidence signals 7a and 7b are simultaneously output if necessary. In this case, the priority may be set as the coincidence decode signal. For example, it is conceivable to give priority to the coincidence output of the comparison circuit having the smaller number. In this case, when the comparison circuits 32a and 32b output the coincidence signal, the coincidence decode signal of (0, 1) ((coincidence decode signal 82, coincidence decode signal 81)) may be output. The order of priorities is arbitrary. The assignment of decoding can also be arbitrarily configured, but it is preferable that all outputs be the same (all 0s or all 1s) when none of the comparison circuits output a coincidence signal.
[0044]
By generating the coincidence decode signal as described above, the holding means and the coincidence detecting means in the instruction decoder can be easily configured as described later.
[0045]
FIG. 3 shows one embodiment of the instruction decoder of the present invention.
In the drawing, reference numeral 80 denotes n coincidence decode signals. In the case of the embodiment shown in FIG. 9 is a PLA, 91 is an AND part constituting the PLA, 92 is an OR part, A0 is an instruction register, A1 is an instruction queue, B0 and B1 are coincidence decode signal holding means for holding a coincidence decode signal at the same timing as an instruction, D is a control signal for controlling each section of the microcomputer to execute a command.
[0046]
This embodiment shows an instruction decoder in a microcomputer using an instruction prefetching technique. Normally, the instruction code specified and read by the prefetch address is stored in the instruction queue A1 via the data bus. Next, at the instruction decoding timing, the instruction code stored in the instruction queue is transferred to the instruction register. The instruction code stored in the instruction register is input to the AND section 91 of the PLA, decoded, and the control signal D for controlling each section of the microcomputer is output from the OR section 92 of the PLA, thereby executing each instruction.
[0047]
The following operations are performed to change the program.
(1) A desired address is compared with a prefetch address by a program changing device as shown in the embodiment of FIG. 2, and a match decode signal 80 obtained by decoding a match signal output when a match occurs is prefetched. The stored instruction code is stored in the coincidence decode signal holding means B1 at the same time as being stored in the instruction queue.
(2) Next, the instruction code is transferred to the coincidence decode signal holding means B0 at the same time as the instruction code is transferred to the instruction register, and the coincidence decode signal is held at the same time as the instruction code is input to the AND section 91 of the PLA at the instruction decoding timing. The coincidence decode signal stored in the means B0 is input to the AND section 91 of the PLA.
(3) When the coincidence decode signal is input to the PLA ((0, 1), (1, 0), (1, 1) in the embodiment of FIG. 2), the following operation is performed irrespective of the instruction code type. Start the microprogram to be executed.
[0048]
(A) Obtain the start address value of the correction program from a predetermined address on the RAM.
[0049]
(B) Unconditionally branch to the acquired start address value and set the address value in the program counter.
(4) The correction program stored in the RAM is read and executed by sequentially incrementing (or decrementing) the program counter.
(5) A series of program corrections is completed by executing a branch instruction to an address on the ROM at the end of the correction program.
[0050]
In this embodiment, the coincidence decode signal is held until the instruction decoding timing and input to the AND section of the PLA. However, the undecoded match signal may be held until the instruction decoding timing and directly input.
[0051]
Further, in the present embodiment, a configuration is adopted in which n coincidence decode signals are inputted to the AND section 91 of the PLA as they are. However, in the decoder of the embodiment of FIG. Therefore, the configuration can be further simplified by inputting n coincidence decode signals to the OR gate and consolidating them into one signal.
[0052]
FIG. 4 shows another embodiment of the instruction decoder of the present invention.
In the drawing, reference numeral 80 denotes n coincidence decode signals. In the case of the embodiment shown in FIG. 9 is a PLA, 91 is an AND part constituting the PLA, 92 is an OR part, A0 is an instruction register, A1 is an instruction queue, B0 and B1 are coincidence decode signal holding means for holding a coincidence decode signal at the same timing as an instruction, C is a micro address pointer, D is a control signal for controlling each part of the microcomputer to execute a command, and E is a micro address control signal.
[0053]
In a general microcomputer, a microcode technology is often used for an instruction decoder. In this case, a PLA is used as hardware, and an instruction register value and a microaddress pointer value are input to an AND section input of the PLA. The micro address pointer is determined by the micro address control signal according to the previous state. That is, the execution state of each instruction is determined by the instruction register value and the micropointer value.
[0054]
In this embodiment, the following operation is performed as in the embodiment of FIG.
(1) A desired modified address is compared with a prefetch address, and a match decode signal 80 obtained by decoding a match signal output in the case of a match is decoded at the same time when the prefetched instruction code is stored in the instruction queue. It is stored in the signal holding means B1.
(2) Next, at the same time when the instruction code is transferred to the instruction register, the instruction code is transferred to the coincidence decode signal holding means B0 to indicate a match ((0, 1), (1, 0) in the embodiment of FIG. 2). (1, 1)) sets the instruction register and the micro address pointer to specific values, and inputs the values to the AND unit 91 of the PLA.
(3) In the PLA, when the specific value is input, a microprogram for executing the following operation is started.
[0055]
(A) Obtain the start address value of the correction program from a predetermined address on the RAM.
[0056]
(B) Unconditionally branch to the acquired start address value and set the address value in the program counter.
(4) The correction program stored in the RAM is read and executed by sequentially incrementing (or decrementing) the program counter.
(5) A series of program corrections is completed by executing a branch instruction to an address on the ROM at the end of the correction program.
[0057]
As a method of setting the instruction register and the micro address pointer to specific addresses, each may be configured by a register with a set or reset and controlled by a coincidence decode signal, or an AND gate or an OR gate may be added to each output. May be inserted and gated with the coincidence decode signal.
[0058]
Since the embodiment shown in FIGS. 3 and 4 has means for holding the coincidence decode signal until the timing of decoding the instruction code, the address where the change instruction is stored may be simply compared with the prefetch address, and the prefetch address is the normal address. Since the data is output to the bus, it is only necessary to compare the corrected address register with the address bus, so that the configuration of the program changing device can be simplified.
[0059]
In the above embodiment, the configuration of the instruction decoder is realized by using the PLA, but it is needless to say that the configuration can be realized by using a random logic.
[0060]
Also, the case where the instruction queue at the time of instruction prefetch has one stage has been described.
[0061]
In the program change device of the present invention, in the execution cycle of the
・ Acquisition of the start address value of the correction program from a predetermined address on the RAM
・ Branch unconditionally to the acquired start address value and set the address value in the program counter
FIG. 5 shows an embodiment of a means for generating an address on the RAM for storing the start address of the correction program at this time.
[0062]
In the figure, reference numeral 8 denotes a decoder, and B0 and B1 are coincidence decode signal holding means for holding a coincidence decode signal at the same timing as the instruction, which is the same as a part of the embodiment shown in FIGS.
[0063]
FIG. 6 shows the RAM space for storing the start address of the correction program and the bit configuration of the address signal.
[0064]
In FIG. 6A, F0 to F2 are start address storage areas of the correction program corresponding to the three sets of program change devices.
[0065]
In this embodiment, for simplicity, the address space of the RAM for storing the correction program is two. ¹⁶ Although it is assumed that the number of bytes (address signal lines is 16 bits) and the number of program change devices are three as shown in FIG. 2, the number of sets of address signal lines and program change devices can be considered in any case.
[0066]
Since the address signal lines in the RAM space are 16 bits, three sets of 16-bit (2 bytes) areas for storing the start address of the correction program are secured as shown in FIG. In the present embodiment, the correction program start address of the program changing device 3a in FIG. 2A is set in the area F0 (X'0202 'and X'0203'), and the area F1 (X'0204 'and X'0205') is similarly set. The correction program start address of the program change device 3b is stored in the address (address), and the correction program start address of the program change device 3c is stored in the area F2 (addresses X'0206 'and X'0207').
[0067]
A general 16-bit microcomputer can access the RAM space in 16-bit units. In this case, in order to obtain the start address of the correction program, the data of the address X'202 ', the address X'204', or the address X'0206 'is simply obtained according to any of the program changers 3a to 3c which output the coincidence signal. What is necessary is just to read in 16-bit units. As shown in FIG. 6B, the upper 15 bits (bit 3 to bit 15) of the 16-bit address signal line are assigned a fixed value b'0000000100000 'to the next two bits (bit 1 to bit 15) as shown in FIG. 2) may output a coincidence decode signal according to the decoder of FIG. 2B, and the last bit (bit 0) may output a fixed value b'0 '. As shown in FIG. 5, the coincidence decode signal only needs to output the data stored in the coincidence decode signal holding means B0 to the address bus at the start address acquisition timing of the correction program, and the circuit can be easily formed.
[0068]
When only 8-bit data can be accessed at a time as in an 8-bit microcomputer, the 8-bit data may be obtained twice, and the least significant bit (bit 0) in FIG. This can be solved by outputting b'0 'in the first address acquisition and outputting b'1' in the second address acquisition.
[0069]
In this embodiment, the match decode signal is output as two bits, bit 1 and bit 2. However, the configuration of the correction program start address storage area, the address bit width of the RAM space, and the bit width of data that can be handled by the microcomputer (4 bits, 8 bits, 16 bits, 32 bits, 64 bits, etc.) may be output to an arbitrary bit position.
[0070]
Also, according to the configuration of the decoder in FIG. 2B, when the coincidence decode signal is b'00 ', the assignment is made when none of the program change devices outputs the coincidence signal. Therefore, addresses X'0200' to X'0201 'are unassigned. However, it goes without saying that if the configuration of the decoder changes, the address of the correction program start address storage area to be allocated also changes.
[0071]
FIG. 7 shows the format of the reduced instruction code. For example, assume that the figure is a 16-bit microcomputer. In this case, the basic unit of the reduced instruction code is 8 bits, and the instruction n has an instruction operation code of 16 bits (2 bytes of M0 to M1) and an operand of 24 bits (3 bytes of M2 to M4). . It is also assumed that the subsequent instruction n + 1 has the same instruction operation code of 16 bits (N0 to N1 2 bytes) and the operand of 16 bits (N2 to N3 2 bytes). In this case, assuming that the instruction n is stored from the address X'0100 'as shown in FIG. 7B, the final code M4 of the instruction n is stored at the address X'0104' and the instruction n is stored at the address X'0105 '. The first code N0 of n + 1 will be stored. Since a general 16-bit microcomputer fetches an instruction in units of 16 bits, addresses X'0104 'and X'0105' are fetched simultaneously as data at address X'0104 '.
[0072]
For example, if the instruction to be modified is instruction n + 1, X'0104 'is stored in the modified address register. Therefore, when the boundary of the instruction is not on the boundary of the instruction fetch unit, the address of the fetch data including the head of the instruction to be corrected is specified in the correction address register.
[0073]
In the above-described example, the case of a 16-bit microcomputer is used. However, even though it is an 8-bit microcomputer such as an 8-bit microcomputer MN101 series manufactured by Matsushita Electronics, a basic unit of the instruction code format is 4 bits. There is also a computer. The same applies to microcomputers of 32 bits or 64 bits or more.
[0074]
When the instruction to be modified is the instruction n + 1 and the modified address register value is X'0104 'as in the example of FIG. 7, the final code M4 of the instruction n and the instruction n + 1 of the instruction n + 1 are stored in the instruction queue A1 shown in FIG. The head code N0 is stored, and the match decode holding means B1 stores a match decode signal. The microcomputer using the reduced instruction code has means for extracting and storing only the instruction operation code of the corresponding instruction when storing the instruction operation code from the instruction queue in the instruction register in the instruction decoder. Zu).
[0075]
Therefore, it is sufficient to extract only the instruction operation code from the instruction queue A1 and transfer the coincidence decode signal from the coincidence decode signal holding means B1 to B0 at the timing of storing the instruction operation code in the instruction register A0. , By executing the microprogram
(1) Obtaining the start address value of the correction program from a predetermined address on the RAM
(2) Branch unconditionally to the acquired start address value and set that address value in the program counter
And the program can be similarly changed.
[0076]
Therefore, according to the present invention, the instruction can be modified in the execution cycle of the instruction to be modified irrespective of the format of the instruction code.
[0077]
【The invention's effect】
As described above, according to the present invention, the correction address storage means for storing the start address of the correction program stored in the RAM at a predetermined address in the RAM and storing the address of a desired correction portion is provided. A comparison circuit that compares an instruction with a fetch address and an address stored in a correction address storage unit, and outputs a match signal when they match, and a circuit that decodes match outputs of the plurality of comparison circuits; The instruction decoder of the CPU includes means for detecting that the comparison circuit has output the coincidence signal. When the coincidence signal is detected, the instruction decoder executes a microinstruction to execute a correction program from a predetermined address of the RAM. By providing a configuration that obtains the start address and branches the execution of the program to the start address of the correction program in the RAM,
(1) Minimize the increase in circuit scale,
(2) Relax the size limit of the patch,
(3) Minimize the time delay before starting the execution of the correction program,
(4) Even a microcomputer using the instruction prefetching technique can directly specify an address of a correction portion,
(5) It is possible to realize an excellent microcomputer program changing device that can directly specify the address of a correction portion even with a microcomputer using a reduction instruction.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an entire embodiment.
FIG. 2 is a diagram showing an embodiment of a program change device and a coincidence signal output means;
FIG. 3 is a diagram showing a first embodiment of an instruction decoder;
FIG. 4 is a diagram showing a second embodiment of the instruction decoder;
FIG. 5 is a diagram showing an address generation unit.
FIG. 6 is a diagram showing a correction program start address storage area.
FIG. 7 shows an example of a reduced instruction code.
FIG. 8 is a diagram showing a first conventional example.
FIG. 9 is a diagram showing a second conventional example.
FIG. 10 is a diagram showing a third conventional example.
[Explanation of symbols]
1 Program counter
2 ROM
3, 3a to 3n program change device
31 Correction address register
32 comparison circuit
33 Modification Instruction Register
34 Interrupt Vector Register
35 Branch address register
36 Branch instruction generation circuit
4 Selection circuit
5 Command decoder
6 RAM
7, 7a, 7b coincidence signal
8 decoder
81, 82 Match decode signal
9 PLA
91 AND section of PLA
92 OR section of PLA
A0 instruction register
A1 instruction queue
B0, B1 coincidence decode signal holding means
C Micro address pointer
D control signal
E Micro address control signal
F0, F1, F2 Correction program start address storage area

Claims (9)

A microcomputer in which a read-only memory (ROM), a random access memory (RAM), and a central processing unit (CPU) for performing calculations and controls are integrated in the same chip, and a command stored in the ROM is modified. A program changing device of a microcomputer for branching execution from the corrected portion to a corrected program stored in the RAM,
A correction program is stored in the RAM, and the start address is stored at a predetermined address in the RAM;
Correction address storage means for storing an address of a desired correction portion of the ROM;
A comparison circuit for comparing a read address to the ROM for fetching an instruction with an address stored in the correction address storage means and outputting a match signal when the addresses match;
The instruction decoder of the CPU includes means for detecting that the comparison circuit has output a coincidence signal, and upon detecting the coincidence signal, the instruction decoder starts execution of a microinstruction to start a correction program from a predetermined address of the RAM. A program change device for a microcomputer, which acquires an address and branches execution of the program to a start address of a correction program in the RAM. When the fetch address of the instruction matches the corrected address storage means, the instruction code read from the ROM and the coincidence signal of the comparison circuit are simultaneously input to the CPU, and the CPU decodes the instruction code and the coincidence signal to decode the instruction code. It is characterized by comprising means for holding until the timing, and when decoding the instruction code, the instruction decoder of the CPU is provided with means for detecting that the instruction code is an instruction code to be corrected based on the input coincidence signal. A program changing device for a microcomputer according to claim 1. 3. The microcomputer according to claim 1, wherein a plurality of sets of corrected address storage means and comparison circuits are provided. A microcomputer in which a read-only memory (ROM), a random access memory (RAM), and a central processing unit (CPU) for performing calculations and controls are integrated in the same chip.
A program change device of a microcomputer that, when a correction portion occurs in an instruction stored in the ROM, branches execution from the correction portion to a correction program stored in the RAM,
A correction program is stored in the RAM, and the start address is stored at a predetermined address in the RAM;
A correction address storage means for storing an address of a desired correction portion of the ROM, an instruction fetch address, and an address stored in the correction address storage means are compared, and a match signal is output if they match. A maximum of 2 ⁿ -1 sets of comparison circuits (n is a natural number);
A decoding circuit for generating, from the 2 ⁿ -1 maximum coincidence outputs, n number of coincidence decode signals indicating which of the comparison circuits coincides with each other, and identifying one set of states of the coincidence decode signals; State (all signals are 0 or 1) is set to a state where all the comparison circuits do not match,
The coincidence decode signal is input to the CPU simultaneously with the instruction code, and the CPU includes means for holding the instruction code and the coincidence decode signal until decoding timing of the instruction code,
At the time of decoding the instruction code, the instruction decoder of the CPU detects from the input match signal that the instruction code is an instruction code to be corrected, and stores the start address of the correction program from the match decode signal. Means for generating a predetermined address in the RAM,
Upon detecting that the correction is necessary, the instruction decoder obtains the start address of the correction program from the predetermined address of the RAM generated by the address generation means by executing the microinstruction, and executes the program in the RAM. A program change device for a microcomputer, wherein the program branches to a start address of a correction program in the microcomputer. As means for holding the instruction code and the coincidence decode signal according to claim 4 until decoding timing of the instruction code,
The CPU includes an instruction register for storing an instruction code to be decoded and an instruction queue for storing at least one or more stages of prefetched instruction codes. A program changing device for a microcomputer, wherein the program is transferred in synchronization with the program. Inputting a coincidence decode signal to the instruction decoder simultaneously with the instruction code as means for detecting the instruction code to be corrected according to claim 4;
The instruction decoder obtains the start address of the correction program from a predetermined address in the RAM irrespective of the instruction code when a coincidence decode signal indicating the instruction code to be corrected is input, and executes the program in the RAM. And a micro-instruction for executing a branch to a start address of a correction program in the microcomputer. A microcomputer for inputting at least an output of an instruction register and an output of a micro address pointer to an instruction decoder of a CPU, wherein the instruction code is a means for detecting an instruction code to be corrected according to claim 4. When a matching decode signal indicating that the instruction code is to be corrected when stored in the instruction register is input, a specific value is set in the instruction register and the micro address pointer, and the instruction decoder decodes the specific value. A program change device for acquiring a start address of a correction program from a predetermined address of the RAM, and executing a microinstruction for branching execution of the program to a start address of the correction program in the RAM. A means for generating a predetermined address in the RAM in which a start address of the correction program according to claim 4 is stored, wherein a coincidence decode signal input to a CPU is output to a specific n bits of a RAM address. Characteristic program changing device for microcomputer. The tone of the instruction code composed of the instruction operation code and the operand following it is an integer multiple of 1 / n (n = 2 or 4) of the bit width of the data to be fetched at a time, and the boundaries of successive instruction codes are fetched simultaneously. A microcomputer that may be located in the middle of the data
The corrected address storage means stores the address of the ROM where the head of the instruction operation code of the instruction requiring correction exists,
Inputting a coincidence decode signal indicating that the corrected address storage means and the instruction fetch address coincide with each other to the CPU simultaneously with the fetch data in which the head of the instruction operation code exists;
The CPU includes means for holding the coincidence decode signal until the timing of decoding the instruction code requiring correction,
When decoding the instruction operation code extracted from the fetch data including the beginning of the instruction code requiring correction, the instruction decoder of the CPU detects that the instruction code is the instruction code to be corrected based on the input match signal. With
Upon detecting that the correction is necessary, the instruction decoder obtains the start address of the correction program from the predetermined address of the RAM by executing the microinstruction, and executes the program to the start address of the correction program in the RAM. A microcomputer program changing device characterized by branching.

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