JP3590763B2 - Digital modulation circuit, digital demodulation circuit, and digital modulation / demodulation circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital signal transmission device using a plurality of variable-band carriers, and more particularly to a digital signal transmission device capable of easily changing the transmission speed and the number of carriers in a digital signal transmission device employing a plurality of carrier transmissions. About.
[0002]
[Prior art]
FIG. 11 shows a configuration example of a conventional digital modulation circuit. In the figure, reference numerals 21, 22, 23, and 24 denote serial-parallel conversion circuits, reference numerals 25, 26, 27, and 28 denote switches, reference numerals 29, 30, 31, and 32 denote modulation circuits, reference numeral 33 denotes a frequency multiplexing circuit, and reference numeral 34 is a control circuit. The configuration example shown in the figure is a configuration example in the case where the number of input ports is up to 4 ports and the number of carriers is up to 4 carriers.
[0003]
The signals input to the input ports # 1 to # 4 are input to the serial / parallel conversion circuits 21 to 24. In each of the serial / parallel conversion circuits 21 to 24, the input signal is converted into parallel signals of up to four systems and input to the switches 25 to 28. However, if there is an input signal from a specific port in the switches 25 to 28, it cannot be input from another port. The switches 25 to 28 output any one input signal of the serial / parallel conversion circuits 21 to 24 to the modulation circuits 29 to 32 under the control of the control circuit 34.
[0004]
The control circuit 34 controls the switches 25 to 28 according to the information of the carriers assigned to the input ports # 1 to # 4 in advance, and distributes the outputs of the serial / parallel conversion circuits 21 to 24 to predetermined modulation circuits 29 to 32. . The modulation circuits 29 to 32 modulate the input signal and output it to the frequency multiplexing circuit 33. The frequency synthesizing circuit 33 synthesizes the signals input from the modulation circuits 29 to 32 in terms of frequency and outputs them. FIG. 13 shows an example of an output spectrum from the frequency multiplexing circuit 33.
[0005]
Next, FIG. 12 shows a configuration example of a conventional digital demodulation circuit. In the figure, reference numeral 36 is a frequency demultiplexing circuit, reference numerals 37, 38, 39, and 40 are demodulation circuits, reference numerals 41, 42, 43, and 44 are switches, reference numerals 45, 46, 47, and 48 are parallel-serial conversion circuits, 35 is a control circuit. The configuration example shown in the figure is a configuration example in a case where the number of output ports is up to 4 ports and the number of carriers is up to 4 carriers.
[0006]
For example, an example in which a frequency-multiplexed signal as shown in FIG. 13 is input will be described. The input signal is input to the frequency demultiplexing circuit 36. In the frequency demultiplexing circuit 36, the frequency-multiplexed signal is demultiplexed, converted into a baseband signal, and then input to the demodulation circuits 37 to 40. The demodulation circuits 37 to 40 demodulate the input signal. The demodulation circuit 37 outputs to the switch 41, the demodulation circuit 38 outputs to the switch 42, the demodulation circuit 39 outputs to the switch 43, and the demodulation circuit 40 outputs to the switch 44. The switches 41 to 44 are controlled by the control circuit 35 and output to any of the parallel / serial conversion circuits 45 to 48, respectively. The parallel / serial conversion circuits 45 to 48 perform parallel / serial conversion. The parallel / serial conversion circuit 45 is the output port # 1, the parallel / serial conversion circuit 46 is the output port # 2, the parallel / serial conversion circuit 47 is the output port # 3, and the parallel / serial conversion. The circuit 48 outputs to the output port # 4.
[0007]
Such a digital modulation circuit and a digital demodulation circuit can be configured as a digital modulation / demodulation circuit by configuring both circuits as one device.
[0008]
[Problems to be solved by the invention]
In the conventional digital modulation / demodulation circuit configured as described above, multi-carrier transmission can be realized only when the number of input ports and the number of carriers are the same. Therefore, for example, as shown in FIG. 10, when the frequency arrangement of the carriers is omission, it is not possible to insert the carriers using the unused frequency band portion to make the multicarrier, and the frequency use efficiency is remarkably reduced. become worse. In addition, the bandwidth allocated to each port is fixed, and it is difficult for one system to mix services with different transmission rates or to provide services with different transmission rates for each port.
[0009]
In addition, it is necessary to increase or decrease the circuit configuration in accordance with the increase or decrease in the number of ports, and it takes time and expense to change the circuit in accordance with the change in the number of ports.If the number of ports increases, the circuit scale increases. , The cost will be huge.
[0010]
The present invention has been made in view of such a background, and a digital modulation / demodulation circuit capable of easily responding to an increase or decrease in the number of ports and capable of suppressing an increase in circuit size even when the number of ports is increased. The purpose is to provide. The present invention provides a multi-carrier and multi-rate modem capable of changing a transmission rate for each port and allocating a plurality of different speed carriers to one port, and coping with a mixture of services having different transmission rates and a variable transmission rate. It is an object of the present invention to provide a digital modulation / demodulation circuit capable of performing such operations.
[0011]
[Means for Solving the Problems]
The digital modulation circuit of the present invention divides a frequency band used for the communication, generates a carrier processing number as an identifier of each of the divided areas, and indicates a port indicating an input port corresponding to the carrier processing number. A processing number is generated, and an input signal is used as a transmission signal at a predetermined carrier frequency in accordance with the correspondence between the carrier processing number and the port processing number.
[0012]
Therefore, by changing this correspondence, an arbitrary input signal can be made a transmission signal of an arbitrary carrier frequency by a simple procedure. Also, by associating a plurality of carrier processing numbers with one port processing number, the transmission speed can be set arbitrarily. At this time, it is possible to arbitrarily set that one allocated transmission band is divided and used by a plurality of signals. Thereby, it is possible to cope with a mixture of services having different transmission rates and a variable transmission rate.
[0013]
In addition, although it has been described that the port processing number is generated after the carrier processing number is generated, the port processing number may be generated first, and then the carrier processing number may be generated.
[0014]
In the digital demodulation circuit of the present invention, an output port is assigned corresponding to a carrier frequency, and this correspondence is indicated by a carrier processing number and a port processing number. In accordance with this correspondence, the split received signal is demodulated and output from the output port. The digital modulation circuit and the demodulation circuit of the present invention can be combined into one digital modulation / demodulation circuit.
[0015]
Accordingly, the digital modulation circuit, digital demodulation circuit, and digital modulation / demodulation circuit of the present invention can easily cope with an increase or decrease in the number of ports, and can suppress an increase in circuit scale even when the number of ports increases. Further, it is possible to provide a multi-carrier and multi-rate modem capable of changing a transmission rate for each port and allocating a plurality of different-speed carriers to one port to cope with a mixture of services having different transmission rates and a variable transmission rate. it can. In addition, it is possible to efficiently use a satellite communication line at a plurality of transmitting stations, and to realize a communication in which a bandwidth is programmably changed with a simple configuration, and to change a transmission speed according to the number of ports and a radio wave environment.
[0016]
That is, a first aspect of the present invention is a digital modulation circuit, which is characterized by a means for generating a timing signal of a predetermined cycle, and a frequency used for the communication every time the timing signal is generated. Means for sequentially generating a carrier processing number as an identifier of each area obtained by dividing the band for each of the areas, and an input port assigned to the area indicated by the carrier processing number each time the carrier processing number is generated. Means for sequentially generating a port processing number to be indicated, means for sequentially reading an input signal at an input port corresponding to the port processing number whenever the port processing number is generated, and sequentially modulating the read input signal. There is a modulating means for processing and a means for frequency-multiplexing the modulated signal modulated by the modulating means.
[0017]
The frequency multiplexing means receives the modulation signal, generates a transmission signal of a predetermined carrier frequency according to a correspondence relationship between the carrier processing number and the port processing number of the modulation signal, and Frequency multiplexing means.
[0018]
A predetermined parameter and an internal signal used for modulation processing are set in the modulating means in accordance with a correspondence relationship between the carrier processing number and the port processing number, and the predetermined value corresponding to the carrier processing number and / or the port processing number is set. It is preferable to include first memory means in which the information of the parameters and the information of the internal signal are stored. Thereby, predetermined parameters and internal signals can be set promptly by inputting the carrier processing number and / or the port processing number. Further, it is desirable to have a second memory means for temporarily storing the transmission signal up to the multiplex timing.
[0019]
Further, a configuration may be employed in which a port processing number is generated first, and then a carrier processing number is generated. That is, means for generating a timing signal having a predetermined period, means for sequentially generating a port processing number indicating an input port in which the input order of the input signal is determined in advance for each generation of the timing signal, and generation of the port processing number Means for sequentially generating a carrier processing number as an identifier of each area obtained by dividing the frequency band used for the communication allocated to the port processing number for each of the areas, and for each occurrence of the port processing number, If there is an input signal at the input port corresponding to the port processing number, a means for sequentially reading the input signal, a modulating means for sequentially modulating the read input signal, and a frequency multiplexing of the modulated signal modulated by the modulating means And means for performing the operation.
[0020]
A second aspect of the present invention is a digital demodulation circuit, which is characterized by means for demultiplexing a frequency-multiplexed received signal for each different carrier frequency, and generating a timing signal having a predetermined period. Means for sequentially generating a carrier processing number as an identifier of each area obtained by dividing the frequency band used for the communication every time the timing signal is generated, for each of the areas, Means for sequentially generating a port processing number indicating an output port assigned to the area indicated by the carrier processing number, and in accordance with the correspondence between the port processing number and the carrier processing number every time the port processing number is generated. Demodulating means for sequentially demodulating the received signal demultiplexed by the demultiplexing means; and receiving signal demodulated by the demodulating means. Some at and means for outputting to the output port assigned to the carrier frequency of the received signal.
[0021]
In the demodulation means, predetermined parameters and internal signals used for demodulation processing are set according to the correspondence relationship between the carrier processing number and the port processing number, and the predetermined parameter corresponding to the carrier processing number and / or the port processing number is set. It is desirable to have a third memory means in which the information of the parameters and the internal signal are stored. Thereby, predetermined parameters and internal signals can be set promptly by inputting the carrier processing number and / or the port processing number. Further, it is desirable to have a fourth memory means for temporarily storing the reception signal.
[0022]
Further, a configuration may be employed in which a port processing number is generated first, and then a carrier processing number is generated. That is, means for demultiplexing a frequency-multiplexed received signal for each different carrier frequency, means for generating a timing signal of a predetermined period, and an output port in which the output order of the received signal is determined in advance for each generation of the timing signal Means for sequentially generating a port processing number indicating a port processing number, and a carrier processing number as an identifier of each area obtained by dividing the frequency band used for the communication allocated to the port processing number every time the port processing number is generated. Means for sequentially generating the area, and for each occurrence of the port processing number, sequentially demodulates the received signal demultiplexed by the demultiplexing means in accordance with the correspondence between the port processing number and the carrier processing number. Demodulating means, and the received signal demodulated by the demodulating means is assigned to a carrier frequency of the received signal. It may be configured and means for outputting the force port.
[0023]
A third aspect of the present invention is a digital modulation / demodulation circuit comprising at least one digital modulation circuit of the present invention.
[0024]
A fourth aspect of the present invention is a digital modulation / demodulation circuit comprising at least one digital demodulation circuit of the present invention.
[0025]
A fifth aspect of the present invention is a digital modulation / demodulation circuit comprising at least one digital modulation circuit of the present invention and at least one digital demodulation circuit of the present invention.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
The configurations of the digital modulation circuit and the digital demodulation circuit according to the embodiment of the present invention will be described with reference to FIGS. 1, 8, 2, and 9. 1 and 8 are block diagrams of a digital modulation circuit according to an embodiment of the present invention. 2 and 9 are block diagrams of the digital demodulation circuit according to the embodiment of the present invention.
[0027]
As shown in FIG. 1, the digital modulation circuit of the present invention includes a time slot generating circuit 8 for generating a time slot processing number which is a timing signal of a predetermined period, and a frequency used for the communication every time the time slot processing number is generated. A carrier number generating circuit 7 for sequentially generating a carrier processing number as an identifier of each area obtained by dividing the band for each of the areas, and a carrier processing number assigned to the area indicated by the carrier processing number every time the carrier processing number is generated. And a port number generating circuit 6 for sequentially generating a port processing number indicating the input port, and for each generation of the port processing number, if there is an input signal at the input port # 1 to # 5 corresponding to the port processing number, this is sequentially performed. A parallel-to-serial conversion circuit 1 for reading, a modulation circuit 2 for sequentially modulating the read input signal, and a modulation process by the modulation circuit 2. Characterized in that a frequency multiplexing circuit 3 which frequency multiplexing modulated signal.
[0028]
The frequency multiplexing circuit 3 receives the modulation signal, generates a transmission signal of a predetermined carrier frequency in accordance with the correspondence between the carrier processing number and the port processing number of the modulation signal, and frequency-multiplexes the transmission signal. I do.
[0029]
A predetermined parameter and an internal signal used for modulation processing are set in the modulation circuit 2 in accordance with the correspondence between the carrier processing number and the port processing number, and the predetermined parameter corresponding to the carrier processing number and / or the port processing number is set. And information of the internal signal are stored in the memory 4. That is, the modulation circuit 2 outputs a predetermined input signal at a predetermined timing according to the correspondence between the carrier processing number and the port processing number. As an example of realizing this operation, a configuration using a shift register can be considered. In this case, a signal used for shifting the shift register corresponds to an internal signal, Combine with shift register Tap coefficients correspond to parameters. Further, a memory 5 for temporarily storing the transmission signal up to the multiplex timing is provided.
[0030]
As shown in FIG. 8, a time slot generating circuit 8 which changes the positional relationship between the port number generating circuit 6 and the carrier number generating circuit 7 and generates a time slot processing number which is a timing signal of a predetermined period, A port number generating circuit 6 for sequentially generating port processing numbers indicating input ports # 1 to # 5 in which the input order of an input signal is determined in advance each time a slot processing number is generated; A carrier number generating circuit 7 for sequentially generating a carrier processing number as an identifier of each area obtained by dividing the frequency band used for the communication allocated to the processing number for each of the areas; A serial-to-serial conversion circuit 1 for sequentially reading input signals from input ports # 1 to # 5 corresponding to the port processing number, if any; A modulation circuit 2 sequentially modulates an input signal, it may be configured to include a frequency multiplexing circuit 3 which frequency-multiplexed modulated signal modulated treated by the modulation circuit 2.
[0031]
As shown in FIG. 2, the digital demodulation circuit of the present invention generates a frequency demultiplexing circuit 9 for demultiplexing a frequency-multiplexed received signal for each different carrier frequency, and generates a time slot processing number which is a timing signal of a predetermined cycle. A time slot generation circuit 16 and a carrier number generation circuit for sequentially generating a carrier processing number as an identifier of each area obtained by dividing the frequency band used for the communication for each of the time slot processing numbers. 15, a port number generation circuit 14 for sequentially generating port processing numbers indicating output ports # 1 to # 5 allocated to the area indicated by the carrier processing number each time the carrier processing number is generated, and a port processing number Every time the frequency demultiplexing circuit 9 generates the port processing number and the carrier processing number. A demodulation circuit 10 that sequentially demodulates the received signals that have been demultiplexed, and a serial / parallel that outputs the received signals demodulated by the demodulation circuit 10 to output ports # 1 to # 5 assigned to the carrier frequency of the received signals. A conversion circuit 11 is provided.
[0032]
In the demodulation circuit 10, predetermined parameters and internal signals used for demodulation processing are set according to the correspondence between the carrier processing number and the port processing number, and the predetermined parameters corresponding to the carrier processing number and / or the port processing number are set. And information of the internal signal are stored in the memory 13. That is, the demodulation circuit 10 outputs a predetermined reception signal at a predetermined timing according to the correspondence between the carrier processing number and the port processing number. As an example of implementing this operation, a configuration using a shift register can be considered. In this case, a signal used for shifting the shift register corresponds to an internal signal, Combine with shift register Tap coefficients correspond to parameters. Further, a memory 12 for temporarily storing the reception signal is provided.
[0033]
Further, as shown in FIG. 9, a frequency division circuit 9 for changing the positional relationship between the port number generation circuit 14 and the carrier number generation circuit 15 to separate the frequency-multiplexed received signal for each different carrier frequency, A time slot generating circuit 16 for generating a time slot processing number which is a timing signal of a cycle; and a port processing for indicating output ports # 1 to # 5 in which the output order of the reception signal is determined in advance each time the time slot processing number is generated. A port number generating circuit 14 for sequentially generating a number, and a carrier processing number as an identifier of each area obtained by dividing the frequency band used for the communication allocated to the port processing number every time the port processing number is generated. And a carrier number generation circuit 15 that is sequentially generated for the region, and the port processing number for each occurrence of the port processing number. A demodulation circuit 10 for sequentially demodulating the received signal demultiplexed by the frequency demultiplexing circuit 9 in accordance with the correspondence with the carrier processing number; and a demodulation circuit 10 for converting the received signal demodulated by the demodulation circuit 10 to the carrier frequency of the received signal. And a serial-to-parallel conversion circuit 11 for outputting to the output ports # 1 to # 5 assigned to.
[0034]
The digital modulation circuit and the digital demodulation circuit according to the present invention may be configured as a digital modulation / demodulation circuit including at least one digital modulation circuit according to the present invention, or may be configured as a digital modulation / demodulation circuit including at least one digital demodulation circuit according to the present invention. It may be configured as a circuit, or may be configured as a digital modulation / demodulation circuit including at least one digital modulation circuit according to the present invention and at least one digital demodulation circuit according to the present invention.
[0035]
Hereinafter, embodiments of the present invention will be described in more detail.
[0036]
In FIG. 1, reference numeral 1 denotes a parallel-to-serial conversion circuit, reference numeral 2 denotes a modulation circuit, reference numeral 3 denotes a frequency synthesis circuit, reference numerals 4 and 5 denote memories, reference numeral 6 denotes a port number generation circuit, reference numeral 7 denotes a carrier number generation circuit, and reference numeral 8 Is a time slot generation circuit. This configuration example is a configuration example in a case where the number of input ports is up to 5 ports and the number of carriers is up to 16 carriers. FIG. 3 is a diagram showing a spectrum of a carrier. As shown in FIG. 3, carrier numbers # 1 to # 16 are assigned to 16 carriers having different frequencies, respectively.
[0037]
The carrier number generating circuit 7 outputs a carrier number in response to an input from the time slot generating circuit 8. The port number generation circuit 6 outputs a port number based on the input from the carrier number generation circuit 7. The memory 4 reads or writes the internal signals and parameters of the modulation circuit 10 for the input ports under the control of the carrier processing number and / or port processing number generated by the carrier number generation circuit 7 and / or the port number generation circuit 6. . The memory 5 reads or writes a signal for performing the frequency multiplexing process of the frequency multiplexing circuit 3 for the input port under the control of the time slot processing number generated by the time slot generating circuit 8.
[0038]
Here, the time slot processing number is a number sequentially assigned to N time slots in one cycle generated by the time slot generation circuit 8 from the beginning of the cycle. For example, when 16 time slots are generated in one cycle, the processing numbers are # 1 to # 16, which are assigned in order from the first time slot in the cycle, and return to # 1 again in the 17th time slot. .
[0039]
The baseband signals input to the input ports # 1 to # 5 are input to the parallel / serial conversion circuit 1. The parallel-serial conversion circuit 1 sequentially reads signals input from the five input ports # 1 to # 5 from a port number that matches the port number input from the port number generation circuit 6, and serially parallels the signals to one system. Convert and output. The output from the parallel-to-serial conversion circuit 1 is input to the modulation circuit 2.
[0040]
The modulation circuit 2 is controlled by the signal input from the parallel / serial conversion circuit 1, the carrier processing number output from the carrier number generation circuit 7 and / or the port processing number output from the port processing number generation circuit 6, and The internal signals and parameters of the modulation circuit 2 are read or written. The output signal from the modulation circuit 2 is input to the frequency multiplexing circuit 3.
[0041]
The frequency multiplexing circuit 3 is controlled by a time slot processing signal generated from the time slot generating circuit 8 and reads or writes a signal for performing the frequency multiplexing processing of the frequency multiplexing circuit 3 from the memory 4 while inputting or outputting an input signal. The output is multiplexed in frequency. The frequency multiplexing circuit 3 is described in the document "Kazuhiro Tanabe," A study of a variable transmission rate modulator / demodulator using a seamless multi-rate filter bank ", 1999 IEICE Communications Society Conference B-3-29". The same operation as the operation example is performed, and the input signal is frequency-multiplexed and output. That is, the carrier frequency is determined for each time slot, and the carrier frequency of the input signal is determined by which input signal is transmitted in which time slot. A plurality of input signals having the determined carrier frequency are frequency-multiplexed.
[0042]
4 to 7 show examples of the output spectrum of the configuration circuit. In the examples of FIGS. 4 to 7, five input ports # 1 to # 5 are allocated to 16 time slots and 16 types of carriers having different frequencies. In the figure, P represents a port processing number, C represents a carrier processing number, and T represents a time slot processing number.
[0043]
In the example of FIG. 4, the time slot processing numbers # 1 to # 8 for eight time slots are allocated to the input signal of the input port # 1, and the carriers of the frequency of the carrier processing numbers # 1 to # 8 are allocated. . As a result, the input signal of the input port # 1 is given a transmission speed for eight time slots. In this example, the input port # 1 uses one signal as an input signal using eight time slots.
[0044]
A time slot processing number # 9 for one time slot is allocated to the input signal of the input port # 2, and a carrier having a frequency of the carrier processing number # 9 is allocated. A time slot processing number # 10 for one time slot is allocated to the input signal of the input port # 3, and a carrier having a frequency of the carrier processing number # 10 is allocated.
[0045]
To the input signal of the input port # 4, time slot processing numbers # 11 and # 12 for two time slots are allocated, and carriers of frequencies of carrier processing numbers # 11 and # 12 are allocated. As a result, the input signal of the input port # 4 is given a transmission speed of two time slots. In this example, the input port # 4 uses one signal as an input signal using two time slots.
[0046]
To the input signal of the input port # 5, time slot processing numbers # 13 to # 16 for four time slots are allocated, and carriers having frequencies of carrier processing numbers # 13 to # 16 are allocated. As a result, the input signal of input port # 5 is given a transmission speed of four time slots. In this example, the input port # 5 uses one signal as an input signal using four time slots.
[0047]
In the example of FIG. 5, the time slot processing numbers # 1 and # 2 for two time slots are assigned to the input signal of the input port # 1, and carriers of frequencies of the carrier numbers # 1 and # 2 are assigned. As a result, the input signal of the input port # 1 is given a transmission rate of two time slots. In this example, the input port # 1 divides a time slot into two, and uses two signals as input signals with time slot processing numbers # 1 and # 2.
[0048]
To the input signal of the input port # 2, time slot processing numbers # 3 to # 6 for four time slots are allocated, and carriers having frequencies of carrier processing numbers # 3 to # 6 are allocated. As a result, the input signal of the input port # 2 is given a transmission speed of four time slots. In this example, the input port # 2 divides a time slot into two, and uses two signals as input signals with time slot processing numbers # 3 and # 4 and # 5 and # 6.
[0049]
To the input signal of the input port # 3, time slot processing numbers # 7 and # 8 for two time slots are allocated, and carriers of frequencies of the carrier processing numbers # 7 and # 8 are allocated. As a result, the input signal of the input port # 3 is given a transmission speed of two time slots. In this example, the input port # 3 divides a time slot into two, and uses two signals as input signals with time slot processing numbers # 7 and # 8.
[0050]
To the input signal of the input port # 4, time slot processing numbers # 9 to # 12 for four time slots are allocated, and carriers having frequencies of carrier processing numbers # 9 to # 12 are allocated. As a result, the input signal of the input port # 4 is given a transmission speed of four time slots. In this example, the input port # 4 uses one time signal as an input signal using four time slots.
[0051]
To the input signal of the input port # 5, time slot processing numbers # 13 to # 16 for four time slots are allocated, and carriers having frequencies of carrier processing numbers # 13 to # 16 are allocated. As a result, the input signal of input port # 5 is given a transmission speed of four time slots. In this example, the input port # 5 divides a time slot into two, and uses two signals as input signals with time slot processing numbers # 13 and # 14 and # 15 and # 16.
[0052]
In the example of FIG. 6, the time slot processing numbers # 1 to # 16 for 16 time slots are allocated to the input signal of the input port # 1, and the carriers of the frequency of the carrier processing numbers # 1 to # 16 are allocated. . As a result, the input signal of the input port # 1 is given a transmission speed of 16 time slots. In this example, the input port # 1 uses one signal as an input signal using 16 time slots.
[0053]
In the example of FIG. 7, the time slot processing numbers # 1 to # 3 for three time slots are assigned to the input signal of the input port # 1, and the carriers of the frequencies of the carrier processing numbers # 7, # 8, and # 13 are assigned. Is assigned. As a result, the input signal of the input port # 1 is given a transmission rate of three time slots. In this example, the input port # 1 uses two signals as input signals with carrier numbers # 7 and # 8 and # 13.
[0054]
To the input signal of the input port # 2, time slot processing numbers # 4 to # 7 for four time slots are allocated, and carriers of frequencies of carrier processing numbers # 9 to # 12 are allocated. As a result, the input signal of the input port # 2 is given a transmission speed of four time slots. In this example, the input port # 2 uses one signal as an input signal using four time slots.
[0055]
To the input signal of the input port # 3, time slot processing numbers # 8 to # 10 for three time slots are allocated, and carriers of frequencies of the carrier processing numbers # 14 to # 16 are allocated. As a result, the input signal of input port # 3 is given a transmission speed of three time slots. In this example, input port # 3 uses two signals as input signals for carrier numbers # 14, # 15 and # 16.
[0056]
To the input signal of the input port # 4, time slot processing numbers # 11 to # 13 for three time slots are allocated, and carriers of frequencies of carrier numbers # 1, # 5, and # 6 are allocated. As a result, the input signal of input port # 4 is given a transmission speed of three time slots. In this example, the input port # 4 uses two signals as input signals with carrier numbers # 1, # 5, and # 6.
[0057]
To the input signal of the input port # 5, time slot processing numbers # 14 to # 16 for three time slots are allocated, and carriers having frequencies of carrier processing numbers # 2 to # 4 are allocated. As a result, the input signal of the input port # 5 is given a transmission speed of three time slots. In this example, the input port # 5 uses two signals as input signals with carrier processing numbers # 2, # 3, and # 4.
[0058]
In FIG. 2, reference numeral 9 denotes a frequency demultiplexing circuit, reference numeral 10 denotes a demodulation circuit, reference numerals 12 and 13 denote memories, reference numeral 14 denotes a port number generation circuit, reference numeral 15 denotes a carrier number generation circuit, reference numeral 16 denotes a time slot generation circuit, and reference numeral 11 is a serial-parallel conversion circuit. This configuration example is a configuration example in which the number of output ports is up to 5 ports and the number of carriers is up to 16 carriers. The carrier number generation circuit 15 outputs a carrier processing number in response to an input from the time slot generation circuit 16. The port number generation circuit 14 outputs a port processing number in response to an input from the carrier number generation circuit 15. The memory 12 supplies a signal for performing the demultiplexing process of the frequency demultiplexing circuit 9 for the input ports # 1 to # 5 to a carrier processing number and / or a port processing generated by the carrier number generation circuit 15 and / or the port number generation circuit 14. Reading or writing is controlled by the number.
[0059]
The memory 13 reads or writes the internal signals and parameters of the demodulation circuit 10 for the input ports # 1 to # 5 under the control of the time slot processing number generated by the time slot generation circuit 16.
[0060]
The signals multiplexed in frequency as shown in FIGS. 4 to 7 are input to the frequency demultiplexing circuit 9. In the frequency demultiplexing circuit 9, the input signal is frequency-demultiplexed while reading or writing the internal signal of the frequency demultiplexing circuit 9 from the memory 12 under the control of the time slot processing number output from the time slot generation circuit 16. Is going. For example, the frequency demultiplexing circuit 9 is described in the document “Kazuhiro Tanabe,“ Study of Variable Transmission Rate Modulator / Demodulator Using Seamless Multirate Filter Bank ”, 1999 IEICE Communications Society Conference B-3-29”. The same operation as the operation example is performed. That is, the carrier frequency is determined for each time slot, and the carrier frequency of the received signal is determined by which time slot outputs which received signal. In this way, demultiplexing is performed for each carrier frequency. The output signal from the frequency demultiplexing circuit 9 is input to the demodulation circuit 10. The demodulation circuit 10 is controlled by the input signal from the frequency demultiplexing circuit 9, the carrier processing number output from the carrier number generation circuit 15, and the port processing number output from the port number generation circuit 14. The demodulation process is performed while reading or writing the internal signal. An output signal from the demodulation circuit 10 is input to the serial-parallel conversion circuit 11. The serial-to-parallel conversion circuit 11 performs serial-to-parallel conversion of the input one-system signal according to the port processing number output from the port number generation circuit 14, and outputs the signal to each of the output ports # 1 to # 5. I have.
[0061]
In this embodiment, the digital signal processing has been described as being processed by the digital signal processing circuit. The processing of the digital signal is not limited to this, and all or some of the functions of each digital circuit may be software processing using a CPU or a DSP. In this case, the program for software processing includes a multi-carrier and multi-rate modulation circuit, a multi-carrier and multi-rate demodulation circuit, a multi-carrier and multi-rate modulation circuit for a regenerative repeater, or a multi-carrier and multi-rate demodulation circuit for regenerative relay. Are stored in a recording medium such as a ROM constituting
[0062]
As another embodiment, as shown in FIG. 8 and FIG. 9, a configuration in which the positional relationship between the carrier number generation circuits 7 and 15 and the port number generation circuits 6 and 14 can be exchanged can be adopted.
[0063]
【The invention's effect】
As described above, according to the present invention, it is possible to easily cope with an increase or decrease in the number of ports, and to suppress an increase in the circuit scale even when the number of ports increases. Further, it is possible to provide a multi-carrier and multi-rate modem capable of changing a transmission rate for each port and allocating a plurality of different-speed carriers to one port to cope with a mixture of services having different transmission rates and a variable transmission rate. it can.
[0064]
As a result, a plurality of bands of different speeds can be assigned to one input port, and batch modulation and demodulation of different speed signals can be performed. Further, the wireless communication line can be efficiently used by a plurality of transmitting stations, and communication for changing the bandwidth in a programmable manner can be realized by a simple configuration device, and the transmission speed can be changed according to the number of ports and the radio wave environment.
[Brief description of the drawings]
FIG. 1 is a block diagram of a digital modulation circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram of a digital demodulation circuit according to an embodiment of the present invention.
FIG. 3 is a diagram showing an example of the spectrum of a carrier in an example of the present invention.
FIG. 4 is a diagram showing an example of an output spectrum in the embodiment of the present invention.
FIG. 5 is a view showing an example of an output spectrum in the embodiment of the present invention.
FIG. 6 is a view showing an example of an output spectrum in the embodiment of the present invention.
FIG. 7 is a view showing an example of an output spectrum in the embodiment of the present invention.
FIG. 8 is a block diagram of a digital modulation circuit according to another embodiment.
FIG. 9 is a block diagram of a digital demodulation circuit according to another embodiment.
FIG. 10 is a diagram showing an example regarding the frequency efficiency of a conventional device.
FIG. 11 is a block diagram of a conventional digital modulation circuit.
FIG. 12 is a block diagram of a conventional digital demodulation circuit.
FIG. 13 is a diagram showing a spectrum example of a conventional carrier.
[Explanation of symbols]
1,45-48 parallel / serial conversion circuit
2, 29-32 modulation circuit
3,33 frequency multiplexing circuit
4, 5, 12, 13 memory
6, 14 port number generation circuit
7, 15 Carrier number generation circuit
8, 16 time slot generation circuit
9,36 frequency demultiplexing circuit
10, 37-40 demodulation circuit
11, 21-24 Serial-parallel conversion circuit
25-28, 41-44 Switch
34, 35 control circuit

Claims (12)

Means for generating a timing signal of a predetermined cycle;
Means for sequentially generating a carrier processing number as an identifier of each area obtained by dividing the frequency band used for the communication for each occurrence of the timing signal for each of the areas,
Means for sequentially generating a port processing number indicating an input port assigned to the area indicated by the carrier processing number for each occurrence of the carrier processing number;
Means for sequentially reading out an input signal at an input port corresponding to the port processing number whenever the port processing number is generated,
A modulating means for sequentially modulating the read input signal;
Means for frequency-multiplexing the modulated signal modulated by the modulating means. The means for frequency multiplexing,
A means for inputting the modulation signal and generating a transmission signal of a predetermined carrier frequency in accordance with the correspondence between the carrier processing number and the port processing number according to the modulation signal,
2. A digital modulation circuit according to claim 1, further comprising means for frequency-multiplexing the transmission signal. The modulating means includes a shift register, and according to the correspondence between the carrier processing number and the port processing number, a tap coefficient combined with the shift register and a signal used for shifting the shift register are set,
2. The digital modulation circuit according to claim 1, further comprising first memory means for storing information on the tap coefficient and a signal used for shifting the shift register corresponding to the carrier processing number and / or the port processing number. 3. The digital modulation circuit according to claim 1, further comprising second memory means for temporarily storing the transmission signal up to the multiplex timing. Means for generating a timing signal of a predetermined cycle;
Means for sequentially generating a port processing number indicating an input port in which the input order of the input signal is determined in advance each time the timing signal is generated;
Means for sequentially generating a carrier processing number as an identifier of each area obtained by dividing the frequency band used for the communication allocated to the port processing number for each of the areas, each time the port processing number is generated,
Means for sequentially reading out an input signal, if any, at an input port corresponding to the port processing number every time the port processing number is generated;
A modulating means for sequentially modulating the read input signal;
Means for frequency-multiplexing the modulated signal modulated by the modulating means. Means for splitting the frequency-multiplexed received signal for each different carrier frequency,
Means for generating a timing signal of a predetermined cycle;
Means for sequentially generating a carrier processing number as an identifier of each area obtained by dividing the frequency band used for the communication for each occurrence of the timing signal for each of the areas,
Means for sequentially generating a port processing number indicating an output port assigned to the area indicated by the carrier processing number each time the carrier processing number is generated;
Demodulating means for sequentially demodulating the received signal demultiplexed by the demultiplexing means in accordance with the correspondence between the port processing number and the carrier processing number for each occurrence of the port processing number;
Means for outputting a reception signal demodulated by the demodulation means to an output port assigned to a carrier frequency of the reception signal. The demodulation means includes a shift register, and according to the correspondence between the carrier processing number and the port processing number, a tap coefficient combined with the shift register and a signal used for shifting the shift register are set,
7. The digital demodulation circuit according to claim 6, further comprising third memory means for storing information on said tap coefficient and a signal used for shifting said shift register corresponding to said carrier processing number and / or said port processing number. 8. The digital demodulation circuit according to claim 6, further comprising fourth memory means for temporarily storing the reception signal. Means for splitting the frequency-multiplexed received signal for each different carrier frequency,
Means for generating a timing signal of a predetermined cycle;
Means for sequentially generating a port processing number indicating an output port in which the output order of the reception signal is determined in advance each time the timing signal is generated;
Means for sequentially generating a carrier processing number as an identifier of each area obtained by dividing the frequency band used for the communication allocated to the port processing number for each of the areas, each time the port processing number is generated,
Demodulation means for sequentially demodulating the received signal demultiplexed by the demultiplexing means according to the correspondence between the port processing number and the carrier processing number for each occurrence of the port processing number,
Means for outputting a reception signal demodulated by the demodulation means to an output port assigned to a carrier frequency of the reception signal. A digital modulation / demodulation circuit comprising at least one digital modulation circuit according to any one of claims 1 to 5. A digital modulation / demodulation circuit comprising at least one digital demodulation circuit according to any one of claims 6 to 9. At least one digital modulation circuit according to any one of claims 1 to 5,
A digital modulation / demodulation circuit comprising at least one digital demodulation circuit according to any one of claims 6 to 9.

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