JP3592041B2 - Cell switching equipment - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a cell switching apparatus, and is suitably applied to, for example, an asynchronous transfer mode (ATM) exchange.
[0002]
[Prior art]
FIG. 2 shows the configuration of a conventionally used ATM exchange. Generally, this type of ATM exchange is premised on accommodating a high-speed line requiring a bandwidth of 156 Mbps. However, the bandwidth of a practical line is relatively low at 1.5 Mbps to 6.3 Mbps. Further, even when a LAN is accommodated, a bandwidth of a commonly used Ethernet or the like is about 10 Mbps.
[0003]
However, the main switch section 4 (FIG. 2) of the ATM exchange is also assumed to accommodate a high-speed line (156 Mbps or the like), and the basic design is often adapted for a high-speed line.
[0004]
In such an apparatus, in order to accommodate a low-speed line as described above, the line accommodating section (multiplexing section 2 and demultiplexing section 6) generally accommodates the signal through two processes of multiplexing and demultiplexing. It was a target. On the other hand, when accommodating a high-speed line, a method of directly connecting using the high-speed line input / output interfaces 8 and 9 is adopted.
[0005]
[Problems to be solved by the invention]
The problem of the related art will be described with reference to FIG. FIG. 3 shows various functions of the ATM exchange in more detail. Hereinafter, the function and operation of each unit will be described based on FIG.
[0006]
The cells input from each of the low-speed line input interface units 1 (1), 1 (2),..., 1 (n) have VPI (virtual path connection identifier) and VCI (virtual channel) for identifying connections. Connection identifier).
[0007]
Usually, an ATM exchange selects an egress port and an identifier based on these identifiers and performs an exchange operation. In this type of exchange, in addition to such identifiers, an in-device header is used. This header is a header (switch control header) used for routing in the main switch unit 4. The additional function is called a switch control header adding function (or a header converting function).
[0008]
In this way, when the switch control header is added to the cell input from each line in the switch control header adding units 1A (1), 1A (2),..., 1A (n), the next stage multiplexing is performed. The multiplexing unit 2 performs a process of multiplexing cells up to the input link capacity (for example, 156 Mbps) of the main switch unit 4.
[0009]
Here, the cells input to the multiplexing unit 2 are temporarily held in buffers 2A (1), 2A (2),..., 2A (n) and multiplexed. The multiplexed cells are input to the main switch unit 4 and exchanged, and then input to the demultiplexing unit 6 at the next stage.
[0010]
The separation unit 6 sorts the cells input from the main switch unit 4 into corresponding lines based on the above-described switch control header in the separation unit 6A, and then prepares the next-stage cell buffer 6B prepared for each line. (1), 6B (2),..., 6B (n).
[0011]
The reason for buffering in the cell buffers 6B (1), 6B (2),..., 6B (n) is to enable cells arriving at a high speed to be output to a low-speed line.
[0012]
That is, the transmission speed control units 6C (1), 6C (2),... 6C (n) at the next stage transmit traffic flow to the low-speed line output interface units 7 (1), 7 (2),. .., 6B (n) in the buffering of cells arriving beyond the band of the output line. Used.
[0013]
However, the ATM exchange having such a configuration has the following problems.
[0014]
(1) First, since the switch control header providing units 1A (1), 1A (2),... 1A (n) are required for each incoming line, the hardware scale becomes large. .
[0015]
(2) Secondly, since an interface is required for each physical line accommodating the incoming line, it is expected that the number of input signals to the multiplexing unit 2 will increase (that is, a pin neck is expected).
[0016]
(3) Third, since an interface is required for each output line, it is expected that the number of output signals from the demultiplexing unit 6 will increase (that is, a pin neck is expected).
[0017]
(4) Fourth, the line speed and the number of lines to be accommodated are specified. For example, in the case of this multiplexing / demultiplexing method, the assumed line speed and number of lines are specified as 1.5M × 8 lines or 6.3M × 4 lines. In addition, even when a line or the like is extended, it is determined according to the above-described implementation specification of the multiplexing / demultiplexing unit, and there is a problem of lack of flexibility (expansion of the multiplexing / demultiplexing unit).
[0018]
[Means for Solving the Problems]
In order to solve such a problem, a cell switching apparatus according to a first aspect of the present invention accommodates at least two or more low-speed lines and converts each cell input via each of the low-speed lines into at least twice as fast as each line speed. Cell exchange equipment that exchanges at the speed ofThe following means are provided.
[0019]
That is,The input interface unit accommodating the low-speed line includes: (1) a buffer unit for temporarily storing each cell input from each low-speed line corresponding to each low-speed line; and (2) a cell unit from the buffer unit. A bus contention control unit that controls reading, controls read timing from a buffer unit corresponding to each low-speed line, and controls contention of the timing; and (3) reads out data from a buffer unit corresponding to each low-speed line. A bus for multiplexing and outputting each cell; and (4) a physical line selection identifier assigning unit for inputting each cell before multiplexing and assigning a physical line selection identifier representing an input line of each cell to a header of each cell. (5) Each multiplexed cell is input, and based on the physical line selection identifier and the connection identifier read from the header of each cell, the egress side of the main switch used for switching each cell. And selectors, characterized in that it comprises a delivery side physical line selected identifier corresponding to the outlet side low-speed line, a header converting portion for imparting an exit side connection identifier.
[0020]
In this way, by multiplexing low-speed lines on the bus, the combination of the number of accommodated lines and the speed of the accommodated lines can be flexibly changed.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
(A) First embodiment
Hereinafter, a first embodiment of an ATM exchange according to the present invention will be described with reference to the drawings.
[0022]
(A-1) Configuration of First Embodiment
(A-1-1) Overall configuration
FIG. 1 shows the configuration of the ATM exchange according to the first embodiment. This ATM exchange is roughly divided into three parts, an input control unit 11 to 15, a main switch unit 16, and an output control unit 17 to 20, and has the following four characteristic points.
[0023]
1. Use of a cell multiplex bus (ensures flexibility in the number of accommodated lines and speed).
[0024]
2. The point that the physical line selection identifier (PID) is adopted and the header conversion is centralized control (reduction of the scale of the input side header conversion circuit and reduction of the circuit of the output side demultiplexer).
[0025]
3. Centralized control of line transmission traffic flow control (reduction of output side separation circuit).
[0026]
Hereinafter, the configuration of each unit will be described in order.
[0027]
(A-1-2) Configuration of input control unit
The input control unit includes physical line interfaces 11 and 12, an incoming cell multiplexed bus interface unit (CBIinf) 13, an incoming cell multiplexed bus (CBI) 14, and a header conversion unit (HCV) 15.
[0028]
The physical line interfaces 11 and 12 correspond to n low-speed line input interface units (PHI) 11 (1), 11 (2),... 11 (n) corresponding to the n low-speed lines, respectively. It is composed of n temporary storage cell buffers 12 (1), 12 (2),... 12 (n).
[0029]
The temporary storage cell buffers 12 (1), 12 (2),..., 12 (n) are temporary storage means used for multiplexing cells input via each low-speed line. Controlled by the side cell multiplex bus interface units 13 (1), 13 (2),..., 13 (n).
[0030]
The input-side cell multiplexed bus interface units 13 (1), 13 (2),..., 13 (n) are cells input from the corresponding temporary storage cell buffers 12 (1), 12 (2),. This is an interface unit whose main functions are to assign a physical line selection identifier (PID) to and to control contention.
[0031]
Cells input from each low-speed line are temporarily stored under the control of the n input-side cell multiplexed bus interface units 13 (1), 13 (2),... 13 (n). , 12 (2),..., 12 (n) and multiplexed on the incoming cell multiplex bus 14.
[0032]
At this time, the input-side cell multiplex bus interface units 13 (1), 13 (2),..., 13 (n) determine that the total bandwidth of each low-speed line is (SW) The bandwidth of each low-speed line is controlled so as not to exceed (the route band of 16).
[0033]
Thereby, the capacity required for the temporary storage cell buffers 12 (1), 12 (2),... 12 (n) can be suppressed to a minimum (a few cells). The cells multiplexed on the incoming cell multiplex bus 14 are output to the header conversion control unit 15.
[0034]
The header conversion control unit 15 converts the input cell into a header of an outgoing cell based on the header added to the input cell, and adds a switch control header. Here, the header conversion control unit 15 is provided for each route unit of the main switch unit 16.
[0035]
(A-1-3) Configuration of output control unit
The output control unit includes an egress line control unit (PSHP) 17, an egress cell multiplex bus (CBO) 18, an egress cell multiplex bus interface unit (CBOinf) 19, and an egress line interface unit (PHO) 20. It consists of.
[0036]
The outgoing line control unit 17 is a control unit provided on the outgoing side of the main switch unit 16 and includes a cell distribution unit 17A, a cell buffer 17B, a cell buffer selecting unit 17C, and a transmission traffic control unit 17D. I have.
[0037]
Among them, the cell distribution unit 17A functions to select the cell buffer 17B based on the physical line selection identifier PID assigned on the input side. Further, the transmission traffic control unit 17D functions to extract the cell header and determine the transmission traffic flow for each line (for each PID). In addition, the cell buffer selection unit 17C functions to select the cell buffer 17B based on the determination result of the transmission traffic control unit 17D.
[0038]
As a result, cells controlled in accordance with the respective outgoing line speeds are multiplexed and output to the output of the outgoing line control unit 17 and sent out to the next outgoing cell multiplexing bus 18.
[0039]
The output line interface units 20 (1), 20 (2),..., 20 (n) corresponding to each low-speed line are provided by the output-side cell multiplex bus interface units 19 (1), 19 (2),. ) Is connected to the outgoing cell multiplex bus 18.
[0040]
(A-2) Operation of the first embodiment
(A-2-1) Cell flow and change in header information in the device
Here, a flow of cells in the ATM exchange according to the first embodiment and an outline of a change in a cell header due to control in the device at this time will be described with reference to FIG.
[0041]
The upper part of FIG. 4 shows the same configuration as that of FIG. 1, and the lower part of FIG. 4 shows how the cell header changes due to control in the device.
[0042]
As is well known, ATM is a method of transferring information in cells (fixed-length packets of 53 bytes), and each cell is provided with VPI / VCI for identifying each connection.
[0043]
The ATM exchange operates to select the outgoing line based on the incoming connection identifier (VPI1 / VCI1) given to the header of each cell as described above, and also outputs the outgoing line connection identifier (VPI2 / VCI2). It works to give. Hereinafter, the cell switching operation will be described.
[0044]
First, each cell input from the low-speed line to the ATM exchange (point A in FIG. 4) is input to the incoming-side cell multiplex bus interface units 13 (1), 13 (2),. After contention control, a physical line selection identifier (PID) is assigned (point B in FIG. 4).
[0045]
Each cell that has been subjected to the contention control is input to the header conversion unit 15 via the incoming-side cell multiplex bus 14 and is subjected to header conversion. Here, the header conversion unit 15 refers to a conversion table set in advance by software based on the identifier (PID + VPI + VCI) given to the header of the cell arriving from each low-speed line. Then, a route selection identifier SWHD, a physical line identifier PID, and a VPI / VCI on the output side of the main switch unit 16 are assigned (C in FIG. 4).
[0046]
Each cell whose header has been converted is input to the main switch unit 16. The main switch unit 16 selects an egress route based on the SWHD of each cell, and outputs the egress route to the egress line control unit 17 (D in FIG. 4).
[0047]
The outgoing line controller 17 selects the cell buffer 17B according to the physical line identifier PID attached to the arriving cell, and outputs the selected cell buffer 17B to the corresponding cell buffer 17B.
[0048]
The output traffic control unit 17D executes speed control of cells to be transmitted for each physical line identifier PID (for each line), and performs control so that the corresponding cells are not transmitted beyond the band of each line set in advance by software. I do.
[0049]
The cell buffer selection unit 17C reads cells temporarily stored in each cell buffer 17B in accordance with an instruction from the output traffic control unit 17D.
[0050]
By the functions of the cell buffer selection unit 17C and the output traffic control unit 17D, cells controlled so as not to exceed the bandwidth of each line are multiplexed and read out on the egress cell multiplex bus 18.
[0051]
Since the outgoing cell multiplex bus 18 is connected to each line unit in a bus format, the output of the outgoing cell multiplex bus 18 is connected to the n outgoing cell multiplex bus interface units connected to each line. 19 (1), 19 (2),..., 19 (n) (E in FIG. 4).
[0052]
Here, each outgoing cell multiplex bus interface section 19 (1), 19 (2),... 19 (n) is assigned to its own line among the cells input from the outgoing cell multiplex bus 18. Only cells having the physical line selection identifier PID2 are extracted and output to the outgoing line interface units 20 (1), 20 (2),..., 20 (n) (F in FIG. 4).
[0053]
The above is the outline of the flow of cells in the ATM exchange and the accompanying operation of changing the header information.
[0054]
(A-2-2) Detailed operation in input side control unit
Subsequently, a more detailed operation content of the input side control unit for realizing the above operation and a configuration for realizing this will be described.
[0055]
FIG. 5 is a detailed configuration diagram of the entry-side control unit used for explaining the operation. FIG. 6 is a diagram showing an outline of a header conversion method executed in the input side control unit.
[0056]
As shown in FIG. 5, cells output from each line input interface unit 11 (i) are input to a cell buffer 12 (i) provided corresponding to each line, and are temporarily stored.
[0057]
From each cell buffer 12 (i), a cell valid signal clav1 indicating the presence / absence of a cell is output to the corresponding incoming cell multiplex bus interface 13 (i). The cell valid signal clav1 is input to a contention control circuit (ABT) 13A provided in each interface 13 (i).
[0058]
When the cell valid signal clav1 becomes valid, the contention control circuit 13A performs contention control for input / output with another circuit (contention control circuit of another incoming cell multiplex bus interface) via the signal line ABTctl. The contention control of the incoming cell multiplex bus 14 is executed based on necessary information (for example, display during data transfer).
[0059]
The contention control circuit 13A for the cell that survived this contention control validates the read instruction rdst1 to the physical line interface unit (PHYinf) 13B. When the read instruction rdst1 becomes valid in this way, the physical line interface unit 13B reads the cell from the cell buffer 12 (i) and transfers it to the subsequent PID stamp unit 13C.
[0060]
The PID stamp unit 13C stamps a PID value set by software (stored in the PID holding register 13E) on a high-order bit portion exceeding a predetermined VPl effective range (line equipment condition) and outputs the stamp. (See FIG. 6).
[0061]
Here, the physical line selection identifier PID is added to the bit portion immediately above the effective VPI because of the degeneration performed by the header conversion unit 15 at the next stage (conversion is performed by packing only the number of effective bits of the VPI and VCI). This is because the function of indexing the table) can be used effectively.
[0062]
In order to realize this function, the input-side cell multiplex bus interface 13 (i) has a register (a VPl valid register 13F set by software) for holding the number of VPl valid bits determined on the line interface. Further, a function of determining the position of the PID bit to be stamped and stamping the PID value set in the PID holding register 13E is provided.
[0063]
Thus, the information (cell) stamped with the physical line selection identifier PID is output to the header conversion unit 15 via the incoming cell multiplex bus 14. The contention control unit 13A performs contention control based on various timing signals transmitted from the header conversion unit 15, and prior to the transmission of the cell, a cell valid signal clav2 for notifying the input-side header conversion table 15 of the transmission. Is sent.
[0064]
Here, the transmission timing of the cell valid signal clav2 is set to an optimal timing for transferring the cell stream. For example, the cycle is set to “the number of clocks required for cell stream transfer” + “the number of clocks required for switching”. With this setting, useless overhead on the cell bus can be optimized.
[0065]
The cell bus interface control unit 15A of the header conversion unit 15 checks the cell valid signal clav2 signal supplied from the incoming cell multiplex bus interface 13 (i) at each timing, and if there is a valid cell, the read control signal rdctl2. Is enabled and the reception of the cell is notified.
[0066]
As described above, when a cell is input through the input cell multiplex bus 14, the header conversion unit 15 performs a process of reducing the VPI value and the VCl value extracted from the header portion into only valid bits in the compression unit 15B. (FIG. 6). The VPI value and the VCI value after the degeneration are given to the conversion table 15C, and index the corresponding path. Note that the header information to be degenerated is set in consideration of the bit range of the PID in addition to VPI + VCI.
[0067]
If the PID is taken into account in this way, header conversion for each line can be realized by one header conversion unit 15. In the conversion table 15C, the outgoing route, PID, and VPI value / VCI value are set in advance by software. By doing so, the outgoing header information converted based on the input header information of the cell is added to the cell and output to the main switch unit 16.
[0068]
(A-2-3) Detailed operation in output side control unit
Subsequently, a detailed operation of the outlet control unit will be described. The feature realized by the output side control unit is that the line control unit 17 provided on the output side path of the main switch unit 16 can centrally execute the speed control corresponding to each line.
[0069]
This will be described with reference to FIG. Each cell routed for each route by the main switch unit 16 is stored in the cell buffer 17B of the line control unit 17. The cell buffer 17B is controlled by a page memory control unit (MEM-CTL) 17E1, and has a configuration in which pages are managed for each cell.
[0070]
Further, a write control unit (WR-CTL) 17E2 that writes data in the cell buffer 17B stores a page address (page memory information) and header information (PID information) written in an arriving cell in a PID queue control. (PID-Queue) 17D1.
[0071]
Here, the PID queue control unit 17D1 operates to configure a virtual queue (queue) for each notified PID information. That is, a chain of memory addresses in which cells are stored is formed in the order of arrival for each PID. These pieces of information are further notified to the determination unit 17D2 that determines the transmission speed for each PID. Here, a determination unit having a transmission history counter for each PID is assumed.
[0072]
The information queued in each PID queue control unit 17D1 is determined at a timing corresponding to the maximum transmission speed (matching the speed of the output-side cell multiplex bus 18), and together with the determination result, the memory address to be read (page memory information) ) Is sent to the read control unit (RD-CTL).
[0073]
As a result, cells whose speed is controlled for each PID are output to the outgoing cell multiplex bus 18 (function of the outgoing traffic flow control (shaping) unit in FIG. 8). Each cell output to the outgoing cell multiplex bus 18 arrives at an interface unit (CBOinf in FIG. 7, CBoa, CBob, CBoc, CBod in FIG. 8) of the outgoing cell multiplex bus 18 provided for each line. I do.
[0074]
Here, the egress cell multiplex bus interface unit 19 extracts the PID header from each cell by the PID extraction unit 19A and supplies the extracted PID header to the PID determination unit 19B to check the PID header attached to each cell. .
[0075]
At this time, the PID determination unit 19B compares the content of the PID header extracted from the bit position stored in the PID bit position register 19C with the value set in the outgoing PID value register 19D. Check if the cell is addressed to itself.
[0076]
Then, the selector 19E is controlled so that only the one that matches the own PID value is passed to the next stage. Here, the PID bit position indicates the same position as the PID bit position given by the input side control unit.
[0077]
As a result of the inspection, when it is determined that the arrived cell matches its own PID value, the PID header deletion unit (PID-del) 19F deletes the PID header part added to the header.
[0078]
Specifically, as shown in FIG. 9, “0” is set to all of the corresponding bit portions. By the way, the bit for selecting the exit side route of the main switch which is no longer needed is also deleted at the same time.
[0079]
On the other hand, when it is determined that the arrived cell does not match its own PID value, the idle cell generated by the idle cell generation unit 19G is inserted and output.
[0080]
The above is the detailed contents of the operation executed by the output side control unit.
[0081]
(A-3) Effects of the first embodiment
As described above, in the ATM switch according to the first embodiment, the output of cells input from each low-speed line to the bus 14 is contention-controlled, and cells from these lines are multiplexed on the bus. By adopting the system, it is possible to realize an ATM switch which can handle an arbitrary line speed.
[0082]
This also makes it possible to configure a line accommodating unit that assumes various numbers of lines according to the line type. For example, expansion for each line is possible.
[0083]
The headers required for switching in the main switch unit 16 are intensively executed in the header conversion unit 15 prepared in common for each line (that is, the physical line assigned in the interface unit 13 corresponding to each line). (Using the identifiers PID and the conversion table 15C prepared for them)), it is possible to realize an ATM exchange having a smaller hardware configuration than in the past.
[0084]
Furthermore, since the outgoing line control unit 17 is configured to centrally execute the speed control for each output line, the speed control is performed in the interface unit of each line as in the related art. The hardware configuration can be small.
[0085]
(B) Second embodiment
Hereinafter, a second embodiment of the ATM exchange according to the present invention will be described with reference to the drawings.
[0086]
(B-1) Configuration of Second Embodiment
FIG. 10 shows the configuration of the ATM exchange according to the second embodiment. The ATM exchange according to the second embodiment is characterized in that the outgoing line control unit 17 'is provided in both the low-speed line accommodating unit and the high-speed line accommodating unit. It has the same configuration as the ATM switch according to the embodiment.
[0087]
Here, the configuration of the outgoing line control unit 17 ′ is basically the same as the configuration of the outgoing line control unit 17 described in the first embodiment, except that the cell read control is performed on a virtual channel (VC) basis. The difference is that a VC / port control unit 17D 'for realizing the transmission traffic control function is used.
[0088]
This is to control the output traffic flow in VC units for the output line. Note that the transmission traffic speed control in VC units for the outgoing line described here is a connection speed (band) set at the end and end, and is independent of the physical line speed.
[0089]
FIG. 11 shows a detailed configuration of the outgoing line control unit 17 '. The outgoing line control unit 17 'is connected to the outgoing side of the main switch unit 16 like the outgoing side control unit 17 described in the first embodiment. It is connected to the multiplex bus 18 or the high-speed line physical control unit 21.
[0090]
The output control unit 17 ′ includes a cell buffer (CELBUF) 17B that stores information for each cell controlled by the page memory control unit (MEM-CTL) 17E1, a page memory write control unit (WR-CTL) 17E2, It comprises a read control unit (RD-CTL) 17E3 and a VC / port control unit 17D '.
[0091]
Here, the write controller 17E2 and the VC / port controller 17D 'are connected via a signal notifying the header information of the arriving cell and a signal line notifying the written page memory management information.
[0092]
Similarly, the read control unit 17E3 and the VC / port control unit 17D 'are connected via a signal line for notifying a read instruction and page memory management information to be read.
[0093]
The VC / port control unit 17D 'includes a VC queue control unit (VC-Queue) 17D11, a VP / PID queue control unit (VP / PID-Queue) 17D12, and a determination unit 17D2.
[0094]
Here, the VC queue control unit (VC-Queue) 17D11Has a function of forming a queue based on the VC information of the header information of the received cell, and measuring a cell interval of the same VC arriving.
[0095]
Also, a VP / PID queue control unit (VP / PID-Queue) 17D12Has a function of forming a VP / PID queue from the PID and VPl information of the header information of the received cell and measuring the cell interval of the same VP / PID that has arrived.
[0096]
The determination unit 17D2 operates to determine these measured cell intervals based on the transmission cell intervals and the allowable value set in advance by software.
[0097]
(B-2) Operation of the second embodiment
Next, the operation of the ATM switch having the above configuration will be described. Since the overall operation flow is the same as that of the first embodiment, in the following description, the operation of the outgoing line control unit 17 ', which is a component specific to the second embodiment, will be described in detail. explain.
[0098]
First, the cell received from the main switch unit 16 to the outgoing line control unit 17 'is written into the cell buffer 17B whose page is managed by the page memory write control unit 17E2.
[0099]
Here, the page management is a function of dividing the memory into storage areas for one cell information such as one page, two pages,..., And making the memory randomly accessible in page units. Is controlled.
[0100]
The page memory write control unit 17E2 writes the sequentially arriving cells in the cell buffer 17B managed in this way, and simultaneously sends the header information (PID) of the sequentially arriving cells to the VC / port control unit 17D '. , VPI, VCI values).
[0101]
The VC queue control unit 17D11 configuring a virtual queue (queue) in VC units extracts a valid part (a value set in advance by software) of the received VCl value based on the header information, The cells are arranged in the arrival order and the cell interval is measured (FIG. 12).
[0102]
At the same time, the VP / PID queue control unit 17D12 extracts valid portions of the received PID value and VPI value, arranges them in the order of arrival, and measures the cell interval (FIG. 12).
[0103]
These results are provided to the determination unit 17D2 at the next stage, and the determination unit 17D2 checks the result against a value set in advance by software. Then, when both the measurement value of the VC queue control unit 17D11 and the measurement value of the VP / PID queue control unit 17D12 satisfy the condition, it is determined to be OK.
[0104]
The cell determined to be OK is notified of the read instruction signal together with the page memory information in which the user information is stored. The read control unit 17E3 reads the cell based on the read instruction signal and the page memory information. Here, at the time of high-speed line connection, the PID value is set to “0”. That is, the content of PID + VPI is controlled by software so that only the VPI value has meaning.
[0105]
(B-3) Effects of the second embodiment
As described above, according to the second embodiment, in a device that needs to control the transmission traffic flow rate on a VC basis and that accommodates a low-speed line and a high-speed line, both the low-speed line and the high-speed line By disposing the outgoing line control unit 17 ', hardware can be shared.
[0106]
Further, similarly to the first embodiment, the adoption of the cell bus and the centralized deployment of the outgoing traffic control can be realized, so that the hardware can be reduced in size.
[0107]
(C) Other embodiments
In the above embodiment, the present invention has been described by taking an ATM exchange as an example, but the present invention can be widely applied to an apparatus having a cell exchange function.
[0108]
【The invention's effect】
As mentioned aboveOneAccording to the present invention, by multiplexing low-speed lines on a bus, the combination of the number of accommodated lines and the speed of the accommodated lines can be flexibly changed as compared with the related art.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of an apparatus according to a first embodiment.
FIG. 2 is a block diagram illustrating a schematic configuration of a conventional device.
FIG. 3 is a block diagram showing a detailed configuration of a conventional device.
FIG. 4 is a diagram showing a flow of a cell transferred in the device according to the first embodiment and a state of change of cell header information.
FIG. 5 is a diagram provided for describing an operation in an entrance-side control unit.
FIG. 6 is a diagram illustrating a state of centralized control of header conversion.
FIG. 7 is a diagram provided for describing an operation in an output side control unit.
FIG. 8 is a diagram showing a flow of a cell in an egress control unit.
FIG. 9 is a diagram illustrating a flow of processing performed on a cell header.
FIG. 10 is a block diagram illustrating a schematic configuration of an apparatus according to a second embodiment.
FIG. 11 is a diagram illustrating an internal configuration of a delivery control unit.
FIG. 12 is a diagram illustrating an operation state of a VC / port control unit.
[Explanation of symbols]
11: low-speed line input interface unit, 12: temporary storage cell buffer, 13: incoming cell multiplex bus interface unit, 13A: contention control circuit, 13B: physical line interface unit, 13C: PID stamp unit, 13E: PID holding register, 13F: VPl valid register, 14: incoming cell multiplex bus, 15: header conversion unit, 15A: cell bus interface control unit, 15B: degeneration unit, 15C: conversion table, 15D: header adding unit, 15E: SW interface, 16 ... Main switch unit, 17, 17 '... Outgoing line control unit, 17A ... Cell distribution unit, 17B ... Cell buffer, 17C ... Cell buffer selection unit, 17D ... Outgoing traffic control unit, 17D1 ... PID queue control unit, 17D' ... VC / port controller, 17E1 ... Page memory controller, 17E ··· Write control unit, 17E3 ··· Read control unit, 18 ··· Outgoing cell multiplexed bus interface, 19 ··· Outgoing cell multiplexed bus interface unit, 19A ··· PID header extraction unit, 19B ··· PID determination unit, 19C ··· PID bit position register, 19D: Outgoing PID value register, 19E: Selector, 19F: PID header deleting unit, 20: Outgoing line interface unit, 21: High speed line physical control unit.

Claims (7)

In a cell switching apparatus accommodating at least two or more low-speed lines and exchanging each cell input through each of the low-speed lines at a speed of at least twice or more each line speed,
In the input interface section that accommodates low-speed lines,
A buffer unit used for temporarily storing each cell input from each low-speed line, corresponding to each low-speed line,
A bus contention control unit that controls reading of cells from the buffer unit, controls read timing from the buffer unit corresponding to each low-speed line, and controls contention of the timing;
A bus for multiplexing and outputting each cell read from the buffer unit corresponding to each low-speed line,
A physical line selection identifier providing unit that inputs each cell before multiplexing, and adds a physical line selection identifier representing an input line of each cell to a header of each cell;
Each of the multiplexed cells is input, and based on the physical line selection identifier and the connection identifier read from the header of each cell, an egress route selector of the main switch used for switching each cell, A cell switching device comprising: a header conversion unit for assigning an egress physical line selection identifier corresponding to a low-speed line and an egress connection identifier. The cell switching device according to claim 1 ,
An output interface unit that outputs each cell exchanged in the main switch unit to a corresponding low-speed line,
A cell switching device, comprising: a transmission traffic control unit that controls a transmission traffic flow rate so as not to exceed a band of an outgoing low-speed line for each outgoing physical line selection identifier given by the header conversion unit. The cell switching device according to claim 2 ,
In the above output interface section,
A bus for inputting each cell output from the transmission traffic control unit,
A bus interface unit that outputs only cells having an outgoing physical line selection identifier assigned to itself to a corresponding outgoing low-speed line, among the cells input via the bus. Cell switching equipment. The cell switching device according to claim 1 ,
The physical line selection identifier providing unit,
A register for holding a value of a physical line selection identifier to be given;
A register for holding the number of valid bits of the connection identifier, and assigning the value of the physical line selection identifier held in the register to a position immediately above the effective bit of the virtual path identifier in the connection identifier. Characteristic cell switching equipment. The cell switching device according to claim 1 ,
The header conversion unit,
A cell switching apparatus characterized in that effective bits of an egress physical line selection identifier and an egress connection identifier are degenerated and a conversion table is indexed. The cell switching device according to claim 2 ,
The output interface unit includes:
A cell switching device comprising: a virtual queue for each egress physical line selection identifier; and a determination unit that measures a cell interval for a corresponding egress line. The cell switching device according to claim 2 ,
The output interface unit includes:
A cell switching apparatus comprising: a virtual queue for each connection; and a determination unit for measuring a cell interval for a corresponding outgoing line.

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