JP3592227B2

JP3592227B2 - Drive technology for starting up liquid crystal devices

Info

Publication number: JP3592227B2
Application number: JP2000319062A
Authority: JP
Inventors: 美香中村; 克己足達; 清弘川崎; 勝治服部
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 1999-10-19
Filing date: 2000-10-19
Publication date: 2004-11-24
Anticipated expiration: 2020-10-19
Also published as: JP2002014317A

Description

【０００１】
【発明の属する技術分野】
本発明は液晶装置に関し、特に液晶層は電圧が印加されていないときにはスプレイ配向であるが表示等の機能発揮時にはベンド配向である液晶装置の駆動のための立上げ技術に関する。
【０００２】
【従来の技術】
液晶装置は、液晶素子の電気的動作が、各画素は１表示周期中、明なら明を、暗なら暗を持続する保持型であるため、１表示周期の更に短い時間だけ輝くブラウン管に比較してちらつきの少ない静止画となるのが特徴のひとつであった。
【０００３】
しかし近年、パーソナルコンピュータではＣＰＵやメモリの高速大容量化で動画処理が容易に行えるようになっている。このため、液晶表示装置での動画表示時の画質向上が望まれている。
【０００４】
また、放送受像機としてのテレビは大画面化が進んでいるが、ブラウン管では大画面化と共にどうしても奥行きがある程度大きくなるため薄型テレビの要望に対しては好ましくない。そのための一手段として液晶表示装置を採用することが考えられている。
【０００５】
現在、液晶装置の主流であるＴＮ配向液晶装置は応答速度が遅く、しかもブラウン管では各表示周期内で各画素が瞬間的、極く短時間のみ発光しているのに対して、液晶素子は、ＯＮ（開、発光）ならばその１表示周期内でその表示期間中ずっと発光し続けている保持型である事もあって、動画表示時には尾を引くように見える等、ブラウン管より画質が劣る。
【０００６】
その対策として、例えば特開昭６１−１１６３２９号あるいは特開平７−８４２５４号にあるようなＯＣＢ型（タイプ）と言われるベンド配向を有する液晶を用いれば高速応答、広視野角で動画表示や大画面化に十分対応でき、ブラウン管よりも薄型で低消費電力の大画面ディスプレイを提供することができる。
【０００７】
また、液晶を使用した装置は、単にワードプロセッサー、パソコン、テレビジョン受像機等の表示部のみならず、光論理素子を使用した回路や装置等にも使用されだしているが、かかる用途においても、良好な表示性能、高速対応等の面からＯＣＢタイプの液晶が注目されている。
【０００８】
【発明が解決しようとする課題】
しかしながら、かかる液晶では図１の（１）や（２）に示すようなスプレイ配向５１から（３）に示すようなベンド配向に転移するためには液晶層に高い電位差を一定時間以上かけ続ける必要があるが、かかる電圧をかけるためには、トランジスタ素子、配線に負担がかかり、高コストともなる。すなわち、現在広く用いられている素子、配線等にて可能な電圧、電流等で容易かつ確実にかかる転移を行なわせる技術は未だ実現されていない。その結果、現在のところこのタイプの液晶は汎用的に使用するには至っていない。
【０００９】
このため、このようなＯＣＢタイプの液晶装置あるいはその駆動回路において、現在のトランジスタ素子、配線等のハードに負担をかけることなく、液晶層を短時間で確実にベンド配向へ転移させるしかも低コストの技術の開発が望まれていた。
【００１０】
また同様に、上述の他の用途への使用に際しても、確実、容易な立上げ技術の開発が望まれていた。
【００１１】
【課題を解決するための手段】
本発明は、以上の課題を解決することを目的としてなされたものであり、液晶を使用した装置の各素子の構造に工夫を凝らしている。また同じく、立上げのために可能な限り高い電圧を印加したり、電圧を印加する際のタイミング等に工夫を凝らしている。具体的には、以下のようにしている。
【００１２】
参考例１の発明では、ＯＣＢタイプの液晶表示装置等の構造に工夫を凝らし、その結果、立上げのために、第１の基板のゲート線と第２の基板の対向電極との間に在る液晶層に、通常の映像の表示時よりも高い電界強度が与えられ、これによりその部分がベンド配向をすると、そこが核となってこれが成長し、液晶層全体のベンド配向への移行を図るものである。この際、液晶パネル内の他の部分に比較して高電圧で駆動しているゲート線を用いるため、ソース線駆動ＩＣや画素トランジスタに負担を与えることなく液晶層に高い電界強度を与えることができる。
【００１３】
また、液晶層により高い電界強度を与えるため、ゲート線上の絶縁膜の厚みを薄くして絶縁膜容量を大きくし、ゲート線、対向電極間の電圧の分圧比を変えている。
【００１４】
また同じく、ゲート線上の絶縁膜に比誘電率の高い材料を用いて絶縁膜容量を大きくし、ゲート線、対向電極間の液晶層と絶縁膜の電圧の分圧比を変えている。
【００１５】
また同じく、液晶層との間に他の金属膜や半導体層が無い部分のゲート線を形成する金属の厚みを厚くすることでゲート線上の液晶層の厚みを０．５〜１．５μｍ程度薄くしている。
【００１６】
また同じく、液晶層との間に他の金属膜や半導体層が無い部分のゲート線上にソース線形成金属を電気的に接触させて積層してゲート線の厚みを厚くしてゲート線上の液晶層の厚みを薄くしている。
【００１７】
また同じく、液晶層との間に他の金属膜や半導体層が無い部分のゲート線上にソース線形成金属を電気的に接触させずに積層してゲート線上の液晶層の厚みを薄くしている。
【００１８】
また同じく、第２の基板上の対向電極を第１の基板のゲート線と対峙する部分とそれ以外の部分に分け、ゲート線に対峙する部分の対向電極にそれ以外の部分よりも高い電圧をかける。
【００１９】
また同じく、第２の基板上でゲート線に対峙する部分の対向電極厚みをそれ以外の部分よりも厚くしてゲート線上の液晶層の厚みを薄くしている。
【００２０】
また同じく、第２の基板上のカラーフィルター形成樹脂を第１の基板のゲート線に対峙する部分で積層してゲート線上の液晶層の厚みを薄くしている。
【００２１】
また同じく、第２の基板上で、第１の基板のゲート線に対峙する部分に柱状スペーサを設け、この柱状スペーサと液晶層の間に対向基板電極を形成してゲート線上の液晶層の厚みを薄くしている。
【００２２】
第１の発明群では、液晶装置の立上げ用回路等に工夫を凝らし、第１の基板の画素電極と第２の基板の対向電極との間に、通常の映像の表示時よりも高い電位差を所定の手順、規則にのっとって連続的に付与するものである。
【００２３】
これにより、対向電極の変動が利用可能となる。また、走査タイミングや印加電位差の変更、変更の制御により、ベンド配向への転移を促している。
【００２４】
また同じく、第１の基板の画素電極と第２の基板の対向電極との間に、通常映像表示期間とは異なる第１種の電位差を連続的に付与する期間を設け、できるだけ広い面積で液晶層にかかる電位差を大きくすることでベンド配向への転移核の生成を増やし、ベンド領域の拡大を高速化し、ベンド配向への転移を短時間で行う。
【００２５】
また同じく、第１の基板の画素電極と第２の基板の対向電極との間に、通常映像表示期間とは異なる第１種の電位差を付与する第１種の電位差印加ステップと、第１種の電位差よりも小さい第２種の電位差を付与する第２種の電位差印加ステップを繰り返し制御ステップで以って一回以上交互に与える駆動方式で、これらの期間のうち、５０％から９５％の時間が第１種の電位差印加ステップとし、ベンド配向の核の生成とベンド領域の拡大を行う第１種の電位差印加ステップと、ベンド配向の核の生成ができなかったりベンド領域の拡大が進まなかった部分の液晶層の再整列を行う第２種の電位差印加ステップを交互に与えることにより、パネル全面を高速にベンド配向に転移させることができる。
【００２６】
また同じく、第２種の電位差印加ステップに画素トランジスタをオンからオフにするときにゲート線の電位変動に誘起されて画素電極に生じる電位変動分を対向電極電位に反映した電位をソース線に与えて画素電極の充電を行う充電小ステップを有し、ゲート線のオン・オフタイミングを通常の映像表示期間から変更することなく、画素電極の電位を所望の電位に固定してパネル全面のベンド配向への転移を高速化できる。
【００２７】
また同じく、第２種の電位差印加ステップに画素トランジスタをオンからオフにするときにゲート線の電位変動に誘起されて画素電極に生じる電位変動分を対向電極電位に反映した電位をソース線に与えて画素電極の充電を行う充電小ステップを有し、第１種の電位差印加ステップには第１種の電位差がより大きくなるようにソース線の電位を第２種の電位差印加ステップとは異なる電位にし、ベンド配向の核の生成とベンド領域の拡大をより高速化して、パネル全面でのベンド配向への転移を高速化する。
【００２８】
また同じく、液晶層をベンド配向させるための駆動を行う期間を第２種の電位差印加ステップから開始し、液晶層の整列を先に行うことで画素電極と対向電極の間に第１種の電位差を与える第１種の電位差印加ステップでのベンド核の生成とベンド領域の拡大を高速化し、パネル全面でのベンド配向への転移を高速化する。
【００２９】
また同じく、液晶層をベンド配向させるために画素電極と対向電極間に第１種の電位差を与える第１種の電位差印加ステップと画素電極と対向電極間の電位差を第１種の電位差よりも小さい第２種の電位差にする第２種の電位差印加ステップを１回以上交互に与える駆動方式で、第１種の電位差印加ステップあるいは第２種の電位差印加ステップを終了し通常の入力映像情報表示期間に移行するまでの間に、液晶層にかかる電位差が大きい映像情報を１フィールド以上表示し、ベンド領域の拡大で液晶層のベンド配向への転移を完了することで、パネル全面でのベンド配向への転移を高速化する。
【００３０】
参考例２は、液晶層の立上げ時の安定化を図るものである。このため、電源の投入等に工夫を凝らしている。
【００３１】
【発明の実施の形態】
以下、本発明をその実施の形態に基づいて説明する。
【００３２】
｛参考例１｝
本参考例１は、主に画素の絶縁膜の構造に工夫を凝らして、液晶層の転移用に高い電圧が加わる様にしたものである。
【００３３】
以下、本発明群をその実施の形態に基づいて説明する。
【００３４】
（第１−１の参考例）
ここに、「（第１−１の参考例）」とは、「参考例１の第１の実施の形態」という意味である。また、本明細書中で、「（第１−１の実施の形態）」とは、「第１の発明群の第１の実施の形態」という意味である。このため、「本参考例の第２の実施の形態」ならば、「（第１−２の参考例）」と記す。
【００３５】
なお、実際には、この様な回路構成の画素が基板上に縦、横、幾列、幾行にも、更にケースによっては多段にまで形成されているが、これは自明かつ煩雑となるので、図示は省略する。そしてこれは、他の発明群や実施の形態でも同様である。
【００３６】
図２は、従来の液晶パネルの１画素分の構造の平面（１）と、トランジスタ素子部のＡ−Ａの断面（２）を示したものである。本図において、２１は、透明画素電極である。３は、画素電極である。５は、液晶層である。６４は、チャネル保護膜である。６５は、ａ−Ｓｉ（アモルファスシリコン）層である。６６は、ｎ＋ａ−Ｓｉ層である。７は、ソース線電極である。７６は、ソース線電極と液晶層間の絶縁膜である。８は、ゲート線電極である。８６は、ゲート線電極とａ−Ｓｉ層間の絶縁膜である。９は、対向電極である。
【００３７】
図３に、図２で示す液晶パネルのゲート線電極、対向電極間の容量性負荷を模式的に示す。
【００３８】
本図において、８は、ゲート線電極である。９は、対向電極である。Ｃ１は、液晶層の容量性負荷である。Ｃ２は、ソース線電極と液晶層間の絶縁膜の容量性負荷である。Ｃ３は、ゲート線電極とａ−Ｓｉ層間の絶縁膜の容量性負荷である。
【００３９】
図４に、本参考例の液晶パネルの１画素分の構造の平面（１）とそのＡ−Ａの断面（２）を示す。
【００４０】
本図において、８はゲート線電極、７はソース線電極、３は画素電極、６４はチャネル保護膜、６５はａーＳｉ層、６６はｎ＋ａーＳｉ層、８６はゲート線電極とａーＳｉ層間の第１の絶縁膜、７６２はソース線電極と液晶層間の第２の絶縁膜、５は液晶層、９は対向電極、２１は透明画素電極、８６２はゲート線電極とａーＳｉ層間の第２の絶縁膜、７６１は、ソース線電極とａ−Ｓｉ層間の第１の絶縁膜である。
【００４１】
以下、これら３図を用いて本参考例における動作を説明する。
【００４２】
図２において、ゲート線電極８と対向電極９に電圧Ｖを印加すると、液晶層５とソース線電極７と液晶層間の絶縁膜７６とゲート線電極とａ−Ｓｉ層間の絶縁膜８６それぞれの容量性負荷値の比で決まる電圧が各層にかかる。その分圧をＶ１、Ｖ２、Ｖ３とする。これらの関係を、図３を用いて説明する。
【００４３】
単位面積Ｓあたりの容量性負荷値Ｃは、層の比誘電率をε、層の厚みをｌ、真空の誘電率をε０とすると、以下の（１−１式）で表される。
Ｃ＝ε０×ε×Ｓ／ｌ …（１−１式）
一方、直列に接続した容量性負荷Ｃ１、Ｃ２、Ｃ３の分圧Ｖ１は、以下の（１−２式）で表される。
Ｖ１＝Ｖ＊Ｃ２＊Ｃ３／（Ｃ１＊Ｃ２＋Ｃ２＊Ｃ３＋Ｃ３＊Ｃ１）（１−２式）となる。
【００４４】
液晶層５、絶縁膜７６、８６それぞれの比誘電率、厚みをε１、ε２、ε３ｌ１、ｌ２、ｌ３とすると、（１−２式）の分圧Ｖ１は
Ｖ１＝Ｖ＊ε２＊ε３＊ｌ１／（ε１＊ε２＊ｌ３＋ε２＊ε３＊ｌ１＋ε３＊ε１＊ｌ２）（１−３式）
となり、電界強度Ｅ１は
Ｅ１＝Ｖ１／ｌ１
＝Ｖ＊ε２＊ε３／（ε１＊ε２＊ｌ３＋ε２＊ε３＊ｌ１＋ε３＊ε１＊ｌ２）
＝Ｖ／（ｌ１＋ｌ２＊ε１／ε２＋ｌ３＊ε１／ε３）（１−４式）
となる。
【００４５】
図４の構造では、ゲート線電極とａ−Ｓｉ層間の絶縁膜とソース線電極と液晶層間の絶縁膜をそれぞれ２層にしてパターニングすることでゲート線電極とａ−Ｓｉ層間、ソース線電極と液晶層間の絶縁は従来同等のまま、ゲート線電極と液晶層間の絶縁膜を薄くしている。このような構造にすることにより、（１−４式）であらわす電界強度Ｅ１の分母が小さくなり、結果的に液晶層にかかる電界強度を高くすることができ、ベンド配向への高速な転移が可能になる。
【００４６】
液晶層の比誘電率は液晶の透過率によって３〜８程度に変化し、絶縁膜として使用するＳｉＯｘ、ＳｉＮｘ、ＴａＯｘの比誘電率はそれぞれ約３．９、約６．４、約２３で、液晶の比誘電率のばらつきが均等な場合、図４の液晶層にかかる電界強度の方が従来の構造の電界強度（１−４式）よりも高くなることが多い。ベンド配向を有する液晶層を、初期のスプレイ配向からベンド配向に高速に転移させるためには液晶層にできるだけ高い電界強度を与えることが非常に有効であるため、本実施の形態のように絶縁膜を薄くすることは大変有効な手段となる。
【００４７】
（第１−２の参考例）
図５に、本参考例の第１−２の参考例の構造図を示す。
【００４８】
本図において、８はゲート線電極、７はソース線電極、３は画素電極、６４はチャネル保護膜、６５はａ−Ｓｉ層、６６はｎ＋ａ−Ｓｉ層、８６はゲート線電極とａ−Ｓｉ層間の絶縁膜、７６はソース線電極と液晶層間の絶縁膜、５は液晶層、９は対向電極、２１は透明画素電極であり、Ａは断面部を示す線である。
【００４９】
先の第１の参考例（誤解が生じ無いので第１−１の参考例をこの様に略記する。以下同様である。）では絶縁膜をそれぞれ２層にしたが、本図５に示すようにパターニングによりゲート線電極と液晶層間の絶縁膜厚みを薄くしても同等の効果が得られる。
【００５０】
（第１−３の参考例）
図６に第１−３の参考例の構成図を示す。
【００５１】
本図においても、８はゲート線電極、７はソース線電極、３は画素電極、６４はチャネル保護膜、６５はａ−Ｓｉ層、６６はｎ＋ａ−Ｓｉ層、８６はゲート線電極とａ−Ｓｉ層間の絶縁膜、７６はソース線電極と液晶層間の絶縁膜、５は液晶層、９は対向電極、２１は透明画素電極であり、Ａは断面を示す線である。
【００５２】
この構造では、ゲート線電極の膜厚を厚くした所定部厚膜型ゲート線とすることでゲート線上の液晶層の厚みが薄くなり、液晶層にかかる電界強度が高くなり、ベンド配向への転移を高速にすることができる。
【００５３】
ゲート線電極の膜厚は、通常０．２μｍから０．６μｍ程度だが、これを約２倍にすることで、液晶層の厚みを０．５μｍ程度薄くすることができる。
【００５４】
（第１−４の参考例）
図７に第１−４の参考例の構成図を示す。
【００５５】
本図においても、８はゲート線電極、７はソース線電極、３は画素電極、６４はチャネル保護膜、６５はａ−Ｓｉ層、６６はｎ＋ａ−Ｓｉ層、８６はゲート線電極とａ−Ｓｉ層間の絶縁膜、７６はソース線電極と液晶層間の絶縁膜、５は液晶層、９は対向電極、２１は透明画素電極であり、Ａは断面部を示す線であり、７０はゲート線電極の上に電気的に接触させて積層したソース線形成金属である。
【００５６】
この構造では、ゲート線形成金属の上にソース線形成金属を電気的に接触させて積層する一部接触型ゲート線とすることにより実質的にゲート線電極の膜厚を厚く、ゲート線上の液晶層の厚みを薄くし、液晶層にかかる電界強度を高くすることでベンド配向への転移を高速にすることができる。
【００５７】
ソース線電極の膜厚は通常０．２μｍから０．６μｍ程度であるため液晶層の厚みをそれだけ薄くすることができる。
【００５８】
（第１−５の参考例）
図８に第１−５の参考例の構成図を示す。
【００５９】
本図においても、８はゲート線電極、７はソース線電極、３は画素電極、６４はチャネル保護膜、６５はａ−Ｓｉ層、６６はｎ＋ａ−Ｓｉ層、８６はゲート線電極とａ−Ｓｉ層間の絶縁膜、７６はソース線電極と液晶層間の絶縁膜、５は液晶層、９は対向電極、２１は透明画素電極であり、Ａは断面部を示す線であり、７１３はゲート線電極の上に電気的に接触させずに積層したソース線形成金属である。
【００６０】
この構造では、ゲート線電極と対向電極の間にソース線形成金属を電気的に絶縁して介在させる非接触型ゲート線とすることでゲート線上の液晶層の厚みを薄くし、液晶層にかかる電界強度を高くすることでベンド配向への転移を高速にすることができる。
【００６１】
（第１−６の参考例）
図９に第１−６の参考例の構成図を示す。本図において、１は第１の基板、８はゲート線電極、７はソース線電極、６は画素トランジスタ、２は第２の基板、９１は第１の基板のゲート線電極と向かい合う位置に形成した第１の対向電極、９２は第１の対向電極とは電気的に絶縁された第２の対向電極である。この分割型対向電極の構造では、第１の対向電極と第２の対向電極を電気的に絶縁しているため、電圧変動が液晶層や絶縁膜の容量性負荷を介して画素電極や画素トランジスタに影響することを防ぎながらゲート線電極上の液晶層に任意の電界強度を与えることができ、ベンド配向への転移を高速に行うことができる。通常の映像表示時には第１の対向電極と第２の対向電極を同電位にすることにより、対向電極がパターニングされていない従来の液晶表示装置と全く同等の画質を得ることができる。
【００６２】
（第１−７の参考例）
図１０に第１−７の参考例の液晶表示装置の断面図を示す。本図において１は第１の基板、８はゲート線電極、７はソース線電極、８７は絶縁膜、２は第２の基板、１１は第１の基板のゲート線電極と向かい合う位置に形成したブラックマトリクス用金属、１２はカラーフィルター、５は液晶層、９１は第２の基板上全面にほぼ均一に形成した１層目の対向電極、９２は第１の基板のゲート線と向かい合う位置に形成した２層目の対向電極である。この対峙部厚膜対向電極の構造では、ゲート線上と向かい合う対向電極を２層にすることでゲート線上の液晶層の厚みが薄くなり電界強度を高くすることができ、ベンド配向への転移を高速に行うことができる。
【００６３】
（第１−８の参考例）
図１１に第１−８の参考例の液晶表示装置の断面図を示す。本図においても１は第１の基板、８はゲート線電極、７はソース線電極、８７は絶縁膜、２は第２の基板、１１は第１の基板のゲート線電極と向かい合う位置に形成したブラックマトリクス用金属、１２１は赤等第１の色彩のカラーフィルター、１２２は青等他の第２の色彩のカラーフィルター、９は対向電極、５は液晶層である。
【００６４】
この構造では第２の基板上で、第１の基板のゲート線電極と向かい合う部分でカラーフィルター形成樹脂を積層することによりこの部分の対向電極を盛り上げゲート線上の液晶層の厚みを薄くすることにより、液晶層の電界強度を高くすることができ、ベンド配向への転移を高速にすることができる。
【００６５】
（第１−９の参考例）
図１２に第１−９の参考例の液晶表示装置の断面図を示す。本図においても１は第１の基板、８はゲート線電極、７はソース線電極、８７は絶縁膜、２は第２の基板、１１は第１の基板のゲート線電極と向かい合う位置に形成したブラックマトリクス用金属、１２はカラーフィルター、１１１は第１の基板のゲート線に向かい合う部分に形成した柱状スペーサ、９は対向電極、５は液晶層である。
【００６６】
この構造では第２の基板上で、第１の基板のゲート線電極と向かい合う部分に柱状スペーサを形成し、この柱状スペーサと液晶層の間に対向電極を形成することによりゲート線上の液晶層の厚みを薄くし、液晶層の電界強度を高くすることができ、ベンド配向への転移を高速にすることができる。
【００６７】
なお、ここに第１の実施の形態から第９の実施の形態まで９つの実施の形態で液晶パネルの構造を説明したが、各実施の形態のうち複数を組み合わせてゲート線上の液晶層の厚みを薄くすることはいずれか単独で実施するよりもより高い効果を得やすく、かつ、対向電極を分割してゲート線に向かい合う電極に任意の電圧を印加すればさらに効果は増大する。
【００６８】
｛第１の発明群｝
本発明群は、液晶層の転移のために、画素電極と対向電極間に通常の映像の表示時よりも高い電圧をかけたり、２種の電圧をかけたりし、更にそのための手段、デューティ比等に工夫を凝らしたものである。
【００６９】
（第１−１の実施の形態）
図１３に、本実施の形態の液晶装置の画素の回路を中心とした構成を示す。本図において、３は、画素電極である。６は、画素トランジスタである。７は、ソース線である。７１は、次のソース線である。８は、ゲート線である。８１は、前のゲート線である。９は、対向電極である。１０は、全蓄積容量に接続する共通電極である。Ｃｇｄは、画素トランジスタのゲート・ドレイン間の容量である。Ｃｓｔは、画素電極に接続し、共通電極との間に形成する蓄積容量である。Ｃｌｃは、液晶層の容量である。Ｃｇｓは、画素トランジスタのゲート・ソース間の容量である。
【００７０】
図１４に、この画素の構造を中心とした平面と断面の概略を示す。本図において、６は画素トランジスタ、２１は透明画素電極、Ｃｓｔは画素電極に接続し、共通電極との間に形成する蓄積容量、Ｃｌｃは液晶層の容量、７はソース線、７１は次のソース線、８はゲート線、８１は前のゲート線、９は対向電極、１０は全蓄積容量に接続する共通電極である。
【００７１】
図１５に、１画素当たりの寸法の１例を示す。本図において、Ｗｔは、画素の幅である。Ｌｔは、画素の長さである。Ｗｐは、画素電極の幅である。Ｌｐは、画素電極の長さである。Ｗｓは、ソース線の幅である。Ｗｇは、ゲート線の幅である。そして、１画素当たりの面積３００００［μｍ２］中で、画素電極の面積は１８２２４μｍ２となり、１画素の６０．７％となる。
【００７２】
これら図１３、１４、１５に示す本実施の形態の液晶装置の動作を図１６に示す。
【００７３】
図１６において、Ｖｇは、ゲート線の電圧である。Ｖｓは、ソース線の電圧である。Ｖｐは、画素電極の電圧である。Ｖｃｃは、共通電極の電圧である。Ｖｃは、対向電極の電圧である。
【００７４】
通常映像表示時には、ゲート線の電圧Ｖｇを画素トランジスタがオン状態になるまで変化させて、ソース線の電圧Ｖｓを画素電極２１、蓄積容量Ｃｓｔ、液晶容量Ｃｌｃに充電する。画素電極の電圧Ｖｐはソース線の電圧Ｖｓと等しくなる。
【００７５】
対向電極の電圧Ｖｃは画素電極の電圧Ｖｐとの間で液晶の透過率が十分に変化する範囲であれば良く、通常ＶｃとＶｐの電位差Ｖｐｃは０Ｖ〜５Ｖ程度に設定する。液晶層をベンド配向させるには更に高い電位差を連続的に液晶層にかける異電位差連続印加ステップが必要である。ベンド配向に転移するために必要な電位差、時間は液晶材料によって異なるが、６Ｖ以上の電位差を画素電極と対向電極の間に与えることで１秒以内に転移が完了する材料があることが実験的に確認できている。液晶表示装置としては、この転移時間が短いほど良く、数秒から１０秒以内であることが望ましいが、そのためにはより大きな電位差（２０Ｖから３０Ｖ程度）を与えたり、液晶材料を選択することとなる。液晶層がベンド配向に転移するための電位差はできるだけ広い面積で与えることが望ましく、画素電極と対向電極の間に与えることが図１５に示すように面積的にもっとも有効である。
【００７６】
（第１−２の実施の形態）
図１３、図１４、図１５を用いて第２の実施の形態における動作を図１７で説明する。
【００７７】
図１７においてＶｇはゲート線の電圧である。Ｖｓはソース線の電圧である。Ｖｐは画素電極の電圧である。Ｖｃｃは共通電極の電圧である。Ｖｃは対向電極の電圧である。このような構成の液晶パネルにおける通常映像表示時の動作は第１の実施の形態と同様で、ＶｃとＶｐの間の電位差Ｖｐｃは０Ｖ〜５Ｖである。ベンド配向に転移させるために画素電極と対向電極との間に６Ｖ以上の第１種の電位差を連続的に与えた場合、液晶パネルの構造や液晶材料によっては、転移状態が進まず膠着する部分が発生し、そこだけが１０秒以上かかっても転移できないことがある。そのようなパネルあるいは液晶材料の条件の場合には対向電極の電圧Ｖｃを画素電極の電圧Ｖｐに近づけ、液晶層にかかる電位差Ｖｐｃを小さい第２種の電位差にして液晶素子の配向を初期状態に戻してから再度高い第１種の電位差を与える。このことにより、元々ベンド状態に転移していた液晶素子は初期状態に戻してから再度電位差をかけ直しても転移しやすいためすぐに転移し、転移状態が膠着していた部分は新たに電位差をかけ直すことで転移しやすくなるため、結果的にパネル全面において短時間にベンド配向に転移させることができる。
【００７８】
図１８に本発明による液晶装置の制御手段の構成の一例を示す。本図において、２０５は液晶パネル、２０４は液晶パネルコントローラ、２０３は各種電源電圧発生回路である。液晶パネルコントローラ２０４には外部より起動スイッチ２１０が接続されている。この起動スイッチ２１０は液晶パネルコントローラ２０４の内部のカウンタ２１１とそれに続く２１２の切換手段Ａが接続され、起動直後はこのカウンタにより、所定の期間をカウントした後、通常映像信号発生部２１３からの映像信号を液晶パネル２０５へ印加する。所定の期間をカウント中は、２１４の電圧発生手段１と２１５の電圧発生手段２を周期カウンタ２１６で設定された所定の周期で、２１７の切換手段Ｂにより切換える。これらの電圧発生手段は単一の電圧を発生するとは限定されない。液晶パネル２０５がアクティブ・マトリクスであり、この中の画素電極−対向電極間の液晶印加実効電位差がポイントであるため、対向電極電圧は勿論、画素電極電圧を決める要因となるソース線電圧、ゲート線電圧、後述する蓄積容量の共通電極電圧の内、必要な電圧を組み合わせて切換えることとなる。
【００７９】
また、ここで述べた起動直後の所定の期間とは約０．１秒ないし１０秒程度の時間であり、周期カウンタ２１６で設定された所定の周期とは約０．１秒から５秒程度の時間である。
【００８０】
本実施の形態において、画素電極と対向電極の間の電位差Ｖｐｃを第２種の電位差にする時間はベンド配向への転移を初期状態に戻すための時間であるため、画素電極と対向電極の間に第１種の電位差を付与する時間に比べて同等以下の短い時間にするほうが液晶パネル全体でのベンド配向への転移は短時間で終了する。図１９に示すように、Ｖｐｃに高い第１種の電位差をかけている第１種の電位差印加ステップのデューティ比が０．５を超えると転移時間は格段に短くなる。この第１種の電位差印加ステップは大体０．１秒から３秒程度である。また、第１種の電位差印加ステップと第２種の電位差印加ステップの切り替え時に発生する対向電極の電圧変化のスルーレートの高低はベンド配向への転移時間に直接影響しない。このため、対向電極のように高い負荷の電極を駆動する場合であっても小さい電流駆動能力しか持たない駆動素子を用いて緩やかに電圧を変化させても同様の効果を得ることができる。図２０に示すように、周期Ｔの繰り返し制御ステップで電位差Ｖｐｃを変化させるとき、電位差の変化に要する時間ｔｒ、ｔｆはそれぞれ周期Ｔの３０％まで達しても速やかな転移が行える。
【００８１】
図２１で示すような回路で容量Ｃ［Ｆ］をｔ秒でＶ［Ｖ］変化させるために必要な電流ｉ［Ａ］は次式で得られ、
ｉ＝Ｃ＊Ｖ／ｔ
１０［ｕＦ］の容量の対向電極を、３００ミリ秒で１０［Ｖ］変化させるために必要な電流駆動能力は０．３３［ｍＡ］となり、汎用的なオペアンプないしは低消費電力型のオペアンプ等の電流駆動素子で回路を構成することができる。また、図示はしないが、パルス状信号源と直列抵抗によって容量素子を駆動しても良い。
【００８２】
（第１−３の実施の形態）
図１３、図１４、図１５を用いて第１の実施の形態において共通電極の電位変化により第１種の電位差を大きくする共通電極電位変動利用型の場合を第３の実施の形態としてその動作を図２２で説明する。構成は第１の実施の形態と同じである。
【００８３】
図２２においてＶｇはゲート線の電圧である。Ｖｓはソース線の電圧である。Ｖｐは画素電極の電圧である。Ｖｃｃは共通電極の電圧である。Ｖｃは対向電極の電圧である。
【００８４】
画素トランジスタがオンの期間、画素電極にはソース線の電位Ｖｓが書き込まれ、画素トランジスタがオフになるとき、ゲート線の電圧変化ΔＶｇに合わせて（２−１式）で算出される突き抜け電圧分ΔＶｐ１だけ画素電極の電位Ｖｐは変化する。さらに、画素トランジスタがオフの期間に蓄積容量の電極となっている共通電極の電位ＶｃｃをΔＶｃｃだけ変化させると（２−２式）で算出される突き抜け電圧ΔＶｐ２が画素電極に発生する。本図に示す信号変化の場合、ΔＶｐ１よりもΔＶｐ２を大きくすることでソース線から書き込んだ電位Ｖｓよりも高い電位を画素電極に与えることができ、画素電極と対向電極との間の電位差Ｖｐｃがより大きくなり、液晶層のベンド配向への転移時間を短くすることができる。
【００８５】
ΔＶｐ１＝ΔＶｇ＊Ｃｇｄ／（Ｃｓｔ＋Ｃｌｃ＋Ｃｇｄ）（２−１式）
ΔＶｐ２＝ΔＶｃｃ＊Ｃｓｔ／（Ｃｓｔ＋Ｃｌｃ＋Ｃｇｄ）（２−２式）
この時、図２３に示すように共通電極の電圧をゲート信号の電圧と同じにしてもＶｐｃを十分大きくでき、かつ、電圧の共用により電源回路の規模を小さくすることができる。
【００８６】
（第１−４の実施の形態）
図２４は液晶パネルの１画素分の構成図を示す。本図において６は画素トランジスタ、３は画素電極、Ｃｇｄは画素トランジスタのゲート・ドレイン間容量、Ｃｓｔは画素電極に接続し、前段のゲート線との間に形成する蓄積容量、Ｃｌｃは液晶層の容量、Ｃｇｓは画素トランジスタのゲート・ソース間容量、７はソース線、７１は次のソース線、８はゲート線、８１は前のゲート線、１１は対向電極である。このような構成の液晶パネルは前段ゲート方式と呼ばれ、図１３、図１４に示す構成に比べて共通電極を削除できるため開口率を高くできる。
【００８７】
図２５に画素構造の平面・断面概略図を示す。６は画素トランジスタ、２１は透明画素電極、Ｃｓｔは画素電極に接続し、前段のゲート線との間に形成する蓄積容量、Ｃｌｃは液晶層の容量、７はソース線、７１は次のソース線、８はゲート線、８１は前のゲート線、９は対向電極である。
【００８８】
図２６に１画素当たりの寸法の１例を示す。Ｗｔは画素の幅、Ｌｔは画素の長さＬｔ、Ｗｐは画素電極の幅、Ｌｐは画素電極の長さ、Ｗｓはソース線の幅、Ｗｇはゲート線の幅、Ｗｓｔは蓄積容量部の長辺、Ｌｓｔは画素電極とゲート線の間隙であり、１画素当たりの面積３００００［μｍ＾２］中、画素電極の面積は１８５６４［μｍ＾２］で１画素の６１．９％となる。
【００８９】
図２４、図２５、図２６を用いて第２の実施の形態において前段のゲート線の電位変化により第１種の電位差を大きくするゲート線電位変動利用型の場合を第４の実施の形態としてその動作を図２７で説明する。
【００９０】
本図においてＶｇはゲート線の電圧、Ｖｓはソース線７の電圧、Ｖｐは画素電極の電圧、Ｖｇ−は前段のゲート線８１の電圧、Ｖｃは対向電極の電圧である。
【００９１】
通常映像表示時には、ゲート線の電圧Ｖｇを画素トランジスタがオン状態になるまで変化させて、ソース線の電圧Ｖｓを透明画素電極２１、蓄積容量Ｃｓｔ、液晶容量Ｃｌｃに充電する。透明画素電極２１の電圧Ｖｐはソース線７の電圧Ｖｓと等しくなる。
【００９２】
画素トランジスタがオフになるとき、ゲート線の電圧変化ΔＶｇに合わせて（２−３式）で算出される突き抜け電圧分ΔＶｐ３だけ画素電極の電位Ｖｐは変化する。さらに、画素トランジスタがオフの期間に蓄積容量の電極となっている前段のゲート線の電位Ｖｇ−をΔＶｇ−だけ変化させると（２−４式）で算出される突き抜け電圧ΔＶｐ４が画素電極に発生する。図２７に示す信号変化の場合、ΔＶｐ３よりもΔＶｐ４を大きくすることでソース線から書き込んだ電位Ｖｓよりも高い電位を画素電極に与えることができ、画素電極と対向電極との間の電位差Ｖｐｃがより大きくなり、液晶層のベンド配向への転移時間を短くすることができる。
【００９３】
ΔＶｐ３＝ΔＶｇ＊Ｃｇｄ／（Ｃｓｔ＋Ｃｌｃ＋Ｃｇｄ）（２−３式）
ΔＶｐ４＝ΔＶｇ−＊Ｃｓｔ／（Ｃｓｔ＋Ｃｌｃ＋Ｃｇｄ）（２−４式）
図２６に示すように一画素中で画素電極が占める面積割合は６１．９％とかなり大きいため、画素電極と対向電極との間に大きい電位差をかけることは非常に有効である。
【００９４】
このような構成の液晶パネルにおける通常映像表示時のＶｃとＶｐの間の電位差Ｖｐｃは０Ｖ〜５Ｖである。ベンド配向に転移させるために画素電極と対向電極との間に６Ｖ以上の電位差を直流で与えた場合、液晶パネルの構造や液晶材料によっては、転移状態が進まず膠着した液晶素子が１０秒以上かかっても転移できないことがある。そのようなパネルあるいは液晶材料の条件の場合には対向電極の電圧Ｖｃを画素電極の電圧Ｖｓに近づけ、液晶層にかかる電位差Ｖｐｃを小さい第２種の電位差にして液晶素子の配向を初期状態に戻してから再度高い第１種の電位差を与えることにより、転移状態が膠着していた部分に新たに電位差をかけ直し、結果的にパネル全面において短時間にベンド配向に転移させることができる。
【００９５】
本実施の形態では前段のゲート線との間に蓄積容量を設けたが後段のゲート線との間に蓄積容量を設けた場合でも同等の動作で同等の効果が得られる。
【００９６】
（第１−５の実施の形態）
図２８に示す画素の電極電位のタイムチャートと図１３の接続図を用いて第１−５の実施の形態における動作を説明する。
【００９７】
図２８において、太い点線は対向電極電位を、細い点線はゲート線電位を、細い実線はソース線電位を、太い実線は画素電極電位を示す。下部のＶｐｃは画素電極・対向電極間電位差の変動を示す。Ｔｃは通常映像表示期間、Ｔ１２は１回目の第２種の電位差印加ステップ、Ｔ１１は１回目の第１種の電位差印加ステップ、Ｔ２２は２回目の第２種の電位差印加ステップ、Ｔ２１は２回目の第１種の電位差印加ステップである。各種の画素電極電位の変動要因を示している。
【００９８】
本図において、Ｔ１２、Ｔ１１、Ｔ２２、Ｔ２１は繰り返し制御ステップで繰り返している。液晶層をベンド配向させるための駆動期間の１回目の第２種の電位差印加ステップＴ１２が開始すると、対向電極電位を通常映像表示期間とは異なる第２の電位とする。画素電極電位は、液晶容量を介して対向電極と接続し、この瞬間には画素トランジスタがオフで電流の供給がないため、対向電極電位の変化分ΔＶｃｏｍに対して、（２−５式）に示すΔＶｐ５だけ、本図の期間Ｔ１２の左側に示すように対向電極電位が変化した方向に電位が変化する。
【００９９】
ΔＶｐ５＝ΔＶｃｏｍ＊Ｃｌｃ／（Ｃｌｃ＋Ｃｓｔ＋Ｃｇｄ）（２−５式）
ゲート線電位が画素トランジスタをオンからオフにするときの電位変動分ΔＶｇが画素電極に影響を与える電位変動分は（２−６式）に示すΔＶｐ６となる。
【０１００】
ソース線電位を、対向電極電位にΔＶｐ６を上乗せした電位とし、画素トランジスタをオフにすると、画素電極電位は本図の期間Ｔ１２の中央ゲート電極電位変動に示すようにΔＶｐ６だけ下がり、対向電極電位との電位差はほぼゼロの第２種の電位差になる。
【０１０１】
ΔＶｐ６＝ΔＶｇ＊Ｃｇｄ／（Ｃｌｃ＋Ｃｓｔ＋Ｃｇｄ）（２−６式）
以降、１回目の第２種の電位差印加ステップＴ１２中は、画素トランジスタがオンで画素電極にソース線電位を充電している充電小ステップ中を除いては画素電極電位と対向電極電位との電位差はほぼゼロの第２種の電位差になる。
【０１０２】
１回目の第２種の電位差印加ステップＴ１２から１回目の第１種の電位差印加ステップＴ１１に移行すると、画素電極電位と対向電極電位との電位差を第１種の電位差にするために対向電極電位を第１の電位に変化させ、画素電極電位はその影響を受けて本図の期間Ｔ１１内左側に示す対向電極電位変動のように対向電極電位が変化した方向に変化する。
【０１０３】
ソース線電位を１回目の第２種の電位差印加ステップＴ１２同様、対向電極電位にΔＶｐ６を上乗せした電位として画素トランジスタを充電小ステップで一度オン・オフすると、画素電極電位は第２種の電位差印加ステップの対向電極電位とほぼ等しい電位までは下がるが、第１種の電位差印加ステップでは画素電極電位と対向電極電位の間の電位差が液晶層がベンド配向に転移するのに必要な十分に大きい第１種の電位差になるように対向電極電位を設定する。以降、１回目の第１種の電位差印加ステップＴ１１中は、画素電極電位と対向電極電位の間の電位差は、液晶層のベンド配向への転移に必要な第１種の電位差が与えられている。
【０１０４】
２回目の第２種の電位差印加ステップＴ２２が開始すると、対向電極電位が変化するため画素電極電位はその影響で本図の期間Ｔ２２の左側の対向電極電位変動（注、この文の記載は期間Ｔ１２内に在る。）に示すように対向電極電位が変化した方向に電位が変化する。充電小ステップで画素トランジスタのオン・オフを一度行うと、１回目の第２種の電位差印加ステップＴ１２と同様に、画素トランジスタがオンになり画素電極にソース線電位を充電している時以外は画素電極・対向電極間の電位差はほぼゼロの第２種の電位差になる。
【０１０５】
２回目の第２種の電位差印加ステップＴ２２から２回目の第１種の電位差印加ステップＴ２１に移行すると、１回目の第１種の電位差印加ステップ同様に画素電極・対向電極間の電位差は、液晶層のベンド配向への転移に必要な第１種の電位差が与えられている。
【０１０６】
以降、液晶層のベンド配向への転移が完了するまで繰り返し制御ステップで第２種の電位差印加ステップと第１種の電位差印加ステップを交互に繰り返し、第２種の電位差印加ステップでは期間開始後１回目の画素トランジスタがオンするまでの間および充電小ステップで画素トランジスタがオンしている時以外は画素電極・対向電極間の電位差はほとんどゼロの第２種の電位差になり、第１種の電位差印加ステップでは期間開始後１回目の画素トランジスタがオンするまでの間以外は画素電極・対向電極間は液晶層がベンド配向へ転移するために必要な十分に大きな第１種の電位差が与えられている。
【０１０７】
画素電極と対向電極の間の電位差を大きくし，ベンド配向の核の発生とベンド領域の拡大を行う第１種の電位差印加ステップと、画素電極と対向電極の間の電位差を小さくしてベンド配向の核が発生しなかったりベンド領域の拡大が行われなかった部分の液晶層の再整列を行う第２種の電位差印加ステップを交互に与えることで、パネル全面を高速にベンド配向に転移させることができる。
【０１０８】
第２種の電位差印加ステップ中の画素電極・対向電極間の第２種の電位差はゼロであることが望ましいが、図２９に示すように±１Ｖの範囲内であれば面内転移完了時間にあまり影響しない。蓄積容量Ｃｓｔ、液晶容量Ｃｌｃ、ゲート・ドレイン間容量Ｃｇｄはその膜厚、膜質によってパネル内部でもパネル相互にもバラツキがあり、ゲート線電位の変化の影響を受ける画素電極電位の変化分ΔＶｐ６にもバラツキが生じるが、そのバラツキが±１Ｖ以内に収まれば、第２種の電位差印加ステップのソース線電位をパネル毎に調整する必要はなくソース線電位を固定した駆動方法を決定できる。
【０１０９】
（第１−６の実施の形態）
図３０、図１３を用いて第５の実施の形態の第２種の電位差印加ステップに画素トランジスタのオン・オフタイミングに合わせてソース線電位を変化させる場合の第６の実施の形態の動作を説明する。
【０１１０】
図３０に、図１３で示す画素の電極電位のタイムチャートを示す。
【０１１１】
本図において、太い点線は対向電極電位を、細い点線はゲート線電位を、細い実線はソース線電位を、太い実線は画素電極電位を示す。下部のＶｐｃは画素電極・対向電極間電位差、Ｖｓｃはソース線・対向電極間電位差である。Ｔｃは通常映像表示期間、Ｔ１２は１回目の第２種の電位差印加ステップ、Ｔ１１は１回目の第１種の電位差印加ステップ、Ｔ２２は２回目の第２種の電位差印加ステップ、Ｔ２１は２回目の第１種の電位差印加ステップである。また、各種の画素電極電位の変動要因を示す。
【０１１２】
本図において、液晶層をベンド配向させるための駆動期間の１回目の第２種の電位差印加ステップＴ１２が開始すると、対向電極電位を通常映像表示期間とは異なる第２の電位とする。画素電極電位は、対向電極電位変動分をΔＶｃｏｍとすると（２−５式）に示す様にΔＶｐ５だけ、本図の対向電極電位変動に示すように対向電極電位が変化した方向に電位が変化する。ソース線電位を、対向電極電位にΔＶｐ６を上乗せした電位とし、充電小ステップで画素トランジスタを一度オン・オフすると、画素電極電位は本図のゲート電極電位変動に示すように、ΔＶｐ６だけ下がり、対向電極との電位差はほぼゼロの第２種の電位差になる。ソース線電位は画素トランジスタがオフしている間は対向電極電位とほぼ等しい電位とし、Ｖｓｃのように、充電小ステップで画素トランジスタのオン・オフタイミングに合わせて変動させる。
【０１１３】
以降、１回目の第２種の電位差印加ステップＴ１２中は、通常映像表示期間と同様のタイミングで画素トランジスタがオン・オフし、その都度ソース線電位は変化し、画素トランジスタがオフしているときには画素電極・対向電極および画素電極・ソース線電位間は電位差はほぼゼロの第２種の電位差になる。
【０１１４】
この画素トランジスタがオフしているときのソース線電位は、対向電極との間の電位差が±１Ｖの範囲内であれば面内転移完了時間に何ら変わりはない。このことは第５の実施の形態で画素電極と対向電極の間の電位差が±１Ｖの範囲内であれば面内転移完了時間にあまり影響しないと図２９を用いて述べたのと同様である。
【０１１５】
１回目の第２種の電位差印加ステップＴ12から１回目の第１種の電位差印加ステップＴ11に移行すると、画素電極と対向電極の間の電位差を第１種の電位差にするため対向電極電位を第１の電位にし、画素電極電位はその影響を受けて本図の期間Ｔ11左側対向電極電位変動に示すように対向電極電位の変化した方向にΔＶｐ５だけ変化する。ソース線電位を１回目の第２種の電位差印加ステップＴ12同様、対向電極電位（第２の電位）にΔＶｐ６を上乗せした電位として充電小ステップで画素トランジスタを一度オン・オフすると、画素電極電位は第２種の電位差印加ステップの対向電極電位（第２の電位）とほぼ等しくなる。
【０１１６】
この第１種の電位差印加ステップにおいてもソース線電位は画素トランジスタのオン・オフのタイミングで電位が変化し、第１種の電位差印加ステップでは画素電極・対向電極間およびソース線・対向電極間の電位差は、第２種の電位差印加ステップの対向電極電位と第１種の電位差印加ステップの対向電極電位の電位差とほぼ等しい。そこで、第１種の電位差印加ステップの対向電極電位と第２種の電位差印加ステップの対向電極電位の電位差が液晶層の転移に必要な第１種の電位差になるようそれぞれの期間の対向電極電位を設定する。
【０１１７】
２回目の第２種の電位差印加ステップＴ２２が開始すると、対向電極電位が変化するため画素電極電位はその影響で本図の期間Ｔ２２内左側の対向電極電位変動で示す（説明の記載は期間Ｔ１２内。）ように対向電極電位の変化した方向に電位が変化する。その後の画素トランジスタによる充電動作で画素電極電位は１回目の第２種の電位差印加ステップと同様の変化をし、対向電極電位とほぼ等しくなる。
【０１１８】
２回目の第２種の電位差印加ステップＴ２２から２回目の第１種の電位差印加ステップＴ２１に移行すると、対向電極電位は１回目の第１種の電位差印加ステップと同様に変化し、この期間中も画素トランジスタによる画素電極の充電で、１回目の第１種の電位差印加ステップＴ１１と同様の第１種の電位差が画素電極・対向電極間に与えられる。
【０１１９】
以降、液晶層のベンド配向への転移が完了するまで繰り返し制御ステップで第２種の電位差印加ステップと第１種の電位差印加ステップを交互に繰り返し、第２種の電位差印加ステップでは画素電極・対向電極間およびソース線・対向電極間の電位差はほとんどゼロの第２種の電位差になり、第１種の電位差印加ステップでは画素電極・対向電極間には液晶層がベンド配向に転移するために必要な十分に大きな第１種の電位差が与えられる。
【０１２０】
この例では、第５の実施の形態で述べた動作に加えて、第２種の電位差印加ステップ中に、面内の大部分の面積を占める画素電極およびソース線と対向電極との電位差をゼロにするので、ソース線電位を変動させる煩雑さはあるが、第５の実施の形態よりも液晶層のベンド配向への転移を更に高速化できる。
【０１２１】
（第１−７の実施の形態）
図３１、図１３を用いて第５の実施の形態の画素トランジスタのオンによる画素電極充電を液晶層をベンド配向させるための駆動期間の初期に１回行う場合の第１−７の実施の形態の動作を説明する。
【０１２２】
図３１に、図１３で示す画素の電極電位のタイムチャートを示す。
図３１において、太い点線は対向電極電位を、細い点線はゲート線電位を、細い実線はソース線電位を、太い実線は画素電極電位を示す。下部のＶｐｃは画素電極・対向電極間電位差である。Ｔｃは通常映像表示期間、Ｔ１２は１回目の第２種の電位差印加ステップ、Ｔ１１は１回目の第１種の電位差印加ステップ、Ｔ２２は２回目の第２種の電位差印加ステップ、Ｔ２１は２回目の第１種の電位差印加ステップである。また、各種の画素電極電位の変動要因をも示す。
【０１２３】
本図において、液晶層をベンド配向させるための駆動期間の１回目の第２種の電位差印加ステップＴ１２が開始すると、対向電極電位を通常映像表示期間とは異なる第２の電位とする。画素電極電位は、対向電極電位変動の影響を受けて、本図の期間Ｔ１２内の対向電極電位変動に示すように対向電極電位が変化した方向にΔＶｐ５だけ電位が変化する。ソース線電位を、対向電極電位にΔＶｐ６を上乗せした電位とし、画素トランジスタを一度オン・オフすると、画素電極電位は本図のゲート電極電位変動に示すようにΔＶｐ６だけ下がり、対向電極電位とほぼ等しくなる。以降、１回目の第２種の電位差印加ステップＴ１２中は、ゲート線電位の変化はなく、画素電極電位と対向電極電位１の電位差はほぼゼロの第２種の電位差のままである。
【０１２４】
１回目の第２種の電位差印加ステップＴ12から１回目の第１種の電位差印加ステップＴ１１に移行すると、画素電極・対向電極間の電位差を第１種の電位差にするため対向電極電位を第１の電位にし、画素電極電位はその影響を受けて本図の期間Ｔ１１内左側対向電極電位変動に示すように対向電極電位の変化した方向にΔＶｐ５だけ変化する。第１種の電位差印加ステップに移行しても画素トランジスタオンによる画素電極の充電は行われないため画素電極の電位は対向電極電位の変動により影響を受けた電位を維持し、画素電極・対向電極間の電位差が液晶層のベンド配向への転移に必要な十分に大きい第１種の電位差になるように対向電極電位を設定する。
【０１２５】
２回目の第２種の電位差印加ステップＴ22が開始すると、対向電極電位を第２の電位に変化するため画素電極電位はその影響で本図の期間Ｔ１１から期間Ｔ22への移行部に示す対向電極電位変動に示すように対向電極電位が変化した方向に電位が変化するが、その電位は１回目の第２種の電位差印加ステップＴ12のゲート電極電位変動での画素電極電位と等しく、対向電極電位との電位差はほぼゼロの第２種の電位差になる。
【０１２６】
２回目の第２種の電位差印加ステップＴ２２から２回目の第１種の電位差印加ステップＴ２１に移行すると、対向電極電位は１回目の第１種の電位差印加ステップと同様に第１の電位に変化し、この期間中も画素電極の充電は行われず、１回目の第１種の電位差印加ステップと同様の第１種の電位差が画素電極・対向電極間には与えられる。
【０１２７】
以降、液晶層のベンド配向への転移が完了するまで繰り返し制御ステップで第２種の電位差印加ステップと第１種の電位差印加ステップを交互に繰り返し、第２種の電位差印加ステップでは画素電極・対向電極間の電位差はほとんどゼロの第２種の電位差になり、第１種の電位差印加ステップでは画素電極・対向電極間には液晶層が転移するために必要な十分に大きな第１種の電位差が与えられる。
【０１２８】
この例では、画素トランジスタのオン・オフタイミングを通常映像表示期間とは変えるという煩雑さはあるが、第２種の電位差印加ステップ中の画素トランジスタオンによる画素電極充電回数が通常タイミングよりも少ないため、画素電極・対向電極間電位差がゼロの時間が第２種の電位差印加ステップ中に多くなり、第５の実施の形態よりも液晶層のベンド配向への転移を高速化できる。
【０１２９】
なお、画素電極の充電が１回の画素トランジスタのオンでは不十分な場合や、液晶層をベンド配向に転移させるための駆動期間が通常の映像表示期間に対して非同期に開始し、画素トランジスタを確実にオンにするために回数のマージンが必要な場合には、液晶層をベンド配向に転移させるための駆動期間の初めの画素トランジスタオンによる画素電極充電を１回ではなく数回行っても効果にあまり影響しない。
【０１３０】
また、１回目の画素トランジスタのオンは、通常の映像表示タイミングから、液晶層をベンド配向させるための駆動への切り替えを済ませた後、１フィールド期間（通常１６．７ミリ秒）以内に行なわれる。
【０１３１】
（第１−８の実施の形態）
図３２、図１３を用いて第５の実施の形態の充電小ステップでの画素トランジスタのオンによる画素電極充電を液晶層をベンド配向させるための駆動期間内の第１種の電位差印加ステップ、第２種の電位差印加ステップそれぞれの初期に１回行う場合の第８の実施の形態の動作を説明する。
【０１３２】
図３２は、図１３で示す画素の電極電位のタイムチャートを示す。
【０１３３】
本図において、太い点線は対向電極電位、細い点線はゲート線電位、細い実線はソース線電位、太い実線は画素電極電位である。下部のＶｐｃは画素電極・対向電極間電位差である。Ｔｃ通常映像表示期間、Ｔ１２は１回目の第２種の電位差印加ステップ、Ｔ１１は１回目の第１種の電位差印加ステップ、Ｔ２２は２回目の第２種の電位差印加ステップ、Ｔ２１は２回目の第１種の電位差印加ステップである。また、各種の画素電極電位の変動要因を示す。
【０１３４】
図３２において、液晶層をベンド配向させるための駆動期間の１回目の第２種の電位差印加ステップＴ１２が開始すると、対向電極電位を通常映像表示期間とは異なる第２の電位にする。画素電極電位は対向電極電位変動の影響を受けて、本図の期間Ｔ１２内の左側の対向電極電位変動に示すように対向電極電位が変化した方向に電位がΔＶｐ５だけ変化する。
【０１３５】
ソース線電位を、対向電極電位にΔＶｐ６を上乗せした電位とし、充電小ステップで画素トランジスタを一度オン・オフすると、画素電極電位は期間Ｔ１２内中央のゲート電極電位変動に示すようにΔＶｐ６だけ下がり、対向電極電位とほぼ等しくなる。以降、１回目の第２種の電位差印加ステップＴ１２中は、ゲート線電位の変化はなく、画素電極・対向電極間の電位差はほぼゼロの第２種の電位差のままである。
【０１３６】
１回目の第２種の電位差印加ステップＴ12から１回目の第１種の電位差印加ステップＴ11に移行すると、画素電極・対向電極間の電位差を第１種の電位差にするため対向電極電位を第１の電位にし、画素電極電位はその影響を受けて期間Ｔ11の左側対向電極電位変動に示すように対向電極電位が変化した方向にΔＶｐ５だけ変化する。ソース線電位を１回目の第２種の電位差印加ステップＴ12同様、対向電極電位（第２の電位）にΔＶｐ６を上乗せした電位として充電小ステップで画素トランジスタを一度オン・オフすると画素電極電位はゲート電極電位変動と同様に、第２種の電位差印加ステップの対向電極電位（第２の電位）とほぼ等しくなる。
【０１３７】
以降、１回目の第１種の電位差印加ステップＴ１１中は画素トランジスタオンによる画素電極の充電がないので画素電極電位は変化しない。このように第１種の電位差印加ステップでは画素電極と対向電極間の電位差は、第２種の電位差印加ステップの対向電極電位と第１種の電位差印加ステップの対向電極電位の電位差とほぼ等しい。そこで、第１種の電位差印加ステップの対向電極電位と第２種の電位差印加ステップの対向電極電位の電位差が液晶層のベンド配向への転移に必要な電位差になるよう各期間の対向電極電位を設定する。
【０１３８】
２回目の第２種の電位差印加ステップＴ22が開始すると、対向電極電位が変化するため画素電極電位はその影響で期間Ｔ１１と期間Ｔ22の境部の対向電極電位変動に示すように対向電極電位が変化した方向に電位が変化する。その後の画素トランジスタオンによる画素電極充電動作でその電位は１回目の第２種の電位差印加ステップでの画素電極電位となり、対向電極電位との電位差はほぼゼロの第２種の電位差になる。
【０１３９】
２回目の第２種の電位差印加ステップＴ２２から２回目の第１種の電位差印加ステップＴ２１に移行すると、対向電極電位は１回目の第１種の電位差印加ステップと同様に変化するが、この期間中も初期の画素トランジスタオンにより、１回目の第１種の電位差印加ステップと同様の第１種の電位差が画素電極・対向電極間には与えられる。
【０１４０】
以降、液晶層のベンド配向への転移が完了するまで繰り返し制御ステップで第２種の電位差印加ステップと第１種の電位差印加ステップを交互に繰り返し、第２種の電位差印加ステップでは画素電極・対向電極間の電位差はほとんどゼロの第２種の電位差になり、第１種の電位差印加ステップでは画素電極・対向電極間の電位差は液晶層が転移するために必要な十分に大きな第１種の電位差が与えられる。
【０１４１】
画素電極へのソース線電位の充電を各期間の初期に１回しか行わないことにより、第７の実施の形態よりも画素トランジスタオン・オフタイミングの制御はより煩雑になるが、第２種の電位差印加ステップ中に画素トランジスタがオンになり画素電極と対向電極の電位差がゼロでなくなる時間を減らしつつ、画素電極電位を各期間の初期に確定して対向電極電位の変動の影響を排除し、第５の実施の形態・第７の実施の形態よりもパネル全面でのベンド配向への転移を高速化している。
【０１４２】
第７の実施の形態と同様に、画素電極の充電が１回の画素トランジスタのオンでは不十分な場合や、液晶層をベンド配向に転移させるための駆動期間が通常の映像表示期間に対して非同期に開始し画素トランジスタを確実にオンにするために回数のマージンが必要な場合には、各期間の初めの画素トランジスタオンによる画素電極充電は１回ではなく数回行っても効果にあまり影響しない。
【０１４３】
（第１−９の実施の形態）
図３３と図２４を用いて第５の実施の形態の液晶層をベンド配向させるための駆動期間中、ゲート線のオフ電圧を直流にする場合の第９の実施の形態の動作を説明する。
【０１４４】
図３３に、図２４で示す画素の電極電位のタイムチャートを示す。
【０１４５】
本図において、液晶層をベンド配向させるための駆動期間の電気的動作タイミングは第５の実施の形態と同様である。図２４の構造の液晶パネルでは、前段のゲート線８１と透明画素電極２１との間に蓄積容量Ｃｓｔを形成し、通常映像表示期間には画素の隣り合う行の間に電位差を与えるために、前段のゲート線の電位と対向電極の電位をおなじ方向に変化させている。この動作はゲート線が画素トランジスタをオフにする電位すなわちオフ電圧を選択している間中行われる。
【０１４６】
液晶層をベンド配向させるための駆動期間中もこの動作が継続すると、前段のゲート線のオフ電圧の変動で式（６）のΔＶｐ６だけ画素電極電位が変動し、特に第２種の電位差印加ステップで画素電極・対向電極間の電位差をほぼゼロの第２種の電位差にしたいにもかかわらず、数ボルトの電位差が生じる。第２種の電位差印加ステップでの画素電極・対向電極間の電位差は図２９に示すように１ボルトを超えると、転移完了時間が長くなる。
【０１４７】
そこで、図３３のように液晶層をベンド配向させるための駆動期間中、ゲート線オフ電圧直流保持ステップでゲート線のオフ電圧を直流にすることにより、第２種の電位差印加ステップでの画素電極の電位変動を回避でき、パネル全面でのベンド配向への転移を高速化できる。
【０１４８】
（第１−１０の実施の形態）
図３４、図１３を用いて第１０の実施の形態における動作を説明する。
【０１４９】
図３４に、図１３で示す画素の電極電位のタイムチャートを示す。
【０１５０】
本図において、太い点線は対向電極電位を、細い点線はゲート線電位を、細い実線はソース線電位を、太い実線は画素電極電位を示す。下部のＶｐｃは、画素電極・対向電極間電位差であり、Ｖｓｃはソース線・対向電極間電位差である。Ｔｃは通常映像表示期間、Ｔ１２は１回目の第２種の電位差印加ステップ、Ｔ１１は１回目の第１種の電位差印加ステップ、Ｔ２２は２回目の第２種の電位差印加ステップ、Ｔ２１は２回目の第１種の電位差印加ステップである。また、各種の画素電極電位の変動要因を示す。
【０１５１】
図３４において、液晶層をベンド配向させるための駆動期間の１回目の第２種の電位差印加ステップＴ１２が開始すると、対向電極電位を通常映像表示期間とは異なる第２の電位とする。画素電極電位４は液晶容量Ｃｌｃを介して対向電極と接続し、この瞬間には画素トランジスタがオフで電流供給がないため、対向電極電位変動分ΔＶｃｏｍに対して式（５）のΔＶｐ５だけＴ１２の左端の対向電極電位変動に示すように対向電極電位の変化した方向に電位が変化する。ソース線電位を、対向電極電位にΔＶｐ６を上乗せした電位とし、充電小ステップで画素トランジスタを一度オン・オフすると、画素電極電位は期間Ｔ１２中央のゲート電極電位変動に示すように、ΔＶｐ６だけ下がり、対向電極電位とほぼ等しくなる。
【０１５２】
１回目の第２種の電位差印加ステップＴ12から１回目の第１種の電位差印加ステップＴ11に移行すると、画素電極・対向電極間の電位差を第１種の電位差にするため、対向電極電位を第１の電位に変化させ、画素電極電位はその影響を受けて期間Ｔ11と期間Ｔ12の境部の対向電極電位変動に示すように対向電極電位の変化した方向にΔＶｐ５だけ変化する。ソース線電位を１回目の第２種の電位差印加ステップＴ12同様、対向電極電位（第２の電位）にΔＶｐ６を上乗せした電位として充電小ステップで画素トランジスタを一度オン・オフすると、画素電極電位は期間Ｔ11のゲート電極電位変動と同様に、ゲート線電位の電位変動の影響で下がる。
【０１５３】
第１種の電位差印加ステップでは画素電極と対向電極の間の電位差が大きいほど液晶層のベンド配向への転移を高速化できるため、第２種の電位差印加ステップから第１種の電位差印加ステップへの対向電極電位の変動とは逆方向にソース線電位を変動させる。対向電極電位は、画素電極電位との電位差が液晶層のベンド配向への転移に必要な第１種の電位差になるように設定する。
【０１５４】
２回目の第２種の電位差印加ステップＴ２２が開始すると、対向電極電位が変化するため画素電極電位はその影響で期間Ｔ１２と期間Ｔ２２の境界部の対向電極電位変動に示すように対向電極電位の変化した方向に電位が変化する。その後の画素トランジスタオンによる画素電極充電動作でその電位は１回目の第２種の電位差印加ステップでの画素電極電位となり、対向電極電位との電位差はほぼゼロの第２種の電位差になる。
【０１５５】
２回目の第２種の電位差印加ステップＴ２２から２回目の第１種の電位差印加ステップＴ２１に移行すると、対向電極電位は１回目の第１種の電位差印加ステップと同様に変化するが、この期間中も画素トランジスタオンによる画素電極充電により、１回目の第１種の電位差印加ステップと同様の第１種の電位差が画素電極・対向電極間には与えられる。
【０１５６】
以降、液晶層のベンド配向への転移が完了するまで繰り返し制御ステップで第２種の電位差印加ステップと第１種の電位差印加ステップを交互に繰り返し、第２種の電位差印加ステップでは期間開始後１回目の画素トランジスタオンまでの間および充電小ステップで画素トランジスタがオンして画素電極を充電している時以外は画素電極・対向電極間の電位差はほとんどゼロの第２種の電位差になり、第１種の電位差印加ステップでは期間開始後１回目の画素トランジスタオンまでの間以外は画素電極・対向電極間は液晶層がベンド配向へ転移するために必要な十分に大きな第１種の電位差が与えられる。
【０１５７】
第２種の電位差印加ステップと第１種の電位差印加ステップとでソース線電位を変動することにより、第１種の電位差印加ステップには画素電極・対向電極間の第１種の電位差をより大きくすることができるため、液晶層のベンド配向への転移を高速化できる。
【０１５８】
図３５に、第５の実施の形態および第６の実施の形態で液晶層をベンド配向させるための駆動期間を第１種の電位差印加ステップから開始した場合と、第２種の電位差印加ステップから開始した場合での転移が完了するまでの所要時間の測定結果を示す。
【０１５９】
横軸に第１種の電位差印加ステップでの画素電極・対向電極間の第１種の電位差を示し、この電位差が大きければ転移完了時間は短くなっているが、いずれの電位差においても第２種の電位差印加ステップから開始した場合の方がより早くベンド配向への転移が完了する。
【０１６０】
（第１−１１の実施の形態）
図３６と図１３を用いて第１１の実施の形態における動作を説明する。
【０１６１】
図３６において、太い点線は対向電極電位を、細い点線はゲート線電位を、細い実線はソース線電位を、太い点線は画素電極電位と示す。Ｖｐｃは、画素電極・対向電極間電位差である。３つのＴｃは通常映像表示期間、Ｔ１２は１回目の第２種の電位差印加ステップ、Ｔ１１は１回目の第１種の電位差印加ステップ、Ｔ２２は２回目の第２種の電位差印加ステップ、Ｔ２１は２回目の第１種の電位差印加ステップである。また、各種の画素電極電位の変動要因を示す。
【０１６２】
本図において、液晶層をベンド配向させるための駆動期間の１回目の第２種の電位差印加ステップＴ１２が開始すると、対向電極電位を通常映像表示期間とは異なる第２の電位とする。画素電極電位は、液晶容量Ｃｌｃを介して対向電極と接続し、この瞬間には画素トランジスタがオフで電流の供給がないため、対向電極電位変動分ΔＶｃｏｍに対してΔＶｐ５だけ本Ｔ１２の左端に示すように対向電極電位が変化した方向に電位が変化する。
【０１６３】
ソース線電位を、対向電極電位にΔＶｐ６を上乗せした電位とし、充電小ステップで画素トランジスタを一度オン・オフすると、画素電極電位は本Ｔ１２の中央に示すようにΔＶｐ６だけ下がり、対向電極電位とほぼ等しくなる。以降、１回目の第２種の電位差印加ステップ中は、充電小ステップで画素トランジスタがオンになり画素電極にソース線電位を充電している時以外は画素電極電位と対向電極電位との電位差はほぼゼロの第２種の電位差になる。
【０１６４】
１回目の第２種の電位差印加ステップＴ12から１回目の第１種の電位差印加ステップＴ11に移行すると、画素電極電位と対向電極電位との電位差を第１種の電位差にするために対向電極電位を第１の電位に変化させ、画素電極電位はその影響を受けて対向電極電位が変化した方向にΔＶｐ５だけ変化する。ソース線電位を１回目の第２種の電位差印加ステップＴ12同様、対向電極電位（第２の電位）にΔＶｐ６を上乗せした電位として充電小ステップで画素トランジスタを一度オン・オフすると、画素電極電位はゲート線電位の電位変動の影響で第２種の電位差印加ステップの対向電極電位（第２の電位）とほぼ等しい電位までは下がるが、第１種の電位差印加ステップでは画素電極電位と対向電極電位の間の電位差が液晶層がベンド配向に転移するのに必要な十分に大きい第１種の電位差になるように対向電極電位を設定する。以降、１回目の第１種の電位差印加ステップＴ11中は、画素電極電位と対向電極電位の間の電位差は、液晶層のベンド配向への転移に必要な第１種の電位差が与えられている。
【０１６５】
２回目の第２種の電位差印加ステップＴ２２が開始すると、対向電極電位が変化するため画素電極電位はその影響でＴ２２の最初の対向電極電位変動に示すように対向電極電位が変化した方向に電位が変化するが、画素トランジスタを一度オン・オフすると、１回目の第２種の電位差印加ステップＴ１２と同様に、画素トランジスタがオンになり画素電極にソース線電位を充電している時以外は画素電極・対向電極間の電位差はほぼゼロの第２種の電位差になる。
【０１６６】
２回目の第２種の電位差印加ステップＴ２２から２回目の第１種の電位差印加ステップＴ２１に移行すると、対向電極電位は１回目の第１種の電位差印加ステップと同様に変化するが、画素トランジスタがオンになり画素電極にソース線電位を充電している時も画素トランジスタがオフしている時も画素電極電位と対向電極電位の間の電位差は、液晶層のベンド配向への転移に必要な第１種の電位差が与えられている。
【０１６７】
以降、液晶層の転移がほぼ完了するまで繰り返し制御ステップで第２種の電位差印加ステップと第１種の電位差印加ステップを交互に繰り返し、第２種の電位差印加ステップでは期間開始後１回目の画素トランジスタがオンするまでの間および画素トランジスタがオンしている時以外は画素電極・対向電極間の電位差はほとんどゼロの第２種の電位差になり、第１種の電位差印加ステップでは期間開始後１回目の画素トランジスタがオンするまでの間以外は画素電極・対向電極間は液晶層がベンド配向へ転移するために必要な十分に大きな第１種の電位差が与えられている。
【０１６８】
液晶層のベンド配向への転移がほぼ完了した時点で通常映像表示期間Ｔｃに移行する前に、移行用高電位差印加ステップで画素電極・対向電極間の電位差が大きい映像情報（通常は黒か白の表示）を１フィールド表示すると、液晶層のベンド配向領域の拡大が完了し、以降、本来の入力映像情報を表示するその次の通常映像表示期間Ｔｃに移行する。
【０１６９】
通常、第１種の電位差印加ステップ、第２種の電位差印加ステップは数フィールド以上、時間にして数百ミリ秒以上になることが多く、液晶層のベンド配向への転移を完了するために第１種の電位差印加ステップもしくは第２種の電位差印加ステップを１回追加すると、転移完了時間は数百ミリ秒単位で増加する。新たなベンド核の発生は不要でベンド領域の拡大のみで転移が完了する場合には、画素電極・対向電極間の電位差が大きい映像情報を表示することで数十ミリ秒の時間追加で良くなり、転移完了時間を短縮することができる。
【０１７０】
｛参考例２｝
本参考例２は、電源投入時の各部の立上げの制御に関する。
【０１７１】
以下、その実施の形態に基づいて本参考例２を説明する。
【０１７２】
以下、本参考例２を、図３７と図３８を参照しつつ説明する。なお、本参考例２は、実施の形態は１つである。
【０１７３】
図３７において、Ｖｇは、ゲート線電位である。Ｖｓは、ソース線の電位である。Ｖｐは、画素電極の電位である。Ｖｐｃは、画素電極と対向電極間の電位差である。また、Ｔｏは、電源オフ期間であり、Ｔ１２は１回目の第２種の電位差印加ステップである。Ｔ１１は１回目の第１種の電位差印加ステップであり、Ｔｃは、通常の映像の表示期間である。また、各種の画素電極電位の変動要因を示す。
【０１７４】
図３８において、３８０１は主電源、３８０２は電源回路コントローラ、３８０３は各種電源電圧発生回路、３８０４は液晶パネルコントローラ、３８０５は液晶パネルである。主電源３８０１と液晶パネルコントローラ３８０４には外部より起動スイッチ３８１０が接続されている。この起動スイッチ３８１０は液晶パネルコントローラ３８０４の内部のカウンタ３８１１とそれに続く３８１２の切換手段Ａが接続され、起動後、液晶パネルコントローラ３８０４に電源が供給された後は、このカウンタにより、所定の期間をカウントした後、通常映像信号発生部３８１３からの映像信号を液晶パネル３８０５へ印加する。所定の期間をカウント中は、３８１４の電圧発生手段１と３８１５の電圧発生手段２を周期カウンタ３８１６で設定された所定の周期で、３８１７の切換手段Ｂにより切換える。
【０１７５】
図３８の回路で、電源オフ期間Ｔｏは液晶パネルに入力するすべての信号は不定である。起動スイッチ３８１０を投入して電源をオンにすると、まず３８０２の電源回路コントローラにのみ電源が供給され、３８０２のコントローラが各種電源電圧発生回路を順次制御して液晶パネルコントローラの動作が開始する。このような液晶層安定保持立ち上げ制御ステップを有する回路構成にすることにより、液晶パネルに入力する信号を電源投入後、直ちに第２種の電位差印加ステップの電圧設定にすることが可能になり、電圧無印加状態での液晶層の整列状態を壊すことなく液晶層のベンド配向への転移期間を開始することができ、電源投入後の転移完了時間を短くすることができる。
【０１７６】
電圧無印加状態での液晶層はスプレイ配向状態で基板のラビング溝に沿って整列しているが、何等かの電位差印加があると、ベンド配向に転移しやすい液晶素子から順に転移が開始する。液晶パネル面内でスプレイ配向のままの液晶素子と、ベンド配向に移転しかけている液晶素子が無秩序に混在すると、それらの液晶素子に同時に大きい電位差を印加しても潤滑なベンド配向への転移が行なわれない場合がある。本実施の形態では、液晶装置の電源投入直後に無作為な電位差印加によりベンド配向への転移を始める液晶素子の発生を抑えて、全面がスプレイ配向状態の液晶素子に対してベンド配向への転移のための駆動を開始することを目的としている。
【０１７７】
表１に本実施の形態の駆動方式による実験結果の一例を示す。
【０１７８】
【表１】

本実施の形態の駆動方式とは、電源投入後、液晶パネルに入力する対向電極電位、ゲート線電位、ソース線電位が全て、第２種の電位差印加ステップで出力されるべき電圧を出力するものである。一方、第２種の電位差印加ステップ前に通常の映像の表示期間がある従来の方式では、電源投入後各種電源電圧発生回路が無制御のまま立ちあがり、第２種の電位差印加ステップの前に通常映像表示期間と同様の電圧が対向電極電位、ゲート線電位、ソース線電位に出力される。これら２方式で第２種の電位差印加ステップの所要時間を変えて転移完了状態を観測すると、本実施の形態の駆動方式のほうが短時間で転移が完了することがわかった。
【０１７９】
なお、第２の発明群と本発明群の実施の形態では、第１種の電位差印加ステップと第２種の電位差印加ステップとでソース線電位は同様に変化する必要はなく、各期間において異なるタイミング、異なる電位で変化しても何ら差し支えない。
【０１８０】
以上、本発明をその幾つかの実施の形態に基づいて説明してきたが、本発明は何もこれらに限定されないのは勿論である。すなわち例えば以下の様にしていても良い。
【０１８２】
１）液晶表示装置は、反射型、いわゆるＲＯＣＢと言われる型のものである。
【０１８３】
２）液晶装置は、光スイッチや光論理素子等である。
【０１８４】
【発明の効果】
以上の説明で判るように、本発明によれば、
液晶パネルの中でも広い面積を占める画素電極と対向電極の間に通常映像表示時よりも高い第１種の電位差を付与することにより、液晶層のベンド配向への核の生成およびベンド領域の拡大を行い、パネル全面で液晶層を短時間にベンド配向に転移することができ、高速応答で広視野角な液晶パネルを提供することができる。
【０１８５】
また、液晶パネルの画素電極と対向電極の間に通常映像表示時よりも
高い第１種の電位差を付与する第１種の電位差印加ステップと、第１種の電位差よりも小さい第２種の電位差を付与する第２種の電位差印加ステップを交互に設けることにより、液晶層のベンド配向への核の生成およびベンド領域の拡大と、液晶層の再整列を交互に行い、結果的にパネル全面で液晶層を短時間にベンド配向に転移することができ、高速応答で広視野角な液晶パネルを提供することができる。
【０１８６】
また、画素電極との間に蓄積容量を形成している共通電極の電位を変更することで、画素電極電位をソース線から与えた電位よりも更に対向電極との電位差が大きくなるように変動させ、液晶層に高い電位差を付与することで、パネル全面で液晶層をより短時間にベンド配向に転移することができ、高速応答で広視野角な液晶パネルを提供することができる。
【０１８７】
また、画素電極との間に蓄積容量を形成している前段のゲート線の電位を変更することで、画素電極電位をソース線から与えた電位よりも更に対向電極との電位差が大きくなるように変動させ、液晶層に高い電位差を付与することで、パネル全面で液晶層をより短時間にベンド配向に転移することができ、高速応答で広視野角な液晶パネルを提供することができる。
【０１８８】
また、ソース線電位に、画素トランジスタがオフする時に画素電極に生じる電位変動分を考慮することで、ゲート線のオン・オフタイミングを通常の映像表示時と変更することなく、画素電極と対向電極間に液晶層のベンド配向への転移に有効な第１種の電位差と第２種の電位差を付与することができ、パネル全面でのベンド配向への転移を高速にすることができる。
【０１８９】
また、同じくゲート線のオン・オフタイミングを通常の映像表示時と同様にしながら、画素トランジスタがオフしているときには更にソース線の電位を変動させて、ソース線と対向電極間にも液晶層のベンド配向への転移に有効な第２種の電位差を付与することにより、パネル全面でのベンド配向への転移をより高速化することができる。
【０１９０】
また、画素トランジスタのオンによる画素電極充電を液晶層をベンド配向に転移させる駆動期間の初期に少なくとも１回行うことにより、画素トランジスタのオン・オフタイミングを通常映像表示期間とは変えるという煩雑さはあるが、第２種の電位差印加ステップ中の画素電極充電回数が通常タイミングよりも少ないため、画素電極と対向電極間の電位差がゼロの時間が第２種の電位差印加ステップ中に多くなり、パネル全面でのベンド配向への転移をより高速にすることができる。
【０１９１】
また、画素トランジスタのオンによる画素電極充電を液晶層をベンド配向させるための第１種の電位差印加ステップ、第２種の電位差印加ステップそれぞれの初期に少なくとも１回行うことにより、画素トランジスタのオン・オフタイミングの制御はより煩雑になるが、各期間の初期に画素電極電位を確定することで対向電極電位の変動の影響を全く排除して第１種の電位差および第２種の電位差を付与することができ、パネル全面でのベンド配向への転移をより高速化することができる。
【０１９２】
また、液晶層のベンド配向への転移の駆動期間中、ゲート線のオフ電圧を直流にすることにより、特に第２種の電位差印加ステップで画素電極がゲート線電位変動から受ける影響を排除することができ、パネル全面でのベンド配向への転移を高速にすることができる。
【０１９３】
また、第１種の電位差印加ステップと第２種の電位差印加ステップとでソース線の電位を変動させ、第１種の電位差印加ステップでの画素電極と対向電極間の電位差をより大きくすることで、パネル全面でのベンド配向への転移を高速にすることができる。
【０１９４】
また、液晶層をベンド配向させるための駆動期間を終了し、通常映像表示期間に移行する前に、画素電極・対向電極間の電位差が大きい映像情報を１フィールド表示することにより、ベンド配向させるための第１種の電位差印加ステップあるいは第２種の電位差印加ステップを追加して転移完了のための時間を数百ミリ秒も増やすことなく、１フィールドすなわち十数ミリ秒の時間の追加でベンド配向への転移を完了することができ、パネル全面での転移完了時間を短縮することができる。
【０１９５】
また、電源投入時の液晶層の状態を電源未投入時の状態から過度に乱すことなく第２種の電位差印加ステップを開始することにより、液晶層の整列をより短時間で行い、パネル全面での液晶層のベンド配向への転移を高速にすることができる。
【図面の簡単な説明】
【図１】液晶素子のスプレイ配向（１）、（２）とベンド配向（３）の様子を示す図である。
【図２】従来の液晶パネルの１画素分の要部の構造の平面と断面を示す図である。
【図３】従来の液晶パネル及び幾つかの実施の形態におけるゲート線電極、対向電極間の容量性負荷を模式的に示した図である。
【図４】第１−１の実施の形態の液晶パネルの１画素分の構成を示した図である。
【図５】第１−２の実施の形態の液晶パネルの１画素分の構成を示した図である。
【図６】第１−３の実施の形態の液晶パネルの１画素分の構成を示した図である。
【図７】第１−４の実施の形態の液晶パネルの１画素分の構成を示した図である。
【図８】第１−５の実施の形態の液晶パネルの１画素分の構成を示した図である。
【図９】第１−６の実施の形態の液晶パネルの１画素分の構成を示した図である。
【図１０】第１−７の実施の形態の液晶装置の断面図である。
【図１１】第１−８の実施の形態の液晶装置の断面図である。
【図１２】第１−９の実施の形態の液晶装置の断面図である。
【図１３】第２−１の実施の形態等の液晶装置の画素の回路構成を示した図である。
【図１４】同じく画素の構造を示した図である。
【図１５】同じく画素の寸法を示した図である。
【図１６】同じく画素間の各部に印加されたり付加されたりする電圧の様子、作用を示した図である。
【図１７】第２−２の実施の形態の電圧印加の様子、作用を示した図である。
【図１８】上記実施の形態の液晶装置の制御手段の構成図である。
【図１９】第２−２の実施の形態における第１種の電位差印加ステップのデューティ比と転移完了時間の相関を示す図である。
【図２０】同じく、画素電極と対向電極間の電位差Ｖｐｃの変化に要する時間ｔｒ、ｔｆを示す図である。
【図２１】同じく、回路の具体的構成を示す図である。
【図２２】第２−３の実施の形態の電圧印加の様子、作用を示した図である。
【図２３】上記実施の形態の変形例を示した図である。
【図２４】第２−４の実施の形態の画素の回路構成を示した図である。
【図２５】上記実施の形態の画素の構造を示した図である。
【図２６】上記実施の形態の画素の寸法を示した図である。
【図２７】第２−４の実施の形態の作用を示した図である。
【図２８】第２−５の実施の形態の画素の電極電位のタイムチャートである。
【図２９】画素電極と対向電極間電位差が変化した場合の電位差と転移完了時間の関係の測定結果を示した図である。
【図３０】第２−６の実施の形態の画素の電極電位のタイムチャートである。
【図３１】第２−７の実施の形態の画素の電極電位のタイムチャートである。
【図３２】第２−８の実施の形態の画素の電極電位のタイムチャートである。
【図３３】第２−９の実施の形態の画素の電極電位のタイムチャートである。
【図３４】第２−１０の実施の形態の画素の電極電位のタイムチャートである。
【図３５】第２−５の実施の形態から第２−１１の実施の形態で液晶層をベンド配向させるための駆動期間を第１種の電位差印加ステップから開始した場合と第２種の電位差印加ステップから開始した場合の転移完了時間測定値を示す図である。
【図３６】第２−１１の実施の形態の画素の電極電位のタイムチャートである。
【図３７】第３−１の実施の形態のタイムチャートである。
【図３８】上記実施の形態等の回路の構成を示した図である。
【符号の説明】
１第１の基板
２第２の基板
３画素電極
２１透明画素電極
５液晶層
６画素トランジスタ
７ソース線、ソース線電極
７０ソース線形成金属膜
７１ソース線
８ゲート線、ゲート線電極
８１前のゲート線
９対向電極
１０共通電極
１１ブラックマトリクス
１２カラーフィルター
６４チャネル保護膜
６５ａ−Ｓｉ層
６６ｎ＋ａ−Ｓｉ層
７６ソース線電極と液晶層間の絶縁膜
８６ゲート線電極とａ−Ｓｉ層間の絶縁膜
８７絶縁膜
Ｖｃｃ共通電極の電位
Ｖｃ対向電極の電位
Ｖｇゲート線の電位
Ｖｓソース線の電位
Ｖｐ画素電極の電位
Ｖｐｃ画素電極と対向電極間の電位差
Ｔｃ通常の映像の表示期間
Ｃｇｄゲート線と画素電極間容量
Ｃｓｔ画素電極と共通電極間の蓄積容量
Ｃｌｃ画素電極と対向電極間の液晶容量
Ｃｇｓゲート線とソース線間容量
２０４液晶パネルコントローラ
２０５液晶パネル[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal device, and more particularly to a startup technique for driving a liquid crystal device in which a liquid crystal layer is in a splay alignment when no voltage is applied but is in a bend alignment when a function such as display is performed.
[0002]
[Prior art]
In a liquid crystal device, the electrical operation of a liquid crystal element is such that each pixel is a holding type that maintains light if bright and dark if dark during one display cycle. One of the features was that it became a still image with little flicker.
[0003]
However, in recent years, moving images can be easily processed in personal computers by increasing the speed and capacity of CPUs and memories. For this reason, it is desired to improve the image quality when displaying a moving image on a liquid crystal display device.
[0004]
Also, televisions as broadcast receivers have been increasing in screen size, but cathode-ray tubes have a larger screen and inevitably have a greater depth to some extent, which is not desirable for the demand for thin-screen televisions. It is considered that a liquid crystal display device is adopted as one means for that.
[0005]
Currently, the TN alignment liquid crystal device, which is the mainstream of the liquid crystal device, has a slow response speed, and in a cathode ray tube, each pixel emits light for a short period of time within each display period, whereas the liquid crystal element is If it is ON (open, light emission), the image is inferior to a cathode ray tube, for example, it is a holding type that keeps emitting light during the display period within one display period, and looks like a trailing edge when displaying a moving image.
[0006]
As a countermeasure, for example, if a liquid crystal having a bend orientation called OCB type (type) disclosed in Japanese Patent Application Laid-Open No. 61-116329 or Japanese Patent Application Laid-Open No. It is possible to provide a large-screen display that can sufficiently cope with a screen and is thinner and consumes less power than a CRT.
[0007]
In addition, devices using liquid crystal are not limited to display units such as word processors, personal computers, and television receivers. ,light Although they are being used in circuits and devices using logic elements, OCB-type liquid crystals are also receiving attention in such applications from the viewpoint of good display performance and high-speed operation.
[0008]
[Problems to be solved by the invention]
However, in such a liquid crystal, a high potential difference needs to be continuously applied to the liquid crystal layer for a certain period of time or more in order to make a transition from the splay alignment 51 shown in (1) or (2) of FIG. 1 to the bend alignment shown in (3). However, applying such a voltage imposes a burden on the transistor element and the wiring, resulting in high cost. That is, a technique for easily and surely performing such transition by using a voltage, a current, or the like that can be used in an element, a wiring, or the like that is widely used at present has not yet been realized. As a result, this type of liquid crystal has not been used for general purposes at present.
[0009]
Therefore, in such an OCB type liquid crystal device or its driving circuit, the liquid crystal layer can be surely transferred to the bend alignment in a short time without burdening the current hardware such as transistor elements and wirings, and at a low cost. Technology development was desired.
[0010]
Similarly, development of a reliable and easy start-up technique has been desired for use in other applications described above.
[0011]
[Means for Solving the Problems]
The present invention has been made for the purpose of solving the above problems, and has devised the structure of each element of a device using a liquid crystal. Similarly, a voltage as high as possible for the start-up is applied, and the timing at which the voltage is applied is devised. Specifically, the following is performed.
[0012]
Reference Example 1 In the invention of the present invention, the structure of an OCB type liquid crystal display device or the like is devised, and as a result, a liquid crystal layer existing between the gate line of the first substrate and the counter electrode of the second substrate is used for startup. And normal video display Time When a higher electric field strength is applied and the portion is bent, the portion becomes a nucleus and grows, thereby shifting the entire liquid crystal layer to the bend alignment. At this time, since a gate line which is driven at a higher voltage than other parts in the liquid crystal panel is used, it is possible to apply a high electric field strength to the liquid crystal layer without burdening the source line driving IC and the pixel transistor. it can.
[0013]
In order to give a higher electric field strength to the liquid crystal layer, the thickness of the insulating film on the gate line is reduced to increase the capacitance of the insulating film, and the voltage division ratio between the gate line and the counter electrode is changed.
[0014]
Similarly, the insulating film capacity is increased by using a material having a high relative dielectric constant for the insulating film on the gate line, and the voltage division ratio of the voltage between the liquid crystal layer and the insulating film between the gate line and the counter electrode is changed.
[0015]
Similarly, the thickness of the liquid crystal layer on the gate line is reduced by about 0.5 to 1.5 μm by increasing the thickness of the metal forming the gate line in a portion where there is no other metal film or semiconductor layer between the liquid crystal layer and the liquid crystal layer. are doing.
[0016]
Similarly, the source line forming metal is electrically contacted and laminated on the gate line where there is no other metal film or semiconductor layer between the liquid crystal layer and the thickness of the gate line is increased, and the liquid crystal layer on the gate line is increased. Has been reduced in thickness.
[0017]
Similarly, a source line forming metal is laminated on a portion of the gate line where there is no other metal film or semiconductor layer between the liquid crystal layer and the metal line or the semiconductor layer without electrically contacting the portion to reduce the thickness of the liquid crystal layer on the gate line. .
[0018]
Similarly, the opposing electrode on the second substrate is divided into a portion facing the gate line of the first substrate and the other portion, and a higher voltage is applied to the opposing electrode facing the gate line than the other portion. Multiply.
[0019]
Similarly, the thickness of the liquid crystal layer over the gate line is reduced by making the thickness of the counter electrode at the portion facing the gate line on the second substrate thicker than at other portions.
[0020]
Similarly, the color filter forming resin on the second substrate is laminated on the portion of the first substrate facing the gate line to reduce the thickness of the liquid crystal layer on the gate line.
[0021]
Similarly, a columnar spacer is provided on a portion of the second substrate facing the gate line of the first substrate, and an opposing substrate electrode is formed between the columnar spacer and the liquid crystal layer to form a liquid crystal layer on the gate line. Is thinner.
[0022]
No. 1 In the inventions of the invention, a circuit for starting up the liquid crystal device is devised so that a predetermined potential difference between the pixel electrode of the first substrate and the counter electrode of the second substrate is higher than that during normal image display. In accordance with the procedure and rules of the above.
[0023]
Thereby, the variation of the counter electrode can be used. The change to the bend alignment is promoted by changing the scan timing and the applied potential difference and controlling the change.
[0024]
Similarly, a period is provided between the pixel electrode of the first substrate and the counter electrode of the second substrate to continuously apply a first type of potential difference different from the normal image display period, and the liquid crystal is made as large as possible in area. By increasing the potential difference applied to the layer, the generation of transition nuclei to bend alignment is increased, the speed of bend region expansion is increased, and the transition to bend alignment is performed in a short time.
[0025]
Similarly, a first type potential difference applying step of applying a first type potential difference different from the normal video display period between the pixel electrode of the first substrate and the counter electrode of the second substrate; Is a driving method in which a second type of potential difference applying step of applying a second type of potential difference smaller than the potential difference is repeatedly and alternately performed at least once by a control step, and 50% to 95% of these periods A first type of potential difference applying step is performed in which the time is a first type of potential difference applying step and a bend alignment nucleus is generated and a bend region is expanded, and a bend alignment nucleus cannot be generated or the bend region is not expanded. By alternately applying the second type of potential difference applying step for rearranging the liquid crystal layer in the bent portion, the entire surface of the panel can be transferred to the bend alignment at high speed.
[0026]
Similarly, when the pixel transistor is turned on from off in the second type of potential difference applying step, a potential reflecting on the potential of the pixel electrode caused by the potential fluctuation of the gate line and reflected on the counter electrode potential is applied to the source line. It has a small charging step to charge the pixel electrode by changing the on / off timing of the gate line from the normal video display period, and fixes the potential of the pixel electrode to a desired potential to bend the entire panel. Transfer to the site can be accelerated.
[0027]
Similarly, when the pixel transistor is turned on from off in the second type of potential difference applying step, a potential reflecting on the potential of the pixel electrode caused by the potential fluctuation of the gate line and reflected on the counter electrode potential is applied to the source line. A first type of potential difference applying step, the source line potential is set to a different potential from the second type potential difference applying step so that the first type potential difference becomes larger. Thus, the generation of the bend alignment nucleus and the expansion of the bend region are accelerated, and the transition to the bend alignment over the entire panel is accelerated.
[0028]
Similarly, the driving period for bend alignment of the liquid crystal layer is started from the second type of potential difference applying step, and the first type of potential difference between the pixel electrode and the counter electrode is performed by aligning the liquid crystal layer first. In the first type of potential difference applying step, the generation of bend nuclei and the expansion of the bend region are accelerated, and the transition to the bend orientation over the entire panel is accelerated.
[0029]
Similarly, a first type of potential difference applying step of providing a first type of potential difference between the pixel electrode and the counter electrode in order to bend the liquid crystal layer, and the potential difference between the pixel electrode and the counter electrode is smaller than the first type potential difference. A driving method in which a second type of potential difference applying step for making a second type of potential difference is alternately performed at least once, and the first type of potential difference applying step or the second type of potential difference applying step is completed to perform a normal input video information display period. Before the transition to, the image information having a large potential difference applied to the liquid crystal layer is displayed in one or more fields, and the transition to the bend alignment of the liquid crystal layer is completed by enlarging the bend area, thereby changing the bend alignment over the entire panel. Speeds up the transition.
[0030]
Reference Example 2 Is to stabilize the liquid crystal layer when it is started. For this reason, efforts have been made to turn on the power.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described based on the embodiments.
[0032]
｛ Reference Example 1 ｝
Book Reference Example 1 Is a device in which a high voltage is applied for transferring the liquid crystal layer by mainly devising the structure of the insulating film of the pixel.
[0033]
Hereinafter, the present invention will be described based on its embodiments.
[0034]
(The 1-1 Reference example )
Here, "(1-1-1 Reference Example) ”means“ the first embodiment of Reference Example 1 ”. Also, in this specification, “(1-1st embodiment)” means “the first embodiment of the first invention group”. For this reason, Reference example In the second embodiment of the present invention, “(1-2. Reference example ) ".
[0035]
In practice, pixels having such a circuit configuration are formed on the substrate in vertical, horizontal, multiple rows, multiple rows, and even in multiple cases depending on the case, but this is obvious and complicated. , Illustration is omitted. This is the same in other invention groups and embodiments.
[0036]
FIG. 2 shows a plane (1) of a structure for one pixel of a conventional liquid crystal panel and a cross section (2) taken along the line AA of the transistor element portion. In the figure, reference numeral 21 denotes a transparent pixel electrode. 3 is a pixel electrode. 5 is a liquid crystal layer. 64 is a channel protective film. 65 is an a-Si (amorphous silicon) layer. 66 is an n + a-Si layer. 7 is a source line electrode. Reference numeral 76 denotes an insulating film between the source line electrode and the liquid crystal layer. 8 is a gate line electrode. Reference numeral 86 denotes an insulating film between the gate line electrode and the a-Si layer. 9 is a counter electrode.
[0037]
Figure 3 And figure 2 3 schematically shows a capacitive load between a gate line electrode and a counter electrode of a liquid crystal panel indicated by.
[0038]
In the figure, reference numeral 8 denotes a gate line electrode. 9 is a counter electrode. C1 is a capacitive load of the liquid crystal layer. C2 is a capacitive load of the insulating film between the source line electrode and the liquid crystal layer. C3 is a capacitive load of the insulating film between the gate line electrode and the a-Si layer.
[0039]
Figure 4 shows the book Reference example 1 shows a plane (1) of a structure of one pixel of the liquid crystal panel of FIG.
[0040]
In this figure, 8 is a gate line electrode, 7 is a source line electrode, 3 is a pixel electrode, 64 is a channel protective film, 65 is an a-Si layer, 66 is an n + a-Si layer, 86 is a gate line electrode and a-Si A first insulating film between the layers, 762 a second insulating film between the source line electrode and the liquid crystal layer, 5 a liquid crystal layer, 9 a counter electrode, 21 a transparent pixel electrode, 862 a gate line electrode and a-Si interlayer A second insulating film 761 is a first insulating film between the source line electrode and the a-Si layer.
[0041]
In the following, the book Reference example Will be described.
[0042]
In FIG. 2, when a voltage V is applied to the gate line electrode 8 and the counter electrode 9, the liquid crystal layer 5, the source line electrode 7, and the insulating film 7 between the liquid crystal layers are formed. 6 and A voltage determined by the ratio of the capacitive load value of each of the insulating film 86 between the gate line electrode and the a-Si layer is applied to each layer. The partial pressures are defined as V1, V2, and V3. These relationships will be described with reference to FIG.
[0043]
The capacitive load value C per unit area S is represented by the following (Equation 1-1), where ε is the relative dielectric constant of the layer, 1 is the thickness of the layer, and ε0 is the dielectric constant of vacuum.
C = ε0 × ε × S / l ... (1-1 formula)
On the other hand, the divided voltage V1 of the capacitive loads C1, C2, and C3 connected in series is expressed by the following equation (1-2).
V1 = V * C2 * C3 / (C1 * C2 + C2 * C3 + C3 * C1) (Equation 1-2).
[0044]
Liquid crystal layer 5, insulating film 7 6, Assuming that the relative permittivity and thickness of each of the 86 are ε1, ε2, ε311, l2, and l3, the partial pressure V1 of (Equation 1-2) is
V1 = V * ε2 * ε3 * 11 / (ε1 * ε2 * 13 + ε2 * ε3 * 11 + ε3 * ε1 * 12) (Equation 1-3)
And the electric field strength E1 is
E1 = V1 / 11
= V * ε2 * ε3 / (ε1 * ε2 * 13 + ε2 * ε3 * 11 + ε3 * ε1 * 12)
= V / (11 + 12 * ε1 / ε2 + 13 * ε1 / ε3) (Equation 1-4)
It becomes.
[0045]
In the structure of FIG. 4, the gate line electrode and the a-Si interlayer, the source line electrode and the source line electrode are patterned by making the insulating film between the gate line electrode and the a-Si layer, the source line electrode, and the liquid crystal layer into two layers. The insulation between the gate line electrode and the liquid crystal layer is made thinner while the insulation between the liquid crystal layers remains the same as before. With such a structure, the denominator of the electric field intensity E1 represented by the expression (1-4) is reduced, and as a result, the electric field intensity applied to the liquid crystal layer can be increased, and a high-speed transition to bend alignment can be achieved. Will be possible.
[0046]
The relative dielectric constant of the liquid crystal layer changes from about 3 to about 8 depending on the transmittance of the liquid crystal. The relative dielectric constants of SiOx, SiNx, and TaOx used as the insulating film are about 3.9, about 6.4, and about 23, respectively. If the variation of the relative permittivity of the liquid crystal is uniform, 4 In many cases, the electric field strength applied to the liquid crystal layer is higher than the electric field strength (formula 1-4) of the conventional structure. The liquid crystal layer having bend alignment is Spray orientation It is very effective to apply as high an electric field strength as possible to the liquid crystal layer in order to make the transition from the bend alignment to the bend alignment at a high speed. Therefore, thinning the insulating film as in this embodiment is a very effective means.
[0047]
(The 1-2th Reference example )
Figure 5 shows the book Reference example Of the 1-2 Reference example FIG.
[0048]
In the figure, 8 is a gate line electrode, 7 is a source line electrode, 3 is a pixel electrode, 64 is a channel protective film, 65 is an a-Si layer, 66 is an n + a-Si layer, 86 is a gate line electrode and a-Si An interlayer insulating film, 76 is an insulating film between the source line electrode and the liquid crystal layer, 5 is a liquid crystal layer, 9 is a counter electrode, 21 is a transparent pixel electrode, and A is a line showing a cross section.
[0049]
First first Reference example (Because there is no misunderstanding, Reference example Is abbreviated as follows. The same applies hereinafter. In (2), the insulating film has two layers, but the same effect can be obtained even if the thickness of the insulating film between the gate line electrode and the liquid crystal layer is reduced by patterning as shown in FIG.
[0050]
(1-3 Reference example )
FIG. Reference example FIG.
[0051]
Also in this figure, 8 is a gate line electrode, 7 is a source line electrode, 3 is a pixel electrode, 64 is a channel protective film, 65 is an a-Si layer, 66 is an n + a-Si layer, 86 is a gate line electrode and a- Reference numeral 76 denotes an insulating film between the Si layers, reference numeral 76 denotes an insulating film between the source line electrode and the liquid crystal layer, reference numeral 5 denotes a liquid crystal layer, reference numeral 9 denotes a counter electrode, reference numeral 21 denotes a transparent pixel electrode, and reference numeral A denotes a line showing a cross section.
[0052]
In this structure, the thickness of the gate line electrode is increased and the thickness of the liquid crystal layer on the gate line is reduced by increasing the thickness of the gate line electrode, thereby increasing the electric field strength applied to the liquid crystal layer and causing transition to bend alignment. Can be faster.
[0053]
The thickness of the gate line electrode is usually about 0.2 μm to 0.6 μm, but by doubling the thickness, the thickness of the liquid crystal layer can be reduced by about 0.5 μm.
[0054]
(No. 1-4 Reference example )
FIG. Reference example FIG.
[0055]
Also in this figure, 8 is a gate line electrode, 7 is a source line electrode, 3 is a pixel electrode, 64 is a channel protective film, 65 is an a-Si layer, 66 is an n + a-Si layer, 86 is a gate line electrode and a- An insulating film between the Si layers, 76 is an insulating film between the source line electrode and the liquid crystal layer, 5 is a liquid crystal layer, 9 is a counter electrode, 21 is a transparent pixel electrode, A is a line showing a cross section, and 70 is a gate line. A source line forming metal that is electrically contacted and laminated on the electrode.
[0056]
In this structure, a partially contacting gate line is formed by electrically contacting and laminating a source line forming metal on a gate line forming metal, so that the thickness of the gate line electrode is substantially increased. By reducing the thickness of the layer and increasing the electric field intensity applied to the liquid crystal layer, the transition to bend alignment can be performed at high speed.
[0057]
Since the thickness of the source line electrode is usually about 0.2 μm to 0.6 μm, the thickness of the liquid crystal layer can be reduced accordingly.
[0058]
(1-5th Reference example )
FIG. Reference example FIG.
[0059]
Also in this figure, 8 is a gate line electrode, 7 is a source line electrode, 3 is a pixel electrode, 64 is a channel protective film, 65 is an a-Si layer, 66 is an n + a-Si layer, 86 is a gate line electrode and a- An insulating film between the Si layers, 76 is an insulating film between the source line electrode and the liquid crystal layer, 5 is a liquid crystal layer, 9 is a counter electrode, 21 is a transparent pixel electrode, A is a line showing a cross section, and 713 is a gate line. It is a source line forming metal laminated on the electrode without making electrical contact.
[0060]
In this structure, the thickness of the liquid crystal layer on the gate line is reduced by using a non-contact type gate line in which a source line forming metal is electrically insulated and interposed between the gate line electrode and the counter electrode, so that the liquid crystal layer is covered. By increasing the electric field strength, the transition to the bend alignment can be performed at high speed.
[0061]
(1-6th Reference example )
FIG. Reference example FIG. In the figure, 1 is a first substrate, 8 is a gate line electrode, 7 is a source line electrode, 6 is a pixel transistor, 2 is a second substrate, and 91 is a position facing the gate line electrode of the first substrate. The first counter electrode 92 is a second counter electrode that is electrically insulated from the first counter electrode. In the structure of the split-type counter electrode, the first counter electrode and the second counter electrode are electrically insulated, so that a voltage change is caused by a pixel electrode or a pixel transistor via a capacitive load of a liquid crystal layer or an insulating film. The electric field strength can be given to the liquid crystal layer on the gate line electrode while preventing the influence on the liquid crystal layer, and the transition to the bend alignment can be performed at high speed. During normal image display, by setting the first and second counter electrodes to the same potential, it is possible to obtain the same image quality as that of a conventional liquid crystal display device in which the counter electrodes are not patterned.
[0062]
(No. 1-7 Reference example )
FIG. Reference example 1 shows a cross-sectional view of a liquid crystal display device. In this figure, 1 is a first substrate, 8 is a gate line electrode, 7 is a source line electrode, 87 is an insulating film, 2 is a second substrate, and 11 is a position facing the gate line electrode of the first substrate. Black matrix metal, 12 is a color filter, 5 is a liquid crystal layer, 91 is a first layer counter electrode formed almost uniformly on the entire surface of the second substrate, and 92 is formed at a position facing the gate line of the first substrate. This is the second layer counter electrode. In the structure of the opposed thick-film counter electrode, the thickness of the liquid crystal layer on the gate line can be reduced by increasing the number of counter electrodes facing the gate line to two, and the electric field strength can be increased. Can be done.
[0063]
(No. 1-8 Reference example )
FIG. Reference example 1 shows a cross-sectional view of a liquid crystal display device. Also in this drawing, 1 is a first substrate, 8 is a gate line electrode, 7 is a source line electrode, 87 is an insulating film, 2 is a second substrate, and 11 is a position facing the gate line electrode of the first substrate. Reference numeral 121 denotes a color filter of a first color such as red, 122 denotes a color filter of another second color such as blue, 9 denotes a counter electrode, and 5 denotes a liquid crystal layer.
[0064]
In this structure, the color filter forming resin is laminated on a portion of the second substrate facing the gate line electrode of the first substrate, thereby raising the counter electrode in this portion to reduce the thickness of the liquid crystal layer on the gate line. In addition, the electric field strength of the liquid crystal layer can be increased, and the transition to bend alignment can be made faster.
[0065]
(1-9th Reference example )
FIG. 12 shows the 1-9 Reference example 1 shows a cross-sectional view of a liquid crystal display device. Also in this drawing, 1 is a first substrate, 8 is a gate line electrode, 7 is a source line electrode, 87 is an insulating film, 2 is a second substrate, and 11 is a position facing the gate line electrode of the first substrate. Reference numeral 12 denotes a color filter, reference numeral 111 denotes a columnar spacer formed in a portion of the first substrate facing the gate line, reference numeral 9 denotes a counter electrode, and reference numeral 5 denotes a liquid crystal layer.
[0066]
In this structure, a columnar spacer is formed on a portion of the second substrate facing the gate line electrode of the first substrate, and a counter electrode is formed between the columnar spacer and the liquid crystal layer to form a liquid crystal layer on the gate line. The thickness can be reduced, the electric field strength of the liquid crystal layer can be increased, and the transition to bend alignment can be performed at high speed.
[0067]
Here, the structure of the liquid crystal panel has been described in the nine embodiments from the first embodiment to the ninth embodiment, but the thickness of the liquid crystal layer on the gate line is determined by combining a plurality of the embodiments. Is easier to obtain than when any of them is used alone, and the effect is further increased by dividing the counter electrode and applying an arbitrary voltage to the electrode facing the gate line.
[0068]
｛No. 1 Invention group
The group of the present invention applies a higher voltage between the pixel electrode and the counter electrode than at the time of displaying an ordinary image, or applies two types of voltages for the transition of the liquid crystal layer. And so on.
[0069]
(No. 1-1 Embodiment)
FIG. 13 illustrates a configuration centering on a pixel circuit of the liquid crystal device of this embodiment. In this figure, 3 is a pixel electrode. 6 is a pixel transistor. 7 is a source line. 71 is the next source line. 8 is a gate line. 81 is a previous gate line. 9 is a counter electrode. Reference numeral 10 denotes a common electrode connected to all storage capacitors. Cgd is the capacitance between the gate and the drain of the pixel transistor. Cst is a storage capacitor connected to the pixel electrode and formed between the pixel electrode and the common electrode. Clc is the capacity of the liquid crystal layer. Cgs is the capacitance between the gate and the source of the pixel transistor.
[0070]
FIG. 14 schematically illustrates a plane and a cross section centered on the structure of the pixel. In this figure, 6 is a pixel transistor, 21 is a transparent pixel electrode, Cst is a storage capacitor connected to the pixel electrode and formed with the common electrode, Clc is a capacitance of the liquid crystal layer, 7 is a source line, and 71 is the following. A source line, 8 is a gate line, 81 is a previous gate line, 9 is a counter electrode, and 10 is a common electrode connected to all storage capacitors.
[0071]
FIG. 15 shows an example of the dimension per pixel. In the figure, Wt is the width of a pixel. Lt is the length of the pixel. Wp is the width of the pixel electrode. Lp is the length of the pixel electrode. Ws is the width of the source line. Wg is the width of the gate line. Then, in an area of 30000 [μm 2] per pixel, the area of the pixel electrode is 18224 μm 2, which is 60.7% of one pixel.
[0072]
FIG. 16 shows the operation of the liquid crystal device of the present embodiment shown in FIGS.
[0073]
In FIG. 16, Vg is the voltage of the gate line. Vs is the voltage of the source line. Vp is the voltage of the pixel electrode. Vcc is the voltage of the common electrode. Vc is the voltage of the counter electrode.
[0074]
During normal image display, the voltage Vg of the gate line is changed until the pixel transistor is turned on, and the voltage Vs of the source line is charged to the pixel electrode 21, the storage capacitor Cst, and the liquid crystal capacitor Clc. The voltage Vp of the pixel electrode becomes equal to the voltage Vs of the source line.
[0075]
The voltage Vc of the counter electrode only needs to be in a range where the transmittance of the liquid crystal sufficiently changes between the voltage Vp of the pixel electrode and the potential difference Vpc between Vc and Vp is usually set to about 0 V to 5 V. In order to bend the liquid crystal layer, a different potential difference continuous application step of continuously applying a higher potential difference to the liquid crystal layer is required. The potential difference and time required for transition to bend alignment differ depending on the liquid crystal material, but it is experimental that some materials can complete transition within 1 second by applying a potential difference of 6 V or more between the pixel electrode and the counter electrode. Has been confirmed. For a liquid crystal display device, the shorter the transition time is, the better, and it is desirable that the transition time is within a few seconds to 10 seconds. For this purpose, a larger potential difference (about 20 V to 30 V) is given or a liquid crystal material is selected. . It is desirable to apply the potential difference for the liquid crystal layer to bend alignment to be as large as possible, and it is most effective to apply the potential difference between the pixel electrode and the counter electrode as shown in FIG.
[0076]
(No. 1-2 Embodiment)
The operation in the second embodiment will be described with reference to FIG. 17, FIG. 14, and FIG.
[0077]
In FIG. 17, Vg is the voltage of the gate line. Vs is the voltage of the source line. Vp is the voltage of the pixel electrode. Vcc is the voltage of the common electrode. Vc is the voltage of the counter electrode. The operation of the liquid crystal panel having such a configuration at the time of displaying a normal image is the same as in the first embodiment, and the potential difference Vpc between Vc and Vp is 0 V to 5 V. When a first-type potential difference of 6 V or more is continuously applied between the pixel electrode and the counter electrode in order to cause the transition to the bend alignment, depending on the structure of the liquid crystal panel or the liquid crystal material, the transition state does not progress and the portion where the transition state sticks. May occur and transfer may not be possible even if it takes only 10 seconds or more. In the case of such a panel or liquid crystal material condition, the voltage Vc of the counter electrode is brought close to the voltage Vp of the pixel electrode, and the potential difference Vpc applied to the liquid crystal layer is changed to a small second type of potential difference so that the orientation of the liquid crystal element is initialized. After returning, a high first type potential difference is applied again. As a result, the liquid crystal element that originally transitioned to the bend state easily transitions even if the potential difference is applied again after returning to the initial state, so that the liquid crystal element immediately transitions, and the portion where the transition state has been stuck has a new potential difference. The transition to the bend orientation is facilitated by re-applying, and consequently, the entire panel can be transitioned to the bend orientation in a short time.
[0078]
FIG. 18 shows an example of the configuration of the control means of the liquid crystal device according to the present invention. In the figure, reference numeral 205 denotes a liquid crystal panel, 204 denotes a liquid crystal panel controller, and 203 denotes various power supply voltage generation circuits. A start switch 210 is connected to the liquid crystal panel controller 204 from outside. The start switch 210 is connected to a counter 211 inside the liquid crystal panel controller 204 and a switching means A subsequent to the counter 211. Immediately after the start, the counter counts a predetermined period by this counter. A signal is applied to the liquid crystal panel 205. While the predetermined period is being counted, the voltage generating means 1 at 214 and the voltage generating means 2 at 215 are switched by the switching means B 217 at a predetermined cycle set by the cycle counter 216. These voltage generating means are not limited to generating a single voltage. Since the liquid crystal panel 205 is an active matrix and the liquid crystal applied effective potential difference between the pixel electrode and the counter electrode therein is the point, the source line voltage and the gate line which are factors that determine the pixel electrode voltage as well as the counter electrode voltage. Switching is performed by combining a required voltage among the voltage and a common electrode voltage of the storage capacitor described later.
[0079]
The predetermined period immediately after the start described here is a period of about 0.1 to 10 seconds, and the predetermined period set by the period counter 216 is about 0.1 to 5 seconds. Time.
[0080]
In the present embodiment, the time for making the potential difference Vpc between the pixel electrode and the counter electrode a second type of potential difference is a time for returning the transition to the bend orientation to the initial state, The transition to the bend alignment in the entire liquid crystal panel is completed in a shorter time if the time is shorter than or equal to the time for applying the first type of potential difference. As shown in FIG. 19, when the duty ratio of the first type potential difference applying step in which a high first type potential difference is applied to Vpc exceeds 0.5, the transition time becomes significantly shorter. The step of applying the first type of potential difference is about 0.1 to 3 seconds. Further, the level of the slew rate of the voltage change of the counter electrode generated when switching between the first type potential difference applying step and the second type potential difference applying step does not directly affect the transition time to the bend alignment. For this reason, even when driving a high-load electrode such as a counter electrode, the same effect can be obtained even if the voltage is gradually changed using a driving element having only a small current driving capability. As shown in FIG. 20, when the potential difference Vpc is changed in the repetitive control step of the cycle T, quick transition can be performed even if the times tr and tf required for the change of the potential difference each reach 30% of the cycle T.
[0081]
The current i [A] required to change the capacitance C [F] by V [V] in t seconds in a circuit as shown in FIG.
i = C * V / t
The current driving capability required to change the counter electrode having a capacitance of 10 [uF] by 10 [V] in 300 milliseconds is 0.33 [mA], which is suitable for a general-purpose operational amplifier or a low-power-consumption operational amplifier. A circuit can be formed by the current driving elements. Although not shown, the capacitive element may be driven by a pulse signal source and a series resistor.
[0082]
(No. 1-3 Embodiment)
13, 14, and 15, an operation of a common electrode potential variation type in which a first-type potential difference is increased by a potential change of a common electrode in the first embodiment is described as a third embodiment. Will be described with reference to FIG. The configuration is the same as in the first embodiment.
[0083]
In FIG. 22, Vg is the voltage of the gate line. Vs is the voltage of the source line. Vp is the voltage of the pixel electrode. Vcc is the voltage of the common electrode. Vc is the voltage of the counter electrode.
[0084]
While the pixel transistor is on, the potential Vs of the source line is written to the pixel electrode. When the pixel transistor is turned off, the penetration voltage calculated by (Equation 2-1) in accordance with the voltage change ΔVg of the gate line. The potential Vp of the pixel electrode changes by ΔVp1. Further, when the potential Vcc of the common electrode serving as the electrode of the storage capacitor is changed by ΔVcc while the pixel transistor is off, a penetration voltage ΔVp2 calculated by (Equation 2-2) is generated at the pixel electrode. In the case of the signal change shown in this drawing, a potential higher than the potential Vs written from the source line can be applied to the pixel electrode by making ΔVp2 larger than ΔVp1, and the potential difference Vpc between the pixel electrode and the counter electrode is reduced. And the transition time of the liquid crystal layer to the bend alignment can be shortened.
[0085]
ΔVp1 = ΔVg * Cgd / (Cst + Clc + Cgd) (Equation 2-1)
ΔVp2 = ΔVcc * Cst / (Cst + Clc + Cgd) (Equation 2-2)
At this time, as shown in FIG. 23, even if the voltage of the common electrode is the same as the voltage of the gate signal, Vpc can be sufficiently increased, and the size of the power supply circuit can be reduced by sharing the voltage.
[0086]
(No. 1-4 Embodiment)
FIG. 24 shows a configuration diagram of one pixel of the liquid crystal panel. In this figure, 6 is a pixel transistor, 3 is a pixel electrode, Cgd is a gate-drain capacitance of the pixel transistor, Cst is a storage capacitor connected to the pixel electrode and formed with the previous gate line, and Clc is a liquid crystal layer. The capacitance, Cgs, is the gate-source capacitance of the pixel transistor, 7 is the source line, 71 is the next source line, 8 is the gate line, 81 is the previous gate line, and 11 is the counter electrode. The liquid crystal panel having such a configuration is called a pre-gate system, and the aperture ratio can be increased because the common electrode can be eliminated as compared with the configurations shown in FIGS.
[0087]
FIG. 25 is a schematic plan and sectional view of the pixel structure. 6 is a pixel transistor, 21 is a transparent pixel electrode, Cst is connected to the pixel electrode, a storage capacitance formed between the gate line in the previous stage, Clc is a capacitance of a liquid crystal layer, 7 is a source line, and 71 is a next source line. , 8 are gate lines, 81 is a previous gate line, and 9 is a counter electrode.
[0088]
FIG. 26 shows an example of the dimension per pixel. Wt is the pixel width, Lt is the pixel length Lt, Wp is the pixel electrode width, Lp is the pixel electrode length, Ws is the source line width, Wg is the gate line width, and Wst is the length of the storage capacitor. The side, Lst, is the gap between the pixel electrode and the gate line, and the area of the pixel electrode is 18564 [μm ^ 2] out of 30,000 [μm ^ 2] per pixel, which is 61.9% of one pixel.
[0089]
Referring to FIGS. 24, 25, and 26, a fourth embodiment uses a gate line potential variation type in which a first-type potential difference is increased by a potential change of a gate line in the preceding stage in the second embodiment. The operation will be described with reference to FIG.
[0090]
In this figure, Vg is the voltage of the gate line, Vs is the voltage of the source line 7, Vp is the voltage of the pixel electrode, Vg- is the voltage of the preceding gate line 81, and Vc is the voltage of the counter electrode.
[0091]
During normal image display, the voltage Vg of the gate line is changed until the pixel transistor is turned on, and the voltage Vs of the source line is charged to the transparent pixel electrode 21, the storage capacitor Cst, and the liquid crystal capacitor Clc. The voltage Vp of the transparent pixel electrode 21 becomes equal to the voltage Vs of the source line 7.
[0092]
When the pixel transistor is turned off, the potential Vp of the pixel electrode changes by the penetration voltage ΔVp3 calculated by (Equation 2-3) according to the voltage change ΔVg of the gate line. Further, when the potential Vg- of the preceding gate line, which is the electrode of the storage capacitor, is changed by ΔVg- while the pixel transistor is off, a penetration voltage ΔVp4 calculated by the equation (2-4) is generated at the pixel electrode. I do. In the case of the signal change shown in FIG. 27, by making ΔVp4 larger than ΔVp3, a potential higher than the potential Vs written from the source line can be given to the pixel electrode, and the potential difference Vpc between the pixel electrode and the counter electrode is reduced. And the transition time of the liquid crystal layer to the bend alignment can be shortened.
[0093]
ΔVp3 = ΔVg * Cgd / (Cst + Clc + Cgd) (Equation 2-3)
ΔVp4 = ΔVg− * Cst / (Cst + Clc + Cgd) (Equation 2-4)
As shown in FIG. 26, the area ratio occupied by the pixel electrode in one pixel is as large as 61.9%. Therefore, it is very effective to apply a large potential difference between the pixel electrode and the counter electrode.
[0094]
The potential difference Vpc between Vc and Vp at the time of displaying a normal image in the liquid crystal panel having such a configuration is 0 V to 5 V. When a potential difference of 6 V or more is applied between the pixel electrode and the counter electrode by direct current for transition to the bend alignment, the transition state does not progress depending on the structure of the liquid crystal panel or the liquid crystal material, and the stuck liquid crystal element takes 10 seconds or more. Even if you do, you may not be able to transfer. In the case of such a panel or liquid crystal material condition, the voltage Vc of the counter electrode is brought close to the voltage Vs of the pixel electrode, and the potential difference Vpc applied to the liquid crystal layer is changed to a small second type of potential difference to set the orientation of the liquid crystal element in the initial state. By applying a high first-type potential difference again after returning, a potential difference is reapplied to the portion where the transition state is stuck, and as a result, it is possible to transition to the bend alignment in a short time over the entire panel.
[0095]
In the present embodiment, the storage capacitor is provided between the former stage gate line and the storage capacitor is provided between the latter stage gate line.
[0096]
(No. 1-5 Embodiment)
Using the time chart of the electrode potential of the pixel shown in FIG. 28 and the connection diagram of FIG. 1-5 The operation in the embodiment will be described.
[0097]
In FIG. 28, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick solid line indicates a pixel electrode potential. The lower Vpc indicates the fluctuation of the potential difference between the pixel electrode and the counter electrode. Tc is a normal video display period, T12 is a first second type potential difference applying step, T11 is a first first type potential difference applying step, T22 is a second second type potential difference applying step, and T21 is a second time. This is a first type of potential difference applying step. The figure shows various pixel electrode potential fluctuation factors.
[0098]
In the figure, T12, T11, T22, and T21 are repeated in a repetitive control step. When the first type of potential difference applying step T12 of the first drive period in the drive period for bend alignment of the liquid crystal layer starts, the counter electrode potential is set to a second potential different from the normal video display period. The pixel electrode potential is connected to the counter electrode via the liquid crystal capacitor. At this moment, since the pixel transistor is off and no current is supplied, the change in the counter electrode potential ΔVcom is given by (2-5) The potential changes by ΔVp5 in the direction in which the counter electrode potential has changed as shown on the left side of the period T12 in the drawing.
[0099]
ΔVp5 = ΔVcom * Clc / (Clc + Cst + Cgd) (Equation 2-5)
The potential variation ΔVg when the gate line potential changes the pixel transistor from on to off affects the pixel electrode is ΔVp6 shown in (2-6).
[0100]
When the source line potential is set to a potential obtained by adding ΔVp6 to the potential of the common electrode, and the pixel transistor is turned off, the potential of the pixel electrode decreases by ΔVp6 as shown by the fluctuation of the potential of the central gate electrode in the period T12 in FIG. Is a second type of potential difference of substantially zero.
[0101]
ΔVp6 = ΔVg * Cgd / (Clc + Cst + Cgd) (Equation 2-6)
Thereafter, during the first second-type potential difference applying step T12, the potential difference between the pixel electrode potential and the counter electrode potential except during a small charging step in which the pixel transistor is turned on and the pixel electrode is charged with the source line potential. Becomes a second kind of potential difference of almost zero.
[0102]
When the process proceeds from the first second-type potential difference applying step T12 to the first first-type potential difference applying step T11, the potential difference between the pixel electrode potential and the common electrode potential is changed to the first type potential difference to make the potential difference between the pixel electrode potential and the common electrode potential a first type potential difference. Is changed to the first potential, and the pixel electrode potential changes in the direction in which the counter electrode potential has changed, like the counter electrode potential fluctuation shown on the left side of the period T11 in FIG.
[0103]
When the pixel transistor is turned on and off once in a small charging step as in the case of the first time of the second type of potential difference applying step T12 of the second type of potential difference T12, the pixel electrode potential is changed to the second type of potential difference application. In the first type of potential difference application step, the potential difference between the pixel electrode potential and the counter electrode potential is sufficiently large for the liquid crystal layer to transition to the bend alignment. The counter electrode potential is set so as to have one type of potential difference. Thereafter, during the first type of first-type potential difference applying step T11, the first-type potential difference required for transition of the liquid crystal layer to the bend alignment is given as the potential difference between the pixel electrode potential and the counter electrode potential. .
[0104]
When the second type second potential difference applying step T22 starts, the counter electrode potential changes, so that the pixel electrode potential is influenced by the change in the counter electrode potential on the left side of the period T22 in FIG. As shown in (T12), the potential changes in the direction in which the counter electrode potential has changed. When the pixel transistor is turned on and off once in the small charging step, the pixel transistor is turned on and the pixel electrode is charged with the source line potential, similarly to the first type of second type potential difference applying step T12. The potential difference between the pixel electrode and the counter electrode is a second type of potential difference of substantially zero.
[0105]
When the process proceeds from the second potential difference applying step T22 of the second type to the potential difference applying step T21 of the second type for the second time, the potential difference between the pixel electrode and the counter electrode is equal to that of the liquid crystal in the same manner as the first potential difference applying step of the first type. A first type of potential difference required for the transition of the layer to the bend orientation is provided.
[0106]
Thereafter, the second type of potential difference application step and the first type of potential difference application step are alternately repeated in the repetitive control step until the transition of the liquid crystal layer to the bend alignment is completed. The potential difference between the pixel electrode and the counter electrode is almost zero, the second type of potential difference, and the first type of potential difference until the pixel transistor is turned on and the pixel transistor is not turned on in a small charging step. In the application step, a sufficiently large first-type potential difference required for the liquid crystal layer to transition to the bend alignment is given between the pixel electrode and the counter electrode except during the period from the start of the period until the first pixel transistor is turned on. I have.
[0107]
A first type of potential difference applying step for increasing the potential difference between the pixel electrode and the counter electrode to generate a bend alignment nucleus and expanding a bend region; and reducing the potential difference between the pixel electrode and the counter electrode to bend alignment. A second type of potential difference applying step for alternately realigning the liquid crystal layer in a portion where no nucleus of the nucleus does not occur or the bend region is not enlarged is applied alternately, so that the entire surface of the panel is rapidly transitioned to the bend alignment. Can be.
[0108]
The second type potential difference between the pixel electrode and the counter electrode during the second type potential difference applying step is desirably zero, but if it is within ± 1 V as shown in FIG. Does not affect much. The storage capacitance Cst, the liquid crystal capacitance Clc, and the gate-drain capacitance Cgd vary depending on the film thickness and the film quality both inside the panel and between the panels, and the variation ΔVp6 of the pixel electrode potential which is affected by the variation of the gate line potential. When the variation falls within ± 1 V, the source line potential in the second type potential difference applying step is reduced. panel It is not necessary to adjust each time, and a driving method in which the source line potential is fixed can be determined.
[0109]
(No. 1-6 Embodiment)
The operation of the sixth embodiment when the source line potential is changed in accordance with the ON / OFF timing of the pixel transistor in the second type potential difference applying step of the fifth embodiment with reference to FIGS. explain.
[0110]
FIG. 30 shows a time chart of the electrode potential of the pixel shown in FIG.
[0111]
In this figure, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick solid line indicates a pixel electrode potential. The lower Vpc is a potential difference between the pixel electrode and the counter electrode, and Vsc is a potential difference between the source line and the counter electrode. Tc is a normal image display period, T12 is a first second type potential difference applying step, T11 is a first first type potential difference applying step, T22 is a second second type potential difference applying step, and T21 is a second time. This is a first type of potential difference applying step. Also, various factors of the fluctuation of the pixel electrode potential are shown.
[0112]
In this drawing, when the second type of potential difference applying step T12 of the first drive period for the bend alignment of the liquid crystal layer starts, the counter electrode potential is set to a second potential different from the normal video display period. Assuming that the change in the counter electrode potential is ΔVcom, the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes as shown in the counter electrode potential change in FIG. . When the source line potential is set to a potential obtained by adding ΔVp6 to the potential of the common electrode, and the pixel transistor is turned on and off once in a small charging step, the potential of the pixel electrode decreases by ΔVp6 as shown in the gate electrode potential variation in FIG. The potential difference between the electrode and the electrode becomes a second kind of potential difference of substantially zero. The source line potential is substantially equal to the potential of the counter electrode while the pixel transistor is off, and is varied according to the ON / OFF timing of the pixel transistor in a small charging step, such as Vsc.
[0113]
Thereafter, during the first second-type potential difference applying step T12, the pixel transistor is turned on and off at the same timing as in the normal video display period, and the source line potential changes each time, and the pixel transistor is turned off. The potential difference between the pixel electrode / counter electrode and the pixel electrode / source line potential is a second type of potential difference of almost zero.
[0114]
When the potential difference between the source line potential and the counter electrode when the pixel transistor is off is within the range of ± 1 V, there is no change in the in-plane transition completion time. This is the same as that described in FIG. 29 in which the in-plane transition completion time is not significantly affected if the potential difference between the pixel electrode and the counter electrode is within ± 1 V in the fifth embodiment. .
[0115]
When the process proceeds from the first second-type potential difference applying step T12 to the first first-type potential difference applying step T11, the potential of the counter electrode is set to the first type in order to make the potential difference between the pixel electrode and the counter electrode a first type of potential difference. As a result, the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes, as shown by the change in the counter electrode potential on the left side of the period T11 in FIG. The source line potential is set to the common electrode potential in the same manner as in the first type T2 potential difference applying step T12. (Second potential) When the pixel transistor is once turned on and off in a small charging step as a potential obtained by adding ΔVp6 to the pixel electrode potential, the pixel electrode potential becomes the counter electrode potential in the second type potential difference applying step. (Second potential) Is almost equal to
[0116]
Also in the first type potential difference applying step, the source line potential is set at the timing of turning on / off the pixel transistor. But In the first type potential difference applying step, the potential difference between the pixel electrode and the counter electrode and between the source line and the common electrode is changed by the counter electrode potential in the second type potential difference applying step and the counter electrode potential in the first type potential difference applying step. It is almost equal to the potential difference between the potentials. Therefore, the potential of the common electrode in each period is set so that the potential difference between the common electrode potential in the first type potential difference applying step and the common electrode potential in the second type potential difference applying step becomes the first type potential difference required for the liquid crystal layer transition. Set.
[0117]
When the second type of potential difference applying step T22 of the second type starts, the potential of the counter electrode changes because the potential of the counter electrode changes due to the influence of the potential of the counter electrode on the left side of the period T22 in FIG. The potential changes in the direction in which the potential of the counter electrode changes as shown in FIG. In the subsequent charging operation by the pixel transistor, the pixel electrode potential changes in the same manner as in the first step of applying the second type of potential difference, and becomes substantially equal to the counter electrode potential.
[0118]
When the process shifts from the second second type potential difference applying step T22 to the second first type potential difference applying step T21, the counter electrode potential changes in the same manner as the first type first potential difference applying step. Also, by the charging of the pixel electrode by the pixel transistor, the same first type of potential difference as in the first type of first type of potential difference applying step T11 is applied between the pixel electrode and the counter electrode.
[0119]
Thereafter, the second type of potential difference applying step and the first type of potential difference applying step are alternately repeated in the control step until the transition of the liquid crystal layer to the bend alignment is completed. The potential difference between the electrodes and between the source line and the counter electrode is almost zero, which is the second kind of potential difference. In the first kind of potential difference applying step, the liquid crystal layer is required to transition to the bend alignment between the pixel electrode and the counter electrode. A sufficiently large first-type potential difference is provided.
[0120]
In this example, in addition to the operation described in the fifth embodiment, during the second-type potential difference applying step, the potential difference between the pixel electrode and the source line occupying most of the area in the plane and the counter electrode is reduced to zero. Therefore, the transition to the bend alignment of the liquid crystal layer can be further accelerated as compared with the fifth embodiment, although there is the complexity of fluctuating the source line potential.
[0121]
(No. 1-7 Embodiment)
The pixel electrode is charged by turning on the pixel transistor according to the fifth embodiment once in the initial period of the driving period for bend-aligning the liquid crystal layer, with reference to FIGS. 1-7 The operation of the embodiment will be described.
[0122]
FIG. 31 shows a time chart of the electrode potential of the pixel shown in FIG.
In FIG. 31, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick solid line indicates a pixel electrode potential. The lower Vpc is a potential difference between the pixel electrode and the counter electrode. Tc is a normal video display period, T12 is a first second type potential difference applying step, T11 is a first first type potential difference applying step, T22 is a second second type potential difference applying step, and T21 is a second time. This is a first type of potential difference applying step. In addition, various factors of the fluctuation of the pixel electrode potential are also shown.
[0123]
In this drawing, when the second type of potential difference applying step T12 of the first drive period for the bend alignment of the liquid crystal layer starts, the counter electrode potential is set to a second potential different from the normal video display period. The pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes as shown by the change in the counter electrode potential during the period T12 in FIG. When the source line potential is a potential obtained by adding ΔVp6 to the potential of the common electrode, and the pixel transistor is turned on and off once, the potential of the pixel electrode decreases by ΔVp6 as shown in the gate electrode potential variation in this figure, and is substantially equal to the potential of the common electrode. Become. Thereafter, during the first second type potential difference applying step T12, there is no change in the gate line potential, and the potential difference between the pixel electrode potential and the counter electrode potential 1 remains substantially the second type potential difference.
[0124]
From the first second potential difference applying step T12 to the first first potential difference applying step T 11 , The counter electrode potential is set to the first potential in order to make the potential difference between the pixel electrode and the counter electrode the first type of potential difference, and the pixel electrode potential is affected by the first potential difference. 11 As shown by the inner left counter electrode potential variation, the potential changes by ΔVp5 in the direction in which the counter electrode potential changes. Even if the process proceeds to the first type potential difference applying step, the pixel electrode is not charged by turning on the pixel transistor, so that the potential of the pixel electrode maintains the potential affected by the fluctuation of the counter electrode potential. The potential of the common electrode is set so that the potential difference between them becomes a sufficiently large first type potential difference required for the transition of the liquid crystal layer to the bend alignment.
[0125]
When the second type of potential difference applying step T22 of the second time starts, the potential of the counter electrode is changed to the second potential. 11 The potential of the common electrode changes in the direction in which the common electrode potential changes as indicated by the change in the common electrode potential shown in the transition from the period T22 to the period T22. And the potential difference from the counter electrode potential is a second type potential difference of substantially zero.
[0126]
When a transition is made from the second-time second type potential difference applying step T22 to the second-time first type potential difference applying step T21, the counter electrode potential changes to the first potential in the same manner as the first-time first type potential difference applying step. However, even during this period, the pixel electrode is not charged, and a first type potential difference similar to that in the first first type potential difference application step is applied between the pixel electrode and the counter electrode.
[0127]
Thereafter, the second type of potential difference applying step and the first type of potential difference applying step are alternately repeated in the control step until the transition of the liquid crystal layer to the bend alignment is completed. The potential difference between the electrodes becomes a second type potential difference of almost zero. In the first type potential difference applying step, a sufficiently large first type potential difference required for the liquid crystal layer to transfer between the pixel electrode and the counter electrode is generated. Given.
[0128]
In this example, although it is complicated to change the on / off timing of the pixel transistor from the normal video display period, the number of times the pixel electrode is charged by turning on the pixel transistor during the second type potential difference applying step is smaller than the normal timing. The time during which the potential difference between the pixel electrode and the counter electrode is zero increases during the second type of potential difference application step, and the transition of the liquid crystal layer to the bend alignment can be performed faster than in the fifth embodiment.
[0129]
Note that when the pixel electrode is not sufficiently charged by one turn-on of the pixel transistor, or when the drive period for transitioning the liquid crystal layer to the bend alignment starts asynchronously with the normal video display period, the pixel transistor is turned on. When a margin of the number of times is necessary to surely turn on, it is effective to charge the pixel electrode several times instead of once by turning on the pixel transistor at the beginning of the driving period for shifting the liquid crystal layer to the bend alignment. Does not affect much.
[0130]
The first turning on of the pixel transistor is performed within one field period (normally 16.7 milliseconds) after switching from normal video display timing to driving for bend alignment of the liquid crystal layer is completed. .
[0131]
(No. 1-8 Embodiment)
32 and 13, a first-type potential difference applying step in a driving period for bend-aligning the liquid crystal layer by charging the pixel electrode by turning on the pixel transistor in the small charging step of the fifth embodiment; The operation of the eighth embodiment in the case of performing once at the beginning of each of the two potential difference applying steps will be described.
[0132]
FIG. 32 shows a time chart of the electrode potential of the pixel shown in FIG.
[0133]
In this figure, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick solid line indicates a pixel electrode potential. The lower Vpc is a potential difference between the pixel electrode and the counter electrode. Tc is a normal video display period, T12 is a first second-type potential difference application step, T11 is a first first-type potential difference application step, T22 is a second second-type potential difference application step, and T21 is a second time. This is a first type potential difference applying step. Also, various factors of the fluctuation of the pixel electrode potential are shown.
[0134]
In FIG. 32, when the second type of potential difference application step T12 of the first drive period in the drive period for bend alignment of the liquid crystal layer is started, the counter electrode potential is set to a second potential different from the normal video display period. The pixel electrode potential is affected by the fluctuation of the counter electrode potential, and the potential changes by ΔVp5 in the direction in which the counter electrode potential changes as indicated by the fluctuation of the counter electrode potential on the left side in the period T12 in the drawing.
[0135]
When the source line potential is set to a potential obtained by adding ΔVp6 to the counter electrode potential, and the pixel transistor is turned on and off once in a small charging step, the pixel electrode potential decreases by ΔVp6 as shown by the gate electrode potential fluctuation at the center in the period T12. It becomes almost equal to the counter electrode potential. Thereafter, during the first second-type potential difference applying step T12, there is no change in the gate line potential, and the second-type potential difference between the pixel electrode and the counter electrode remains substantially zero.
[0136]
When the process proceeds from the first second-type potential difference applying step T12 to the first first-type potential difference applying step T11, the counter electrode potential is set to the first type in order to make the potential difference between the pixel electrode and the counter electrode a first type potential difference. , And the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes as shown by the left counter electrode potential fluctuation during the period T11. The source line potential is set to the common electrode potential in the same manner as in the first type T2 potential difference applying step T12. (Second potential) When the pixel transistor is once turned on and off in a small charging step as a potential obtained by adding ΔVp6 to the potential of the pixel electrode, the pixel electrode potential becomes the counter electrode potential in the second type potential difference applying step in the same manner as the gate electrode potential variation. (Second potential) Is almost equal to
[0137]
Thereafter, during the first type of first-type potential difference applying step T11, the pixel electrode is not charged by turning on the pixel transistor, so that the pixel electrode potential does not change. Thus, in the first type of potential difference application step, the potential difference between the pixel electrode and the counter electrode is substantially equal to the potential difference between the counter electrode potential in the second type potential difference application step and the counter electrode potential in the first type potential difference application step. Therefore, the counter electrode potential in each period is set so that the potential difference between the counter electrode potential in the first type potential difference application step and the counter electrode potential in the second type potential difference application step becomes a potential difference required for transition of the liquid crystal layer to the bend alignment. Set.
[0138]
When the second type of potential difference applying step T22 of the second time starts, the potential of the counter electrode changes, and the potential of the pixel electrode is affected by the change in the period T22. 11 And the potential changes in the direction in which the potential of the common electrode changes as indicated by the change in the common electrode potential at the boundary between the periods T22 and T22. In the subsequent pixel electrode charging operation by turning on the pixel transistor, the potential becomes the pixel electrode potential in the first type of second potential difference application step, and the potential difference from the counter electrode potential becomes a second type potential difference of substantially zero.
[0139]
When the process proceeds from the second-time second-type potential difference applying step T22 to the second-time first-type potential difference applying step T21, the counter electrode potential changes in the same manner as in the first-time first type potential difference applying step. Also during the initial turning on of the pixel transistor, a first type potential difference similar to that in the first first type potential difference applying step is applied between the pixel electrode and the counter electrode.
[0140]
Thereafter, the second type of potential difference applying step and the first type of potential difference applying step are alternately repeated in the control step until the transition of the liquid crystal layer to the bend alignment is completed. The potential difference between the electrodes becomes a second type potential difference of almost zero. In the first type potential difference applying step, the potential difference between the pixel electrode and the counter electrode is a sufficiently large first type potential difference necessary for the liquid crystal layer to transfer. Is given.
[0141]
By performing the charging of the source line potential to the pixel electrode only once at the beginning of each period, the control of the on / off timing of the pixel transistor becomes more complicated than in the seventh embodiment. While reducing the time when the pixel transistor is turned on during the potential difference applying step and the potential difference between the pixel electrode and the counter electrode is not zero, the pixel electrode potential is determined at the beginning of each period to eliminate the influence of the fluctuation of the counter electrode potential, The transition to the bend alignment over the entire panel is faster than in the fifth and seventh embodiments.
[0142]
Similarly to the seventh embodiment, when the pixel electrode is not sufficiently charged by one turn-on of the pixel transistor, or when the driving period for shifting the liquid crystal layer to the bend alignment is longer than the normal video display period. If a margin is required to start the pixel transistor asynchronously and turn on the pixel transistor reliably, the effect of charging the pixel electrode by turning on the pixel transistor at the beginning of each period several times instead of once is not so large. do not do.
[0143]
(No. 1-9 Embodiment)
The operation of the ninth embodiment when the off-voltage of the gate line is set to DC during the drive period for bend-aligning the liquid crystal layer of the fifth embodiment will be described with reference to FIGS.
[0144]
FIG. 33 shows a time chart of the electrode potential of the pixel shown in FIG.
[0145]
In this drawing, the electrical operation timing during the drive period for bend-aligning the liquid crystal layer is the same as in the fifth embodiment. In the liquid crystal panel having the structure shown in FIG. 24, a storage capacitor Cst is formed between the gate line 81 and the transparent pixel electrode 21 in the preceding stage, and a potential difference is given between adjacent rows of pixels during the normal video display period. The potential of the previous gate line and the potential of the counter electrode are changed in the same direction. This operation is performed while the gate line selects the potential for turning off the pixel transistor, that is, the off voltage.
[0146]
If this operation continues even during the driving period for bend alignment of the liquid crystal layer, the pixel electrode potential fluctuates by ΔVp6 of the equation (6) due to the fluctuation of the off-state voltage of the preceding gate line. Therefore, a potential difference of several volts is generated even if it is desired to make the potential difference between the pixel electrode and the counter electrode a second-type potential difference of substantially zero. When the potential difference between the pixel electrode and the counter electrode in the second type of potential difference application step exceeds 1 volt as shown in FIG. 29, the transition completion time becomes longer.
[0147]
Therefore, during the drive period for bend alignment of the liquid crystal layer as shown in FIG. 33, the off voltage of the gate line is changed to DC in the step of holding the gate line off voltage DC, so that the pixel electrode in the second type potential difference applying step is changed. Can be avoided, and the transition to bend alignment over the entire panel can be speeded up.
[0148]
(No. 1-10 Embodiment)
The operation in the tenth embodiment will be described with reference to FIGS.
[0149]
FIG. 34 shows a time chart of the electrode potential of the pixel shown in FIG.
[0150]
In this figure, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick solid line indicates a pixel electrode potential. The lower Vpc is a potential difference between the pixel electrode and the counter electrode, and Vsc is a potential difference between the source line and the counter electrode. Tc is a normal video display period, T12 is a first second type potential difference applying step, T11 is a first first type potential difference applying step, T22 is a second second type potential difference applying step, and T21 is a second time. This is a first type of potential difference applying step. Also, various factors of the fluctuation of the pixel electrode potential are shown.
[0151]
In FIG. 34, when the second type of potential difference application step T12 of the first drive period for driving the liquid crystal layer for bend alignment starts, the counter electrode potential is set to a second potential different from the normal video display period. The pixel electrode potential 4 is connected to the counter electrode via the liquid crystal capacitance Clc. At this moment, the pixel transistor is turned off and there is no current supply. Therefore, the difference of the counter electrode potential ΔVcom by ΔVp5 of equation (5) from T12 The potential changes in the direction in which the counter electrode potential changes, as indicated by the change in the counter electrode potential at the left end. When the source line potential is set to a potential obtained by adding ΔVp6 to the counter electrode potential, and the pixel transistor is turned on and off once in a small charging step, the pixel electrode potential decreases by ΔVp6 as shown by the gate electrode potential fluctuation at the center of the period T12. It becomes almost equal to the counter electrode potential.
[0152]
When the process proceeds from the first second-type potential difference applying step T12 to the first first-type potential difference applying step T11, the potential difference between the pixel electrode and the counter electrode is changed to the first type potential difference. 1 and the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes as shown by the change in the counter electrode potential at the boundary between the periods T11 and T12. The source line potential is set to the common electrode potential in the same manner as in the first type T2 potential difference applying step T12. (Second potential) When the pixel transistor is once turned on and off in a small charging step as a potential obtained by adding .DELTA.Vp6 to the potential of the pixel electrode, the pixel electrode potential decreases due to the influence of the potential fluctuation of the gate line potential similarly to the fluctuation of the gate electrode potential in the period T11.
[0153]
In the first-type potential difference applying step, the transition to the bend alignment of the liquid crystal layer can be accelerated as the potential difference between the pixel electrode and the counter electrode increases, so that the second-type potential difference applying step is changed to the first-type potential difference applying step. The source line potential is changed in a direction opposite to the change in the counter electrode potential. The counter electrode potential is set so that the potential difference from the pixel electrode potential is a first type potential difference required for transition of the liquid crystal layer to bend alignment.
[0154]
When the second-time second type potential difference applying step T22 starts, the potential of the common electrode changes because the potential of the common electrode changes due to the influence thereof, as shown by the change in the common electrode potential at the boundary between the periods T12 and T22. The potential changes in the changed direction. In the subsequent pixel electrode charging operation by turning on the pixel transistor, the potential becomes the pixel electrode potential in the first type of second potential difference application step, and the potential difference from the counter electrode potential becomes a second type potential difference of substantially zero.
[0155]
When the process proceeds from the second-time second-type potential difference applying step T22 to the second-time first-type potential difference applying step T21, the counter electrode potential changes in the same manner as in the first-time first type potential difference applying step. Even during the charging of the pixel electrode by turning on the pixel transistor, a first type potential difference similar to that in the first first type potential difference applying step is applied between the pixel electrode and the counter electrode.
[0156]
Thereafter, the second type of potential difference application step and the first type of potential difference application step are alternately repeated in the repetitive control step until the transition of the liquid crystal layer to the bend alignment is completed. Unless the pixel transistor is turned on and the pixel electrode is charged in the small charging step until the second pixel transistor is turned on, the potential difference between the pixel electrode and the counter electrode becomes a second type potential difference of almost zero, In one type of potential difference application step, a sufficiently large first type potential difference necessary for the liquid crystal layer to transition to the bend alignment is applied between the pixel electrode and the counter electrode except during the period from the start of the period until the first turn on of the pixel transistor. Can be
[0157]
By varying the source line potential between the second type potential difference applying step and the first type potential difference applying step, the first type potential difference applying step increases the first type potential difference between the pixel electrode and the counter electrode in the first type potential difference applying step. Therefore, the transition of the liquid crystal layer to the bend alignment can be accelerated.
[0158]
FIG. 35 shows the case where the driving period for bend-aligning the liquid crystal layer in the fifth and sixth embodiments is started from the first type of potential difference applying step, and the case where the driving period is changed from the second type of potential difference applying step. The measurement result of the time required until the transfer is completed in the case of starting is shown.
[0159]
The horizontal axis shows the first type of potential difference between the pixel electrode and the counter electrode in the first type of potential difference application step. The greater the potential difference, the shorter the transition completion time. When the process is started from the potential difference applying step, the transition to the bend orientation is completed earlier.
[0160]
(No. 1-11 Embodiment)
The operation in the eleventh embodiment will be described with reference to FIG. 36 and FIG.
[0161]
In FIG. 36, a thick dotted line indicates a counter electrode potential, a thin dotted line indicates a gate line potential, a thin solid line indicates a source line potential, and a thick dotted line indicates a pixel electrode potential. Vpc is a potential difference between the pixel electrode and the counter electrode. Three Tc are a normal image display period, T12 is a first type of second type potential difference applying step, T11 is a first type of first type potential difference applying step, T22 is a second type of second type potential difference applying step, and T21 is a second type of potential difference applying step. This is the second type of potential difference application step of the first type. Also, various factors of the fluctuation of the pixel electrode potential are shown.
[0162]
In this drawing, when the second type of potential difference applying step T12 of the first drive period for the bend alignment of the liquid crystal layer starts, the counter electrode potential is set to a second potential different from the normal video display period. The pixel electrode potential is connected to the counter electrode via the liquid crystal capacitance Clc. At this moment, since the pixel transistor is off and no current is supplied, the pixel electrode potential is shown at the left end of the T12 by ΔVp5 with respect to the counter electrode potential variation ΔVcom. Thus, the potential changes in the direction in which the potential of the counter electrode changes.
[0163]
When the source line potential is set to a potential obtained by adding ΔVp6 to the potential of the common electrode, and the pixel transistor is once turned on and off in a small charging step, the potential of the pixel electrode decreases by ΔVp6 as shown in the center of the present T12, and becomes substantially equal to the potential of the common electrode. Be equal. Thereafter, during the first second-type potential difference applying step, the potential difference between the pixel electrode potential and the counter electrode potential is not except when the pixel transistor is turned on in the small charging step and the pixel electrode is charged with the source line potential. A second type of potential difference of almost zero results.
[0164]
When the process proceeds from the first-time second-type potential difference applying step T12 to the first-time first-type potential difference applying step T11, the potential difference between the pixel electrode potential and the common electrode potential is changed to the first type potential difference by the common electrode potential difference. Is changed to the first potential, and the pixel electrode potential changes by ΔVp5 in the direction in which the counter electrode potential changes under the influence of the first potential. The source line potential is set to the common electrode potential in the same manner as in the first type T2 potential difference applying step T12. (Second potential) When the pixel transistor is turned on and off once in a small charging step as a potential obtained by adding ΔVp6 to the potential of the pixel electrode, the potential of the pixel electrode becomes the opposite electrode potential in the second type potential difference applying step due to the potential fluctuation of the gate line potential (Second potential) However, in the first type of potential difference applying step, the potential difference between the pixel electrode potential and the counter electrode potential is reduced to a sufficiently large first type potential difference required for the liquid crystal layer to transition to bend alignment. The potential of the counter electrode is set so as to be as follows. Thereafter, during the first type of first-type potential difference applying step T11, the first-type potential difference required for the transition of the liquid crystal layer to the bend alignment is given as the potential difference between the pixel electrode potential and the counter electrode potential. .
[0165]
When the second type of second potential difference applying step T22 starts, the potential of the counter electrode changes because the potential of the pixel electrode changes due to the influence of the potential of the pixel electrode in the direction in which the potential of the counter electrode changes as indicated by the first variation of the potential of the counter electrode in T22. However, once the pixel transistor is turned on and off once, the pixel transistor is turned on and the pixel electrode is charged except when the source electrode potential is charged to the pixel electrode, as in the first type T2 of the second type of potential difference application step T12. The potential difference between the electrode and the counter electrode is a second type of potential difference of substantially zero.
[0166]
When the process proceeds from the second-time second-type potential difference applying step T22 to the second-time first-type potential difference applying step T21, the counter electrode potential changes in the same manner as in the first-time first type potential difference applying step. Is turned on and the pixel electrode is charged with the source line potential and the pixel transistor is turned off, the potential difference between the pixel electrode potential and the counter electrode potential is necessary for the transition of the liquid crystal layer to the bend alignment. A first type of potential difference is provided.
[0167]
Thereafter, the second type of potential difference applying step and the first type of potential difference applying step are alternately repeated in the repetitive control step until the transition of the liquid crystal layer is substantially completed, and in the second type of potential difference applying step, the first pixel after the start of the period Until the transistor is turned on and when the pixel transistor is not turned on, the potential difference between the pixel electrode and the counter electrode becomes a second type potential difference of almost zero, and in the first type potential difference applying step, the potential difference is 1 after the start of the period. A sufficiently large first-type potential difference necessary for the liquid crystal layer to transition to the bend alignment is given between the pixel electrode and the counter electrode except during the period until the second pixel transistor is turned on.
[0168]
When the transition to the bend alignment of the liquid crystal layer is almost completed and before the transition to the normal video display period Tc, video information having a large potential difference between the pixel electrode and the counter electrode in the transition high potential difference applying step (usually black or white). Is displayed in one field, the expansion of the bend alignment region of the liquid crystal layer is completed, and thereafter, the process shifts to the next normal video display period Tc for displaying the original input video information.
[0169]
Usually, the first type of potential difference application step and the second type of potential difference application step are often several fields or more and several hundred milliseconds or more in time, and are required to complete the transition to the bend alignment of the liquid crystal layer. When one type of potential difference applying step or the second type of potential difference applying step is added once, the transition completion time increases in units of several hundred milliseconds. When the transition is completed only by expanding the bend area without generating a new bend nucleus, displaying video information with a large potential difference between the pixel electrode and the counter electrode can be added by adding several tens of milliseconds. In addition, the transfer completion time can be shortened.
[0170]
｛ Reference Example 2 ｝
Book Reference Example 2 Relates to control of startup of each unit when the power is turned on.
[0171]
Hereinafter, the book based on the embodiment Reference Example 2 Will be described.
[0172]
Below, the book Reference Example 2 Will be described with reference to FIGS. 37 and 38. The book Reference Example 2 Is one embodiment.
[0173]
In FIG. 37, Vg is a gate line potential. Vs is the potential of the source line. Vp is the potential of the pixel electrode. Vpc is a potential difference between the pixel electrode and the counter electrode. Further, To is a power-off period, and T12 is a first type of second-type potential difference application step. T11 is a first type of potential difference application step of the first type, and Tc is a display period of a normal image. Also, various factors of the fluctuation of the pixel electrode potential are shown.
[0174]
38, reference numeral 3801 denotes a main power supply, 3802 denotes a power supply circuit controller, 3803 denotes various power supply voltage generation circuits, 3804 denotes a liquid crystal panel controller, and 3805 denotes a liquid crystal panel. A start switch 3810 is connected to the main power supply 3801 and the liquid crystal panel controller 3804 from outside. The start switch 3810 is connected to a counter 3811 inside the liquid crystal panel controller 3804 and a switching means A of 3812 following the counter 3811. After the power is supplied to the liquid crystal panel controller 3804 after the start, a predetermined period is set by the counter. After counting, the video signal from the normal video signal generation unit 3813 is applied to the liquid crystal panel 3805. While the predetermined period is being counted, the voltage generation means 1 of 3814 and the voltage generation means 2 of 3815 are switched by the switching means B 3817 at a predetermined cycle set by the cycle counter 3816.
[0175]
In the circuit of FIG. 38, all signals input to the liquid crystal panel are undefined during the power-off period To. When the start switch 3810 is turned on to turn on the power, first, power is supplied only to the power supply circuit controller 3802, and the controller 3802 sequentially controls various power supply voltage generation circuits to start the operation of the liquid crystal panel controller. By adopting such a circuit configuration having a liquid crystal layer stable holding start-up control step, it becomes possible to immediately set the voltage of the second type potential difference application step after turning on a signal input to the liquid crystal panel, The transition period of the liquid crystal layer to the bend alignment can be started without breaking the alignment state of the liquid crystal layer in the state where no voltage is applied, and the transition completion time after turning on the power can be shortened.
[0176]
When no voltage is applied, the liquid crystal layer is aligned in the splay alignment state along the rubbing groove of the substrate. However, if any potential difference is applied, the liquid crystal elements which tend to transition to the bend alignment start in order. If a liquid crystal element that remains in splay alignment and a liquid crystal element that is about to shift to bend alignment are randomly mixed in the liquid crystal panel surface, even if a large potential difference is applied to those liquid crystal elements at the same time, the transition to lubricious bend alignment will occur. May not be done. In this embodiment mode, the occurrence of a liquid crystal element which starts transition to bend alignment by applying a random potential difference immediately after the power of the liquid crystal device is turned on is suppressed, and the transition to bend alignment with respect to the liquid crystal element in which the entire surface is in a splay alignment state is suppressed. It is intended to start driving for.
[0177]
Table 1 shows an example of an experimental result by the driving method according to the present embodiment.
[0178]
[Table 1]

The driving method according to the present embodiment refers to a method in which, after power is turned on, a counter electrode potential, a gate line potential, and a source line potential input to a liquid crystal panel all output voltages to be output in a second type of potential difference applying step. It is. On the other hand, in the conventional method in which there is a normal video display period before the second type of potential difference applying step, various power supply voltage generating circuits start up without power control after the power is turned on, and usually before the second type of potential difference applying step. The same voltage as in the video display period is output to the common electrode potential, the gate line potential, and the source line potential. Observing the transition completion state by changing the time required for the second type potential difference applying step in these two methods, it was found that the transition was completed in a shorter time in the driving method of the present embodiment.
[0179]
In the embodiments of the second invention group and the present invention group, the source line potential does not need to be similarly changed between the first type of potential difference applying step and the second type of potential difference applying step, and differs in each period. There is no problem if the timing changes at different potentials.
[0180]
As described above, the present invention has been described based on some embodiments, but it is needless to say that the present invention is not limited to these embodiments. That is, for example, the following may be performed.
[0182]
1) The liquid crystal display device is of a reflection type, so-called ROCB.
[0183]
2) The liquid crystal device is an optical switch, an optical logic element, or the like.
[0184]
【The invention's effect】
As can be seen from the above description, according to the present invention,
By applying a first type of potential difference between the pixel electrode and the counter electrode, which occupy a large area in the liquid crystal panel, as compared with that during normal image display, it is possible to generate nuclei in the bend alignment of the liquid crystal layer and expand the bend region. As a result, the liquid crystal layer can be transferred to the bend alignment in a short time over the entire surface of the panel, and a liquid crystal panel with high speed response and a wide viewing angle can be provided.
[0185]
In addition, between the pixel electrode and the counter electrode of the liquid crystal panel, the
A liquid crystal layer is provided by alternately providing a first type of potential difference applying step of applying a high first type of potential difference and a second type of potential difference applying step of applying a second type of potential difference smaller than the first type of potential difference. The generation of nuclei in the bend alignment and the expansion of the bend region and the realignment of the liquid crystal layer are alternately performed. As a result, the liquid crystal layer can be transferred to the bend alignment in a short time over the entire panel, and the response can be widened with high speed. A liquid crystal panel with a wide viewing angle can be provided.
[0186]
Further, by changing the potential of the common electrode forming a storage capacitor between the pixel electrode and the pixel electrode, the potential of the pixel electrode is changed so that the potential difference between the pixel electrode and the counter electrode becomes larger than the potential given from the source line. By applying a high potential difference to the liquid crystal layer, the liquid crystal layer can be transferred to the bend alignment in a shorter time over the entire surface of the panel, and a liquid crystal panel with high speed response and a wide viewing angle can be provided.
[0187]
In addition, by changing the potential of the gate line in the previous stage where a storage capacitor is formed between the pixel electrode and the pixel electrode, the potential difference between the pixel electrode and the counter electrode is made larger than the potential given from the source line. By causing the liquid crystal layer to fluctuate and apply a high potential difference to the liquid crystal layer, the liquid crystal layer can be transferred to the bend alignment in a shorter time over the entire surface of the panel, and a liquid crystal panel with high speed response and a wide viewing angle can be provided.
[0188]
Also, by taking into account the potential fluctuation generated in the pixel electrode when the pixel transistor is turned off, the on / off timing of the gate line is not changed from that during normal image display, so that the pixel electrode and the counter electrode can be used. A first type of potential difference and a second type of potential difference effective for the transition of the liquid crystal layer to the bend alignment can be provided therebetween, and the transition to the bend alignment over the entire panel can be performed at high speed.
[0189]
Similarly, while the on / off timing of the gate line is the same as during normal image display, when the pixel transistor is off, the potential of the source line is further changed so that the liquid crystal layer is also provided between the source line and the counter electrode. By imparting a second type of potential difference effective for transition to bend alignment, the transition to bend alignment over the entire panel can be further accelerated.
[0190]
In addition, by performing at least one charge of the pixel electrode by turning on the pixel transistor at the beginning of the driving period for shifting the liquid crystal layer to the bend alignment, the complexity of changing the on / off timing of the pixel transistor from the normal video display period is eliminated. However, since the number of times of charging the pixel electrode during the second type of potential difference applying step is smaller than the normal timing, the time during which the potential difference between the pixel electrode and the counter electrode is zero increases during the second type of potential difference applying step. The transition to bend alignment over the entire surface can be made faster.
[0191]
In addition, the pixel transistor is charged by turning on the pixel transistor at least once at the beginning of each of the first type potential difference applying step and the second type potential difference applying step for bend alignment of the liquid crystal layer. The control of the OFF timing becomes more complicated, but by determining the pixel electrode potential at the beginning of each period, the influence of the fluctuation of the counter electrode potential is completely eliminated, and the first type potential difference and the second type potential difference are provided. Therefore, the transition to the bend alignment over the entire surface of the panel can be further accelerated.
[0192]
In addition, during the driving period of the transition of the liquid crystal layer to the bend alignment, the off-voltage of the gate line is set to DC, thereby eliminating the influence of the pixel line from the gate line potential fluctuation, particularly in the second type potential difference applying step. Thus, the transition to the bend alignment over the entire panel can be performed at high speed.
[0193]
Further, the potential of the source line is varied between the first type potential difference applying step and the second type potential difference applying step, and the potential difference between the pixel electrode and the counter electrode in the first type potential difference applying step is increased. In addition, the transition to the bend alignment over the entire panel can be performed at high speed.
[0194]
In addition, before the drive period for bend alignment of the liquid crystal layer is completed and before the transition to the normal image display period, video information having a large potential difference between the pixel electrode and the counter electrode is displayed in one field, so that the bend alignment is performed. Bend alignment by adding one field, that is, tens of milliseconds, without adding a first type of potential difference applying step or a second type of potential difference applying step to increase the time for completion of transition by several hundred milliseconds. Can be completed, and the time required for completing the transfer on the entire panel can be reduced.
[0195]
In addition, by starting the second type of potential difference applying step without excessively disturbing the state of the liquid crystal layer when the power is turned on from the state when the power is not turned on, the liquid crystal layer can be aligned in a shorter time, and the entire panel can be aligned. Of the liquid crystal layer to the bend alignment can be accelerated.
[Brief description of the drawings]
FIG. 1 is a view showing a state of splay alignment (1) and (2) and bend alignment (3) of a liquid crystal element.
FIG. 2 is a diagram showing a plane and a cross section of a structure of a main part for one pixel of a conventional liquid crystal panel.
FIG. 3 is a diagram schematically showing a conventional liquid crystal panel and a capacitive load between a gate line electrode and a counter electrode in some embodiments.
FIG. 4 is a diagram illustrating a configuration of one pixel of the liquid crystal panel according to the first embodiment.
FIG. 5 is a diagram illustrating a configuration for one pixel of a liquid crystal panel according to a 1-2th embodiment.
FIG. 6 is a diagram illustrating a configuration for one pixel of the liquid crystal panel according to the first to third embodiments.
FIG. 7 is a diagram illustrating a configuration for one pixel of the liquid crystal panel according to the first to fourth embodiments.
FIG. 8 is a diagram showing a configuration for one pixel of a liquid crystal panel according to the first to fifth embodiments.
FIG. 9 is a diagram illustrating a configuration of one pixel of the liquid crystal panel according to the first to sixth embodiments.
FIG. 10 is a sectional view of the liquid crystal device according to the first to seventh embodiments.
FIG. 11 is a sectional view of the liquid crystal device according to the first to eighth embodiments.
FIG. 12 is a sectional view of the liquid crystal device according to the first to ninth embodiments.
FIG. 13 is a diagram illustrating a circuit configuration of a pixel of a liquid crystal device according to Embodiment 2-1 and the like.
FIG. 14 is a view similarly showing a structure of a pixel.
FIG. 15 is a diagram showing the dimensions of the pixel.
FIG. 16 is a diagram showing a state and an action of a voltage applied to or added to each part between pixels.
FIG. 17 is a diagram illustrating a state of voltage application and an operation according to the 2-2nd Embodiment;
FIG. 18 is a configuration diagram of a control unit of the liquid crystal device of the above embodiment.
FIG. 19 is a diagram showing a correlation between a duty ratio of a first type potential difference applying step and a transition completion time in the 2-2nd embodiment.
FIG. 20 is a diagram showing times tr and tf required for changing a potential difference Vpc between a pixel electrode and a counter electrode.
FIG. 21 is a diagram showing a specific configuration of the circuit.
FIG. 22 is a diagram illustrating a state and an operation of applying a voltage according to the second to third embodiments.
FIG. 23 is a diagram showing a modification of the above embodiment.
FIG. 24 is a diagram illustrating a circuit configuration of a pixel according to a second to fourth embodiments.
FIG. 25 is a diagram showing a structure of a pixel in the above embodiment.
FIG. 26 is a diagram showing dimensions of a pixel in the above embodiment.
FIG. 27 is a diagram showing the operation of the second to fourth embodiments.
FIG. 28 is a time chart of the electrode potential of the pixel according to the second to fifth embodiments.
FIG. 29 is a diagram showing a measurement result of a relationship between a potential difference and a transition completion time when a potential difference between a pixel electrode and a counter electrode changes.
FIG. 30 is a time chart of the electrode potential of the pixel according to the second to sixth embodiments.
FIG. 31 is a time chart of the electrode potential of the pixel according to the second to seventh embodiments.
FIG. 32 is a time chart of the electrode potential of the pixel according to the second to eighth embodiments.
FIG. 33 is a time chart of the electrode potential of the pixel according to the 2-9th embodiment;
FIG. 34 is a time chart of the electrode potential of the pixel according to the 2-10th embodiment;
FIG. 35 shows a case where a driving period for bend alignment of a liquid crystal layer is started from a first type of potential difference applying step and a second type of potential difference in the second to fifth embodiments. FIG. 9 is a diagram illustrating a measured value of a transition completion time when starting from an application step.
FIG. 36 is a time chart of the electrode potential of the pixel according to the 2-11th embodiment;
FIG. 37 is a time chart of the embodiment 3-1.
FIG. 38 is a diagram showing a configuration of a circuit in the above embodiment and the like.
[Explanation of symbols]
1 First substrate
2 Second substrate
3 Pixel electrode
21 Transparent pixel electrode
5 Liquid crystal layer
6 pixel transistor
7 Source line, source line electrode
70 Source line forming metal film
71 Source line
8 Gate line, gate line electrode
81 Previous Gate Line
9 Counter electrode
10 Common electrode
11 Black matrix
12 Color filters
64 channel protective film
65 a-Si layer
66 n + a-Si layer
76 Insulation film between source line electrode and liquid crystal layer
86 insulating film between gate line electrode and a-Si layer
87 insulating film
Vcc potential of common electrode
Vc Potential of counter electrode
Vg Gate line potential
Vs Source line potential
Vp Pixel electrode potential
Vpc Potential difference between pixel electrode and counter electrode
Tc Normal video display period
Cgd Capacitance between gate line and pixel electrode
Cst Storage capacitance between pixel electrode and common electrode
Liquid crystal capacitance between Clc pixel electrode and counter electrode
Cgs Capacitance between gate line and source line
204 LCD panel controller
205 LCD panel

Claims

A first substrate on which thin film transistors and pixel electrodes are formed in a matrix, a second substrate on which counter electrodes are formed, and a liquid crystal layer between the first substrate and the second substrate; In a method of driving a liquid crystal device that performs image display with a liquid crystal layer having a bend alignment,
Between the counter electrode of the first pixel electrode and the second substrate of the substrate, the first type of potential difference application step of indicia pressure to different first type of potential difference and the potential difference applied to the normal image display period When,
And a second type potential difference applying step of applying a second type potential difference smaller than the first type potential difference, at least once alternately,
A method for driving a liquid crystal device, wherein the step of applying the second type of potential difference is performed before the step of applying the first type of potential difference .

In one repetition period of the application of the first type of potential difference application step and the second type of potential difference application step, the period of applying the first type potential difference is 50% or more and 95% or less. The method for driving a liquid crystal device according to claim 1, wherein

When the first type of potential difference and the second type of potential difference are alternately applied, the time required to switch the potential difference is set to be 30% or less of one cycle of the one repetition period. A method for driving a liquid crystal device according to claim 2 .

The first type of potential difference applying step is
A storage capacitor connected to each pixel electrode is formed between a common electrode having a common potential with respect to all pixel electrodes, and a pixel electrode capacitor including the storage capacitor and a gate line parasitic to the thin film transistor and the pixel electrode. 2. The method according to claim 1, wherein a potential difference is obtained by utilizing a potential change of a pixel electrode which accompanies a potential change of a common electrode based on a ratio to the capacitance of the common electrode .

The first type potential difference applying step includes:
5. The method according to claim 4, wherein the voltage applied to the common electrode is equal to the voltage used for the gate signal.

The first type of potential difference applying step includes:
A storage capacitor connected to each pixel electrode is formed between the gate line before or after one line, and the ratio of the pixel electrode capacitance including the storage capacitor to the capacitance between the gate line and the pixel electrode parasitic on the thin film transistor. 2. The method according to claim 1, wherein a potential difference is obtained by using a potential change of a pixel electrode which accompanies a potential change of a gate line before or after one line .

In the period of the second type of potential difference applying step, when the thin film transistor is turned on from off, a potential obtained by adding a potential variation generated in the pixel electrode caused by the potential variation of the gate line to the counter electrode potential is applied to the source line. The driving method of a liquid crystal device according to claim 1, further comprising a charging small step of charging the pixel electrode by charging .

The second type of potential difference applying step includes:
The method according to claim 7, wherein the second type of potential difference is set within ± 1V .

The second type of potential difference applying step includes:
8. The driving method of a liquid crystal device according to claim 7, wherein a potential equal to that of the counter electrode is applied to the source line when the pixel transistor is off during the period of applying the second type of potential difference .

The driving method of a liquid crystal device according to claim 7, wherein the small charging step is performed at least once at an initial stage of a driving period for performing the bend alignment of the liquid crystal layer .

The small charging step is performed at least once at the beginning of the first type potential difference applying step and the second type potential difference applying step during a period in which the liquid crystal layer is driven for bend alignment. A method for driving a liquid crystal device according to claim 7 .

8. The method according to claim 7, further comprising the step of keeping the off voltage of the gate line at DC .

In the period of the second type of potential difference applying step, when the thin film transistor is turned on from off, a potential obtained by adding a potential variation generated in the pixel electrode caused by the potential variation of the gate line to the counter electrode potential is applied to the source line. Having a charging small step of charging the pixel electrode by
During the period in which the first type potential difference is applied, the potential of the source line is set to a different potential from the period in which the second type potential difference is applied so that the first type potential difference becomes larger. The method for driving a liquid crystal device according to claim 1, wherein:

The above steps are performed at least alternately at least once, and a large potential difference among the potential differences applied to the liquid crystal layer during the normal video information display period is transferred to the liquid crystal layer before the transition to the period for displaying the normal video information. 2. The method according to claim 1, further comprising the step of applying at least one field .

2. The liquid crystal device according to claim 1, further comprising a step of controlling start-up of each part of the liquid crystal device so as not to disturb the alignment state of the liquid crystal layer excessively after power-on and before application of a potential difference. Drive method.

A liquid crystal device driven by the liquid crystal device driving method according to claim 1.