JP3593755B2 - Digital signal reproduction circuit and reproduction method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital signal reproducing circuit and a reproducing method for reproducing a digital signal recorded on, for example, a tape, and more particularly to an automatically adjustable equalizer and an automatic adjusting method.
[0002]
[Prior art]
In digital magnetic recording / reproduction such as a digital VTR, it is known that a reproduction signal is passed through an equalizer in order to increase the density of magnetic recording and improve an error rate. Further, a configuration is known in which the characteristics of the equalizer are automatically and optimally controlled. In addition, it has been proposed to remove nonlinear distortion using a Viterbi algorithm. As an automatic adjustment method of the equalizer, an error rate of a reproduction signal is obtained, a control signal that minimizes the error rate is generated, and the amplitude characteristic and the phase characteristic of the equalizer are controlled by the control signal. It is considered.
[0003]
In the method of automatically adjusting the characteristics of the equalizer based on the error rate, it is necessary to increase the error rate detection accuracy in order to adjust the characteristics of the equalizer to an optimum one. In other words, the problem is what to use as the evaluation value for detecting the error rate. Normally, in a digital VTR or the like, error correction encoding is performed to prevent errors during recording / reproduction. Therefore, the error rate can be detected from the decoding result of the error correction code, for example, the total number of errors.
[0004]
[Problems to be solved by the invention]
It is considered that the equalization error of the equalizer basically causes a random error. In that sense, it is preferable to control the characteristics of the equalizer based on the number of single symbol errors in a region where the equalization error is relatively small. However, according to the measurements and simulations of the inventor of the present application, as the equalization error increases from a region where the equalization error is relatively small, the continuity error gradually increases, and the continuity error number exceeds the single error number. . That is, in this region, the detection sensitivity of the equalization error can be further increased by using the number of continuity errors as the evaluation value rather than the number of single errors.
[0005]
Further, when the equalization error increases, almost all of the code errors occur (errors occur so that the error cannot be corrected depending on the error correction code), and the change in the increase in the number of continuity errors with the increase in the equalization error becomes slow. Therefore, in this state, even if the decoding result of the error correction code is used as the evaluation value, there is a problem that the equalization error cannot be accurately detected, and the automatic adjustment of the equalizer cannot be performed well. Further, a burst error such as a dropout or a head clog generated by a scratch or the like on a magnetic tape has a problem that an evaluation of an equalization error is erroneously performed in any region.
[0006]
Accordingly, an object of the present invention is to provide a digital signal reproducing apparatus capable of reducing an equalization error by using an optimum evaluation value in accordance with a stage of automatic adjustment when characteristics of an equalizer are automatically adjusted. A circuit and a reproducing method are provided.
[0007]
[Means for Solving the Problems]
The present invention relates to a digital signal reproducing circuit that reproduces error-correction-encoded data and supplies a reproduction signal to a reproduction signal processing circuit including decoding means for error-correction encoding via an equalizer.
By controlling the equalization parameters for the equalizer, control means for automatically controlling the characteristics of the equalizer to an optimal one is provided,
The control unit takes in the number of errors obtained by the decoding unit, and sequentially switches the evaluation value to the number of continuity errors and the number of single errors as the characteristics of the equalizer approach the optimum, based on the switched evaluation value. A digital signal reproducing circuit characterized by controlling an equalization parameter. Further, as described above, the present invention is a digital signal reproducing method characterized by switching an evaluation value and controlling an equalization parameter based on the switched evaluation value.
[0008]
When the equalization error of the equalizer is small, the number of single errors corrected by the error correction code is used as the evaluation value. When the equalization error is large to some extent, the continuity error number is used because the change in the continuity error number with respect to the equalization error is large. As described above, it is possible to switch to use the evaluation value with the highest sensitivity in accordance with the state of the equalization error, and ultimately minimize the equalization error.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention. A reproduction signal reproduced from the magnetic tape 2 by the magnetic head 1 is supplied to the equalizer 4 via the reproduction amplifier 3. The equalizer 4 includes an amplitude equalizer 4a and a phase equalizer 4b. As the equalizer 4, a PR4 (Partial Response class 4), an integral equalizer, or the like can be used. As will be described later, the amplitude-frequency characteristics of the amplitude equalizer 4a and the phase-frequency characteristics of the phase equalizer 4b are controlled by the equalization parameters from the CPU 11. In the case of PR4, the amplitude characteristic is controlled by changing the gain in the frequency band above and below the Nyquist frequency using a phase linear cosine equalizer and correcting the phase distortion of the electromagnetic conversion system. The phase characteristics are changed as follows. When controlling the characteristics of the equalizer 4, it is also possible to reduce the equalization error by controlling at least one of the amplitude and the phase.
[0010]
The output signal of the equalizer 4 is supplied to the A / D converter 5 and the PLL 6. The PLL 6 extracts a clock signal from the reproduced signal, and performs A / D conversion using the extracted clock. The output signal of the A / D converter 5 is supplied to the decoder 7. The decoder 7 outputs binarized reproduced data by comparing the output signal of the A / D converter 5 with a threshold level. The reproduced data from the decoder 7 is supplied to the sync detector 8, and the detector 8 detects the sync added to the data every predetermined length. The reproduced data from the sync detector 8 is supplied to the error correction circuit 9. Data reproduced from the error correction circuit 9 is output to an output terminal 10.
[0011]
The sync detector 8 detects a sync using, for example, that the sync has a specific bit pattern. Various timing signals are formed based on the detected sync, and these timing signals are used for controlling the processing of the reproduction system. At the same time, in the case of a rotary head type recording / reproducing apparatus for a predetermined period, for example, data of the number of syncs detected in a period corresponding to one rotation of the drum provided with the rotary head is supplied to the CPU 11. Further, the CPU 11 generates a C1 error request to the error correction circuit 9 at a constant cycle, and when the error correction circuit 9 receives this request, sends a C1 error correction number to the CPU 11. The C1 error correction number is data of the number of errors corrected by the error correction circuit 9 using the C1 code.
[0012]
The C1 code is one of two error correction codes that are generally used for a product code, and is used for a plurality of symbols in the recording / reproduction direction (a plurality of syncs in a sync block in a digital VTR described later). Refers to the sign. However, in the present invention, the error correction result of the outer code can be used, and it is not necessary to use a product code. In addition, the cycle of the error request generated by the CPU 11 is a cycle corresponding to one rotation of the drum, similarly to the detection cycle of the number of detected syncs. This cycle of the error request is referred to as an evaluation cycle.
[0013]
The number of detected syncs and the number of C1 error corrections given to the CPU 11 are used as evaluation values of the equalization error of the equalizer 4. More specifically, the number of C1 error corrections includes two types of data. One is the number of C1 single errors, which are single symbol single errors, and the other is the total number of C1 errors including continuity errors. As the C1 code, a code that can correct up to three symbol errors, for example, a digital VTR described later is used.
[0014]
The number of C1 single errors is the number of one-symbol errors corrected by the C1 code within the evaluation cycle. In this case, two or more consecutive symbols are in error, and those that can be corrected by the C1 code may be counted as one symbol error. Within the evaluation cycle, the number of sync blocks of one symbol error is the number of C1 single errors.
[0015]
The total number of C1 errors is the total number of errors including one-symbol single error, continuous error, and code error (when the C1 code cannot be corrected due to errors of four or more symbols) within the evaluation value period. Code errors are counted as 4 errors. In the evaluation value cycle, if the number of sync blocks of one symbol error is n1, the number of sync blocks of two symbol errors is n2, the number of sync blocks of three symbol errors is n3, and the number of sync blocks of code error is n4, The total number of C1 errors is obtained as (n1 + 2n2 + 3n3 + 4n4). The number of C1 single errors is n1.
[0016]
As will be described later, the CPU 11 receives these evaluation values, and by hill-climbing control, determines that the amplitude characteristic and / or the phase characteristic of the equalizer 4 is optimal (that is, the error due to the equalization error is minimized). Is determined. This equalization parameter is supplied to the equalizer 4. When controlling the amplitude and the phase, the amplitude equalization parameter and the phase equalization parameter need to be determined. When changing one of the amplitude characteristic and the phase characteristic, the other needs to be fixed. For example, one of the amplitude equalization parameter and the phase equalization parameter is determined first, and then the other is determined. In addition, there is a method for optimally determining the bi-equalization parameters. Here, the determination of the phase equalization parameter and the amplitude equalization parameter will be described without particular distinction for simplicity.
[0017]
The hill-climbing control sets a certain equalization parameter, checks an equalization error (evaluation value) by the equalization parameter before and after the certain equalization parameter, determines a direction in which the equalization parameter is changed, and continues until the equalization error is not reduced , The control for changing the equalization parameter. In this embodiment, three types of evaluation values, ie, the number of detected syncs, the total number of C1 errors, and the number of C1 single errors, are selected and used.
[0018]
The equalization error of the equalizer 4 may be basically considered as a random error. In that sense, in a region where the error is relatively small, the number of C1 single errors is most suitable as the evaluation value. As the equalization error increases from this state, the continuity error gradually increases, and the continuity error number becomes larger than the C1 single error number. Therefore, in this area, the continuity error or the total number of C1 errors including the continuity error is the evaluation value with the highest sensitivity. Further, when the equalization error increases, the code error becomes almost the same and the change in the total number of C1 errors becomes slow. On the other hand, the number of detected syncs that have hardly changed until then rapidly decreases. Therefore, in this region, the number of detected syncs has the highest sensitivity as the evaluation value. As described above, since the evaluation values having high sensitivity differ depending on the equalization state, three types of evaluation values are switched and used.
[0019]
FIG. 2 is a flowchart showing a process of automatic adjustment of the equalizer 4 performed by the CPU 11 according to one embodiment of the present invention. First, in step ST1, the number of detected syncs and the number of C1 errors (including the number of C1 single errors and the total number of C1 errors) are read, for example, for each rotation cycle of the rotating drum. If the read number of detected syncs is smaller than a certain threshold value, a burst error check is performed to determine that a burst error has occurred due to dropout, head clog, or the like (step ST2). If it is determined that a burst error has occurred, the automatic adjustment of the equalization parameter cannot be appropriately performed, so that the process of the automatic adjustment is not performed.
[0020]
If it is determined in step ST2 that the number of detected syncs is equal to or greater than the number of syncs and that no burst error has occurred, the process proceeds to step ST3. In step ST3, a process of selecting an evaluation value is performed. The error state is divided into three levels based on the read number of detected syncs and the number of C1 errors. That is, a first level with very many errors, a third level with very few errors, and a second level intermediate between the first and third levels are identified. For this identification, it is necessary to measure the equalization state in advance and obtain a threshold value for level division.
[0021]
At the first level, the number of detected syncs is used as the evaluation value, at the second level, the total number of C1 errors is used as the evaluation value, and at the third level, the number of single C1 errors is used as the evaluation value. . If the current evaluation value is to be changed, the evaluation value is changed in step ST4, the process returns to step ST1 (reading of the number of detected syncs and the number of C1 errors), and a burst error check is performed in step ST2. If it is determined that the error is not a burst error, the currently read value is determined as the current evaluation value of the equalization parameter (step ST5).
[0022]
In order to determine the hill-climbing direction, the equalization parameter is changed before and after the current equalization parameter (step ST6). The evaluation value is determined for the front equalization parameter in the same manner as described above, and the evaluation value is also determined for the rear equalization parameter. At present, when the front and rear evaluation values are respectively determined, the process moves from step ST5 to step ST7. In this step ST7, based on the magnitude relation of the (three) determined evaluation values, an equalization parameter for reducing the evaluation value from the current value is determined. That is, the direction of the hill-climbing control is determined. Then, the equalization parameters are updated (step ST8).
[0023]
After the update step ST8, processing of step ST9 (reading of the number of detected syncs and C1 error), step ST10 (burst error check), and step ST11 (selection / change of evaluation value) are sequentially performed. Then, in step ST11, when the evaluation value is not selected or changed, the process proceeds to step ST13, and the magnitude of the evaluation value before and after the update is compared.
[0024]
If the evaluation value after the update is smaller than the evaluation value before the update, that is, if the equalization error has decreased, the process returns from step ST13 to step ST8 (update of the equalization parameter), and the parameter is set again. Update in the same direction. This process is repeated until the evaluation value before the update becomes smaller. When the evaluation value before update becomes smaller, an equalization parameter that generates the evaluation value before update is determined as the optimal equalization parameter (step ST14). When the optimum equalization parameter is determined, the hill-climbing control stops.
[0025]
The process of automatic adjustment of the equalizer described above is applied to both determination of the amplitude equalization parameter and the phase equalization parameter. Usually, the automatic adjustment of the equalizer is performed using a standard tape when the reproducing apparatus is shipped. However, this can be performed not only at the time of shipment but also at the time of testing of the device.
[0026]
Next, a rotary head type digital VTR will be described as a specific example of a magnetic reproducing apparatus to which the above-described present invention can be applied. As shown in FIG. 3, diagonal tracks are formed on the tape. T0 and T1 indicate track numbers, and inclined azimuth recording in which the azimuth between adjacent tracks is different is performed. FIG. 4 shows one track. At the track entrance side, a timing block for reliably performing post-recording called ITI (Insert and Track Information) is provided. This is provided in order to accurately position the area when data written in an area thereafter is dubbed and rewritten.
[0027]
In this example, are converted composite digital color video signal is a luminance signal Y, the color difference signals C _R and component signal consisting of C _B, the compressed component signal by DCT conversion and variable-length code, recorded on the magnetic tape by the rotating head You. As a recording method, an SD method (525 lines / 60 Hz, 625 lines / 50 Hz) and an HD method (1125 lines / 60 Hz, 1250 lines / 50 Hz) can be set.
[0028]
As shown in FIG. 5, in the case of the SD system, the number of tracks per frame is set to 10 tracks (in the case of 525 lines / 60 Hz), or as shown in FIG. 6, 12 tracks (525 lines / 60 Hz). Is the case). Although not shown, in the case of the HD system, the number of tracks per frame is twice that of the SD system, that is, 20 tracks (in the case of 1125 lines / 60 Hz) or 24 tracks (in the case of 1250 lines / 50 Hz).
[0029]
As shown in the track format of FIG. 4, after the ITI area, audio data, video data, and subcode data are recorded in the order of head scanning. An area for recording auxiliary data (AUX) for recording additional information is provided in each of the areas for recording video data and audio data. Data other than audio and video data such as recording date and time and recording time can be written in the AUX. The subcode data, AUX, and data recorded in the semiconductor memory built in the cassette have a common format. This form is called a pack structure.
[0030]
The areas where audio data, video data, and subcodes are respectively recorded are called audio sectors, video sectors, and subcode sectors, respectively. Between these sectors, gaps G1, G2, G3 in which no data is recorded are arranged. The audio sector includes a preamble (pre-sync block) PR1, a data portion (14 sync blocks), and a postamble PO1 (post-sync block).
[0031]
The audio sync block is composed of 90 bytes as shown in FIG. The first five bytes are sync and ID data. Audio data (72 bytes) and audio AUX (AAUX) (5 bytes) are included in one sync block. This data is subjected to error correction coding by a product code. That is, encoding of the inner code (referred to as C1 code) is performed on 77 bytes arranged in the horizontal direction. Specifically, a (85,77) Reed-Solomon code is used as a C1 code, and an 8-byte C1 (inner code) parity is added. The direction of the sequence of the C1 code is the data recording / reproducing direction. The 9-byte data arranged in the vertical direction is subjected to outer code (referred to as C2 code) error correction coding. Specifically, a (14,9) Reed-Solomon code is used as a C2 code, and a 5-byte C2 (outer code) parity is added.
[0032]
The video sector includes a preamble (pre-sync block) PR2, a data section (149 sync blocks), and a postamble PO2 (post-sync block). FIG. 8 shows a configuration of a video sector. The structure of the preamble and postamble is the same as that of the audio sector shown in FIG. One SYNC block is composed of 90 bytes in the 149 video sync blocks included in the video sector, similarly to the audio sync block.
[0033]
The first 5 bytes of the sync block are a sync and an ID. The data part is 77 bytes, and the same product code error correction coding as audio data is performed. Specifically, a (85,77) Reed-Solomon code is used as a C1 code, and a (149,138) Reed-Solomon code is used as a C2 code. Then, a C1 (inner code) parity (8 bytes) and a C2 (outer code) parity (11 bytes) are respectively added. Two sync blocks with sync block numbers 19 and 20 and one sync block immediately before the C2 parity are dedicated syncs for video AUX (VAUX), and 77-byte data is used as VAUX data. The central 135 sync block other than the VAUX and C2 parity is an area where video data of the compressed video signal is stored.
[0034]
FIG. 9 shows the configuration of a subcode sector. Unlike the audio sector and the video sector, the preamble and postamble of the subcode sector have no presync and postsync. The subcode sync block is 12 bytes long, and the first 5 bytes are a sync and an ID. The next 5 bytes are a data portion, and only the C1 code is encoded in the data portion. Then, C1 parity (2 bytes) is added. As described above, the product code configuration is not adopted in the subcode. This is because the subcode is mainly for high-speed search, and C2 parity is rarely reproduced. The sync length is also reduced to 12 bytes in order to perform a high-speed search up to about 200 times. There are 12 sub-code sync blocks per track.
[0035]
The number of C1 errors corrected in one embodiment of the present invention is the number of errors corrected by the C1 code in the case of the digital VTR described above, and more specifically, the number of C1 errors corrected for a video sector is used. Since the C1 code is encoded for each block sync, if the number of block syncs for one symbol error is n1 within the evaluation value cycle (for example, one rotation cycle of the drum), the number of C1 single errors is n1. Assuming that the number of block syncs for two symbol errors is n2, the number of block syncs for three symbol errors is n3, and the number of block syncs for code errors is n4, the total number of C1 errors is obtained as (n1 + 2n2 + 3n3 + 4n4). . Even if there are two or three symbol errors, a continuous one in the block sync may be detected as a C1 single error. The number of detected syncs is the number of block syncs extracted within the evaluation value cycle.
[0036]
【The invention's effect】
According to the present invention, when automatically adjusting an equalizer in a digital signal reproducing apparatus, an equalization state is divided into a plurality of levels, and an optimum evaluation value (higher sensitivity to a change in an equalization error) is used for each level. ing. Therefore, the present invention can perform automatic equalization more quickly in time.
[0037]
Further, in a region where the equalization error is small, the evaluation value is greatly affected by disturbance such as a burst error, and the sensitivity of the evaluation value to the equalization error is reduced. However, the present invention uses the number of C1 single errors as the evaluation value. Therefore, the influence of the burst error can be avoided, and finally the equalization error can be minimized.
[0038]
Further, by using the number of detected syncs as the evaluation value, even if the equalization parameter is considerably deviated from the optimum value, it is possible to quickly pull in the optimum equalization parameter without erroneous control.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a flowchart illustrating an example of an automatic equalizer adjustment process according to the present invention.
FIG. 3 is a schematic diagram showing a track pattern of a digital VTR to which the present invention can be applied.
FIG. 4 is a schematic diagram illustrating the configuration of one track of a digital VTR.
FIG. 5 is a schematic diagram showing an example of a track pattern when data of one frame of a digital VTR to which the present invention can be applied is recorded.
FIG. 6 is a schematic diagram showing another example of a track pattern when data of one frame of a digital VTR to which the present invention can be applied is recorded.
FIG. 7 is a schematic diagram illustrating a configuration of one sector of audio data.
FIG. 8 is a schematic diagram illustrating a configuration of one sector of video data.
FIG. 9 is a schematic diagram illustrating a configuration of one sector of subcode data.
[Explanation of symbols]
Reference Signs List 1 magnetic head 2 magnetic tape 4 equalizer 8 sink detector 9 error correction circuit 11 CPU for automatically adjusting equalization parameters

Claims (8)

A digital signal reproducing circuit that reproduces error-correction-encoded data and supplies a reproduction signal to a reproduction signal processing circuit that includes decoding means for error-correction encoding through an equalizer.
By controlling the equalization parameters for the equalizer, control means for automatically controlling the characteristics of the equalizer to an optimal one is provided,
The control means takes in the number of errors obtained by the decoding means, and sequentially switches the evaluation value to the number of continuity errors and the number of single errors as the characteristics of the equalizer approach the optimum. A digital signal reproducing circuit for controlling an equalization parameter based on a value. In claim 1 ,
The reproduction signal is obtained by adding a sync for each data of a predetermined length, and is provided with a sync detecting means for detecting the sync. As the characteristic of the equalizer approaches an optimum, the evaluation value is calculated by the sync detection. A digital signal reproducing circuit for sequentially switching the number of detected syncs from the means, the number of continuity errors, and the number of single errors . In claim 1 ,
A digital signal reproducing circuit wherein an equalization parameter for an equalizer is controlled by hill-climbing control . In claim 1 ,
A digital signal reproducing circuit characterized in that a total error number including a single error number is used as the continuity error number . A digital signal reproducing method for reproducing data subjected to error correction encoding and supplying a reproduction signal to a reproduction signal processing circuit including decoding means for error correction encoding through an equalizer,
A control method for automatically controlling characteristics of the equalizer to an optimal one by controlling an equalization parameter for the equalizer,
The control method captures the number of errors obtained by decoding the error correction code, and sequentially switches the evaluation value to the number of continuity errors and the number of single errors as the characteristics of the equalizer approach the optimum. A digital signal reproducing method, wherein an equalization parameter is controlled based on the obtained evaluation value. In claim 5,
The reproduction signal is obtained by adding a sync for each data of a predetermined length, and is provided with a sync detecting means for detecting the sync. As the characteristic of the equalizer approaches an optimum, the evaluation value is calculated by the sync detection. A digital signal reproducing method characterized by sequentially switching the number of detected syncs from the means, the number of continuity errors, and the number of single errors. In claim 5,
A digital signal reproducing method, wherein an equalization parameter for an equalizer is controlled by hill-climbing control. In claim 5,
A digital signal reproducing method characterized by using a total error number including a single error number as a continuity error number.

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