JP3595565B2 - Semiconductor memory cell circuit and memory cell array - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to improvements in semiconductor memory cell circuits and memory cell arrays.
[0002]
[Prior art]
Conventionally, there is a memory cell circuit of an internal addressing memory as shown in FIG. The memory cell circuit 1 is a memory cell circuit that determines whether a potential applied to the bit line pair 2 or 3 matches a potential held in the bit storage unit 6.
[0003]
Here, the state where the potential of the terminal 12 is high is referred to as “bit storage H”, and the state where the potential of the terminal 13 is high is referred to as “bit storage L”. Further, a state in which the potential of the bit line 2 is high and the potential of the bit line 3 is low is referred to as “bit input H”, and conversely, the potential of the bit line 2 is low and the potential of the bit line 3 is low. The state where the potential is high is referred to as “bit input L”.
[0004]
If the content of the bit storage is different from the content of the bit input, the one of the transistors 9 and 10 connected to the high potential bit line is turned on. Therefore, the gate of the transistor 11 has a high potential, and the transistor 11 is turned on. On the other hand, when the contents of the bit storage match the contents of the bit input, the transistor connected to the bit line which has become a low potential among the transistors 9 and 10 is turned on. Therefore, the gate of the transistor 11 has a low potential, and the transistor 11 is turned off. Since the match line 5 connected to the transistor 11 is charged to a high potential in advance, the potential (contents of bit input) given to the bit line pair 2 and 3 and the potential held in the bit storage unit 6 ( (The contents of the bit storage), the match line 5 is kept at a high potential, while if they do not match, the match line 5 is pulled down to a low potential.
[0005]
FIG. 11 shows a structure of a memory cell array in which the memory cell circuits 1 as shown in FIG. 10 are arranged in an n × m (n and m are both positive integers) lattice. Note that each memory cell circuit 1 is ₁₁ ~ C _nm It is represented by That is, this memory cell array can store n words of m bits.
[0006]
In the memory cell array having the above configuration, the bit line 2 ₁ ・ 3 ₁ , 2 ₂ ・ 3 ₂ , ..., 2 _m ・ 3 _m When a search is made for a word that matches the search data (input data) input in step (1), the following operation is performed. That is, bit line 2 ₁ ・ 3 ₁ ~ 2 _m ・ 3 _m When the search data is input to the memory cell circuits m, _k1 ~ C _km In each of the cases (k = 1 to n), the check of the match / mismatch between the bit storage and the bit input as described in FIG. 10 is performed. When the bit storage matches the bit input in all m memory cell circuits 1, the corresponding match line 5 _k Is held as a high potential and output as a response output.
[0007]
In the above memory cell array, bit line pair 2 ₁ , 3 ₁ Is input to C ₁₁ To C _n1 To the n memory cell circuits 1 up to n. Therefore, all word lines 4 ₁ ~ 4 _n And ground all bit lines 2 ₁ ・ 3 ₁ , 2 ₂ ・ 3 ₂ , ..., 2 _m ・ 3 _m By inputting the inspection data into the ₁ ~ 5 _n It is possible to search for a word that matches the input search data based on the contents of the n-bit response output output from.
[0008]
[Problems to be solved by the invention]
However, the memory cell array using the memory cell circuit of the conventional content addressing memory has the following problems.
[0009]
That is, as described above, when searching for a word that matches the input search data, the bit line 2 ₁ ・ 3 ₁ ~ 2 _m ・ 3 _m , The m-bit search data and n words can be compared in parallel, so there is no problem. Also, match line 5 ₁ ~ 5 _n The match signal S output from each of _k May be one bit representing a match or a mismatch for one word, so that there is no problem even if batch processing is performed outside the memory cell array on the n-bit response output.
[0010]
However, the bit line 2 ₁ ・ 3 ₁ ~ 2 _m ・ 3 _m Represents an m-bit binary number. In the case where the bit storage stored in each of the m memory cell circuits 1 arranged in the row direction and the above-mentioned binary numbers are to be calculated, , Word line 4 _k Must be sequentially read out from the m-bit storage to the outside of the memory cell array, and an operation with a binary number input by an external arithmetic unit must be performed. Therefore, there is a problem in that processing can be performed only sequentially for each word represented by the storage of m bits, which takes time.
[0011]
Therefore, an object of the present invention is to firstly provide a memory cell circuit and a memory cell array capable of executing arithmetic operations on a plurality of stored data simultaneously and in parallel when performing a numerical operation between input data and stored data. Is to do. A second object is to provide a memory cell circuit and a memory cell array capable of storing operation results in a storage circuit simultaneously and in parallel. A third object is to provide a memory cell circuit and a memory cell array that can perform full addition stably at high speed.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, an invention according to claim 1 is a semiconductor memory cell circuit having a static storage circuit, wherein the bit line is connected to a bit line and the storage circuit, and has an operation result output terminal. Performing a 1-bit arithmetic or logical operation on the input data input from the line and the storage data stored in the storage circuit; Include carry information An arithmetic circuit for outputting an arithmetic result from the arithmetic result output terminal is provided.
[0013]
According to a second aspect of the present invention, in the semiconductor memory cell circuit according to the first aspect, the arithmetic circuit has a carry signal input terminal and a carry signal output terminal, and is inputted from the bit line. A 1-bit addition operation is performed based on the input data, the storage data stored in the storage circuit, and the carry signal input from the carry signal input terminal to generate a sum signal and output the calculation result output terminal. And a carry signal generating circuit for generating a carry signal to upper bits based on the input data, the stored data, and the carry signal, and outputting the signal from the carry signal output terminal. It is characterized by having.
[0014]
According to a third aspect of the present invention, there is provided a memory cell array in which the semiconductor memory cell circuits according to the first aspect of the present invention are arranged in a lattice, and a plurality of semiconductor memory cell circuits forming a column of the lattice are connected to the same bit line. It is characterized by being connected.
[0015]
According to a fourth aspect of the present invention, in the memory cell array, the semiconductor memory cell circuits according to the second aspect of the present invention are arranged in a lattice, and a plurality of semiconductor memory cell circuits forming a column of the lattice are connected to the same bit line. On the other hand, the carry signal output terminal of the semiconductor memory cell circuit on the lower bit side and the carry signal input terminal of the semiconductor memory cell circuit on the upper bit side in the semiconductor memory cell circuits adjacent to each other in a row of the lattice. And is connected.
[0016]
According to a fifth aspect of the present invention, in the memory cell array according to the third or fourth aspect of the present invention, the memory cell array is connected to the corresponding operation result output terminal in each of the semiconductor memory cell circuits arranged in a lattice pattern. The semiconductor memory cell circuit further includes a shift register for storing an operation result from the operation circuit.
[0017]
According to a sixth aspect of the present invention, in the semiconductor memory cell circuit according to the first aspect, the storage circuit has a write data input terminal, and the write data input from the write data input terminal. It is characterized in that the stored data can be rewritten by the
[0018]
According to a seventh aspect of the present invention, in the semiconductor memory cell circuit according to the second aspect, the arithmetic circuit has a write data input terminal, and the write data input from the write data input terminal is provided. It is characterized in that the stored data can be rewritten by the
[0019]
According to an eighth aspect of the present invention, in the semiconductor memory cell circuit according to the seventh aspect of the present invention, the arithmetic circuit has a transistor which is turned on / off by a signal from the storage circuit, and includes the transistor All circuit elements Symmetry When the 1-bit addition operation is performed by the arithmetic circuit using the storage data stored in the storage circuit, the data is input from the storage circuit to the arithmetic circuit. Is input to only the gate of the transistor, and the arithmetic circuit operates complementarily to execute the arithmetic operation.
[0020]
According to a ninth aspect of the present invention, the semiconductor memory cell circuits according to the sixth aspect of the present invention are arranged in a lattice, and a plurality of semiconductor memory cell circuits forming a column of the lattice are connected to the same bit line. The operation result output terminal of one semiconductor memory cell circuit and the write data input terminal of the other semiconductor memory cell circuit in the semiconductor memory cell circuits which are adjacent to each other in the lattice column are connected. .
[0021]
According to a tenth aspect of the present invention, the semiconductor memory cell circuits according to the seventh or eighth aspect of the present invention are arranged in a lattice pattern, and a plurality of semiconductor memory cell circuits forming a column of the lattice are connected to the same bit line. In addition, the operation result output terminal of one of the semiconductor memory cell circuits in the semiconductor memory cell circuits adjacent to each other in the lattice column is connected to the write data input terminal of the other semiconductor memory cell circuit. On the other hand, the carry signal output terminal of the semiconductor memory cell circuit on the lower bit side and the carry signal input terminal of the semiconductor memory cell circuit on the upper bit side in the semiconductor memory cell circuits adjacent to each other forming a row of the lattice. Is connected.
[0022]
[Action]
In the invention according to claim 1, when input data is input from the bit line, a 1-bit arithmetic operation or a logical operation of the input data and the storage data stored in the storage circuit is executed by the arithmetic circuit, Include carry information The operation result is output from the operation result output terminal.
[0023]
In the invention according to claim 2, when the input data is input from the bit line, the sum signal generation circuit constituting the arithmetic circuit causes the input data, the storage data stored in the storage circuit, and the carry signal input terminal. 1-bit addition operation is performed on the basis of the carry signal input from, and a sum signal is generated, and the generated sum signal is output from the operation result output terminal. On the other hand, the carry signal generation circuit constituting the arithmetic circuit generates a carry signal for the upper bit based on the input data, the stored data, and the carry signal, and outputs the signal from the carry signal output terminal. .
[0024]
Thus, the full addition of the input data and the stored data is performed.
[0025]
Further, in the invention according to claim 3, input data is input to each bit line commonly connected to a plurality of semiconductor memory cell circuits forming a column of the lattice among the semiconductor memory cell circuits arranged in a lattice. . Then, a plurality of semiconductor memory cell circuits connected to each bit line simultaneously perform an operation of one input data input from the corresponding bit line and a plurality of storage data stored in each semiconductor memory cell circuit. Executed in parallel.
[0026]
According to the fourth aspect of the present invention, when the operation of one input data and a plurality of storage data are performed simultaneously and in parallel in the same manner as the third aspect of the present invention, the carry signal of each semiconductor memory cell circuit is carried out. The generation circuit generates a carry signal for the upper bit based on a carry signal from the semiconductor memory cell circuit located on the lower bit side. Then, the generated carry signal is output from the carry signal output terminal to the semiconductor memory cell circuit located on the upper bit side.
[0027]
In this way, the full addition of one input data and a plurality of storage data is performed simultaneously and in parallel.
[0028]
According to the fifth aspect of the present invention, when the operation of one input data and a plurality of storage data is executed in parallel in the same manner as in the third or fourth aspect of the invention, each semiconductor memory cell circuit The sum signal generated by the arithmetic circuit is sent from the operation result output terminal to the shift register and stored.
[0029]
In this way, the operation for the next input data input to the bit line is continuously executed without sending the operation result obtained by each semiconductor memory cell circuit to the outside each time.
[0030]
In the invention according to claim 6 and claim 7, the storage data to be subjected to the 1-bit operation by the arithmetic circuit is rewritten by inputting write data to the storage circuit from a write data input terminal in advance. This is stored in the storage circuit.
[0031]
Further, in the invention according to claim 8, when a 1-bit addition operation of the input data and the storage data stored in the storage circuit is performed by the calculation circuit, the signal taken into the calculation circuit from the storage circuit is the calculation signal. It is input only to the gates of the transistors that make up the circuit. Therefore, the capacity of the terminal of the storage circuit to be driven when performing the addition operation is small. Therefore, fluctuations in terminal potential of the memory circuit are reduced and external noise does not enter the memory circuit.
[0032]
Further, the arithmetic circuit operates complementarily when performing the addition operation, and the addition operation is performed at high speed.
[0033]
According to the ninth and tenth aspects of the present invention, the operation of one input data and a plurality of storage data is performed in parallel in the same manner as in the third or fourth aspect of the present invention. The operation result is output from the operation result output terminal by the operation circuit of the cell circuit. Then, the operation result from the operation result output terminal is sent to the write data input terminal of the semiconductor memory cell circuit located at the next stage of the semiconductor memory cell circuit, and is sent to the storage circuit of the next-stage semiconductor memory cell circuit. It is memorized.
[0034]
In this way, the operation for the next input data input to the bit line is continuously executed without sending the operation result obtained by each semiconductor memory cell circuit to the outside each time.
[0035]
At this time, when the semiconductor memory cell circuits arranged in a lattice are the semiconductor memory cell circuits of the invention according to claim 8, the arithmetic circuit of each semiconductor memory cell circuit transmits a signal from the storage circuit to this. Input to only the gates of the transistors constituting the arithmetic circuit operates in a complementary manner. Therefore, the addition operation is performed at high speed and stably simultaneously and in parallel.
[0036]
【Example】
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
<First embodiment>
A first object of the present invention is to provide a memory cell circuit and a memory cell array capable of executing operations on a plurality of storage data simultaneously and in parallel when performing a numerical operation between input data and storage data. It is an example to achieve.
[0037]
FIG. 1 is a diagram showing a memory cell circuit of this embodiment. The bit storage unit 26 and the transistors 27, 28, 29, 30 form the same circuit as the circuit including the bit storage unit 6 and the transistors 7, 8, 9, 10 in the conventional memory cell circuit 1 shown in FIG. are doing. In the memory cell circuit 21 according to the present embodiment, a transistor 31 having a gate connected to a terminal 41 of the bit storage unit 26 and a transistor 32 having a gate connected to a terminal 42 are newly added to the above circuit configuration. Transistors 34 and 3 whose gates are commonly connected to input-side carry line 25 5 and , Common to the drain of transistor 31 and transistor 32 33 whose gate is connected to And a transistor 36 having a gate connected to the drains of the transistors 29 and 30 in common. Is added. The drains of the transistors 33 and 36 are commonly connected to an output carry line 37, and the drains of the transistors 34 and 35 are commonly connected to a sum signal line 38.
[0038]
Data is stored and held in the bit storage unit 26. The state where the potential of the terminal 41 is high is represented as “bit storage H”, and the state where the potential of the terminal 42 is high is “bit storage”. The storage L ”will be represented. A state where the potential of the bit line 22 is high and the potential of the bit line 23 is low is referred to as “bit input H”, and conversely, the potential of the bit line 22 is low and the potential of the bit line 23 is low. The state where the potential is high is referred to as “bit input L”.
[0039]
Here, in the conventional memory cell circuit 1 shown in FIG. 10, only the match / mismatch between the bit storage and the bit input is determined based on the potential of the terminal corresponding to the terminal 40 in the present embodiment. On the other hand, in the present embodiment, by providing the transistors 31 and 32, the terminal 39 which is logically relative to the terminal 40 is formed. Then, based on the potentials of these two terminals 39 and 40, a 1-bit sum signal S and a carry signal Co resulting from adding the bit storage, the bit input, and the carry signal Ci from the input side carry line 25 are calculated. It can be generated. The generated sum signal S is output from the sum signal line 38, and the carry signal Co is output from the output side carry line 37.
[0040]
The addition of the bit storage and the bit input is performed as follows.
[0041]
Now, it is assumed that the content of the bit storage is "H" and the content of the bit input is "H". Then, the gate of the transistor 29 becomes low potential and the gate of the transistor 30 becomes high potential, so that the transistor 30 is turned on and the potential of the terminal 40 becomes low potential. Similarly, the gate of the transistor 31 has a high potential and the gate of the transistor 32 has a low potential, so that the transistor 31 conducts and the potential of the terminal 39 becomes high.
[0042]
Here, if there is a carry from the lower bit, the input side carry line 25 becomes high potential and the transistor 3 4 Conduct. On the other hand, since the gate of the transistor 33 connected to the bit line 22 is at a high potential, the transistor 33 is turned on. Therefore, the sum signal line 38 outputs the sum signal S having a high potential. On the other hand, the potential of the output side carry line 37 becomes high, and the carry signal Co is output to the upper bit. On the other hand, when there is no carry from the lower bit, the input carry line 25 has a low potential, and the transistor 35 is turned on. On the other hand, since the gate of the transistor 33 connected to the bit line 22 is at a high potential, the transistor 33 is turned on. Accordingly, the sum signal line 38 outputs the sum signal S having a low potential. On the other hand, the potential of the output side carry line 37 becomes high, and the carry signal Co is output to the upper bit.
[0043]
Hereinafter, the same operation is performed when the above-mentioned bit storage and bit input have other contents, and the sum signal line 38 according to the potential of the input side carry line 25 (ie, the carry signal Ci from the lower bit). In addition, the potential of the output side carry line 37 is set, and the sum signal S and the carry signal Co to the upper bit are output. At this time, the operations performed by the transistors 29 to 32 are the exclusive OR of the bit input and the bit storage and the operation of negation.
[0044]
As described above, in the present embodiment, a storage circuit for storing storage data is configured by the bit storage unit 26 and the transistors 27 and 28, and the exclusive OR of the bit input and the bit storage is formed by the transistors 29 to 32. A calculation unit for calculating the negation is configured, a carry signal generation unit that generates the carry signal Co is configured by the transistors 33 and 36, and a sum signal generation unit that generates the sum signal S is configured by the transistors 34 and 35. . Then, using the result of the operation performed by the operation unit based on the bit storage stored in the storage circuit and the bit input from the bit line pair 22 and 23, the carry signal generation unit generates a digit from the input side carry line 25. A carry signal Co for upper bits is generated based on the carry signal Ci. On the other hand, the sum signal generator generates a sum signal S based on the calculation result and the carry signal Ci.
[0045]
That is, in the case of the present embodiment, the arithmetic unit and the carry signal generating unit constitute the carry signal generating circuit, and the arithmetic unit and the sum signal generating unit constitute the sum signal generating circuit.
[0046]
Therefore, according to the present embodiment, a memory cell circuit having a 1-bit full addition function can be provided.
[0047]
Further, if the memory cell circuits 21 are arranged in a grid, full addition of one input data and a plurality of storage data can be performed simultaneously and in parallel.
[0048]
FIG. 2 shows the structure of a memory cell array in which n × m memory cell circuits 21 as shown in FIG. 1 are arranged in a lattice. Note that each memory cell circuit 21 is ₁₁ ~ C _nm It is represented by
[0049]
In the memory cell array having the above configuration, each of the n memory cell circuits 21 connected to the common bit line pair 22 and 23 has a 1-bit addition function. Further, since the output carry line 37 and the input carry line 25 of the memory cell circuits 21 which are adjacent to each other in the same row are connected, the carry signal generated by the lower bit memory cell circuit 21 is connected. Co is input to the upper bit memory cell circuit 21.
[0050]
Therefore, all the word lines 24 ₁ ~ 24 _n To the bit line 22 ₁ ・ 23 ₁ ~ 22 _m ・ 23 _m , Full addition of one input data and n pieces of storage data stored in the columns of the n sets of memory cell circuits 21 can be performed simultaneously and in parallel.
[0051]
<Second embodiment>
This embodiment is an embodiment for achieving the second object of providing a memory cell circuit and a memory cell array capable of storing operation results in a storage circuit simultaneously and in parallel.
[0052]
FIG. 2 is a diagram illustrating the memory cell array according to the present embodiment. Memory cell circuit C ₁₁ ~ C _nm , Bit line 22 ₁ ・ 23 ₁ ~ 22 _m ・ 23 _m , Word line 24 ₁ ~ 24 _n , Input carry line 25 ₁ ~ 25 _n , Output carry line 37 ₁ ~ 37 _n Operates as described in the first embodiment to operate the bit line 22. ₁ ・ 23 ₁ ~ 22 _m ・ 23 _m , And the total addition of one piece of input data input to n and the n pieces of storage data stored in the n sets of memory cell circuit rows is performed simultaneously and in parallel.
[0053]
A shift register 43 is connected to the sum signal line 38 from each memory cell circuit 21 in the memory cell array of the present embodiment, and the addition result obtained in each memory cell circuit 21 is transferred to the shift register 43 and stored. You. Therefore, each memory cell circuit 21 does not need to transfer the operation result to the processing unit outside the memory cell array every time the addition processing is performed as in the related art, and can continuously execute the addition processing for the next input data.
[0054]
In this embodiment, the control system of the shift register 43 is omitted because it has nothing to do with the essence of the present invention.
[0055]
<Third embodiment>
This embodiment is a modification of the second embodiment, in which the operation result between input data and storage data is stored in another memory cell circuit.
[0056]
FIG. 3 is a diagram showing the memory cell circuit of the present embodiment. The bit storage unit 56 and the transistors 57 and 58 form the same storage circuit as the storage circuit including the bit storage unit 26 and the transistors 27 and 28 in the memory cell circuit 21 shown in FIG. In the memory cell circuit 51 of the present embodiment, bit storage (write data) to be written in the bit storage unit 56 is performed by a transistor 70 having a gate connected to a bit storage write control line 74 from a bit storage write line pair 72, 73. , 71 to the bit storage unit 56.
[0057]
On the other hand, the output of the sum signal from the memory cell circuit 51 to the outside is output via the sum signal line pair 68, 69. Then, in order to generate sum signal S output from sum signal line pair 68 and 69 and its negation S #, transistors 59 and 60 whose gates are commonly connected to input-side carry line 55, and transistors 59 and 60 It has transistors 63 to 66 whose gates are commonly connected to their drains. The drains of the transistors 64 and 65 are commonly connected to a sum signal line 68, while the drains of the transistors 63 and 66 are commonly connected to a sum signal line 69.
[0058]
The drains of the transistors 59 and 60 are connected to the gates of carry transistors 61 and 62 for generating a carry signal. The drains of the transistors 61 and 62 are commonly connected to the output carry line 67.
[0059]
The full addition (for example, the full addition of the bit storage “H” and the bit input “H”) by the memory cell circuit 51 of this embodiment is performed as follows.
[0060]
When writing the bit storage “H” into the bit storage unit 56, the potential of the bit storage write line 72 is set to a high potential while the potential of the bit storage write line 73 is set to a low potential, and the bit storage write control line 74 is set. Is applied with a write control signal.
[0061]
Next, while the potential of the bit line 52 becomes high, the potential of the bit line 53 becomes low and the bit input “H” is input. Here, when there is a carry from the lower bit, the input-side carry line 55 has a high potential, the transistor 60 conducts, and the potential of the terminal 77 has a low potential. Therefore, the transistor 61 is turned on, the potential of the output side carry line 67 becomes high, and a high potential carry signal Co is output to the upper bit. On the other hand, the transistors 65 and 66 are turned on, and the sum signal line 68 outputs a high-potential sum signal S, and the sum signal line 69 outputs a low-potential sum signal S #.
[0062]
On the other hand, when there is no carry from the lower bit, the input-side carry line 55 has a low potential, the transistor 59 conducts, and the potential of the terminal 77 has a high potential. Therefore, the transistor 62 is turned on, the potential of the output side carry line 67 becomes high, and a high potential carry signal Co is output to the upper bit. On the other hand, the transistors 63 and 64 are turned on, and the sum signal line 68 outputs the low-potential sum signal S, and the sum signal line 69 outputs the high-potential sum signal S #.
[0063]
Hereinafter, the same operation is performed when the contents of the bit storage and the contents of the bit input are other contents, and according to the potential of the input side carry line 55 (that is, the carry signal Ci from the lower bit). The potentials of the sum signal lines 68 and 69 and the output carry line 67 are set, and the sum signals S and S # and the carry signal Co to the upper bit are output.
[0064]
As described above, in the present embodiment, the bit storage unit 56 and the transistors 57, 58, 70, and 71 constitute the storage circuit, and the transistors 59 to 62 constitute the carry signal generation circuit. , 60, 63 to 66 constitute the sum signal generation circuit. Then, based on the bit storage stored in the storage circuit, the bit input from the bit line pair 52, 53 and the carry signal Ci from the input carry line 55, the carry signal generation circuit carries the carry to the upper bit. A signal Co is generated. On the other hand, the sum signals S and S # are generated by the sum signal generation circuit.
[0065]
That is, according to the memory cell circuit of the present embodiment, it has a 1-bit full addition function and can output the operation result in the state of the sum signal S that can be stored in the bit storage unit 56 and its negative S #. . Therefore, as will be described in the next embodiment, if the memory cell circuits 51 are arranged in a lattice pattern, full addition of a plurality of bits can be performed simultaneously and in parallel, and the operation result is stored in the next memory cell circuit 51. Can be memorized.
[0066]
<Fourth embodiment>
The present embodiment is an embodiment relating to a memory cell array capable of simultaneously and concurrently performing m-bit full addition using the memory cell circuit in the third embodiment.
[0067]
FIG. 4 shows the structure of a memory cell array in which n × m memory cell circuits 51 as shown in FIG. 3 are arranged in a lattice. Note that each memory cell circuit 51 is ₁₁ ~ C _nm It is represented by
[0068]
In the memory cell array having the above configuration, each of the n memory cell circuits 51 connected to the common bit line pairs 52 and 53 has a 1-bit addition function. Further, since the input carry line 55 and the output carry line 67 of the memory cell circuits 51 adjacent to each other in the same row are connected, the carry signal generated by the lower-order bit memory cell circuit 51 is connected. Co is input to the upper bit memory cell circuit 51. Therefore, according to the present embodiment, it is possible to simultaneously perform the full addition of a single input data with a plurality of storage data in parallel.
[0069]
At this time, a sum signal line pair 68, 69 which is connected to the common bit line pair 52, 53 and is an output terminal pair of the addition result between the adjacent memory cell circuits 51, and a bit storage input terminal pair to be added. Since the bit storage write line pairs 72 and 73 are connected to each other, the addition result in each memory cell circuit 51 is sequentially sent to the bit storage unit 56 of the adjacent memory cell circuit 51 and stored. is there.
[0070]
For example, the memory cell circuit C ₁₁ ~ C _1m Of the memory cell circuit C ₂₁ ~ C _2m It is assumed that no bit storage is given to the bit storage unit 56 and the cell is an unused cell. Then, the bit line pair 52 ₁ , 53 ₁ ~ 52 _m , 53 _m And the memory cell circuit C ₁₁ ~ C _1m Is added to the bit storage stored in the bit storage unit 56 of the memory cell circuit C. ₁₁ ~ C _1m In the memory cell circuit C ₂₁ ~ C _2m Is transferred to and stored in the bit storage unit 56. By doing so, the memory cell circuit C ₁₁ ~ C _1m Can be input without delay, and the addition process for the next bit input can be executed without transferring the addition result to the outside of the memory cell array.
[0071]
Further, as described above, the memory cell circuit C ₁₁ ~ C _1m The operation result executed in the memory cell circuit C ₂₁ ~ C _2m Of the memory cell circuit C ₂₁ ~ C _2m Memory cell circuit C stored in ₁₁ ~ C _1m Memory cell circuit C ₂₁ ~ C _2m This makes it possible to perform an addition process with the next bit input. Thus, the bit line pair 52 ₁ ・ 53 ₁ ~ 52 _m ・ 53 _m Using the operation result of the input data and the stored data, the operation with the next input data can be further performed.
[0072]
In each of the above embodiments, the memory cell circuit having a 1-bit full addition function has been described as an example. However, the present invention is not limited to this, and any other 1-bit arithmetic operation circuit or memory cell circuit having a 1-bit logical operation circuit may be used.
[0073]
<Fifth embodiment>
The present embodiment is an embodiment for achieving a third object of providing a memory cell circuit and a memory cell array capable of performing full addition stably at high speed.
[0074]
The memory cell circuit 51 having the function of the full adder shown in FIG. 3 has a circuit configuration in which a current flows from the bit storage unit 56 of the memory cell circuit 51 to the output carry line 67 through the transistor 61. In some cases, the carry signal Co is output from the bit storage unit 56 through the transistor 61. In the worst case, while the carry signal Co is being output from the bit storage unit 56 to the output side carry line 67 through the transistor 61, the potential of the terminal 75 in the bit storage unit 56 transiently changes to the intermediate potential. At this time, noise may enter the terminal 75 of the bit storage data 56 and destroy the contents of the bit storage stored in the bit storage unit 56.
[0075]
In the memory cell circuit 51 shown in FIG. 3, elements corresponding to the transistors 61 and 62 do not exist on the bit line 53 side, and the capacitance of the memory cell circuit 51 is asymmetrical in the drawing. As a result, the potential of the terminal 75 of the bit storage unit 56 fluctuates greatly greatly, and the time required for the carry signal Co to be output from the output carry line 67 greatly varies, thereby speeding up the addition operation. Disadvantageous.
[0076]
That is, in the memory cell circuit 51 shown in FIG. 3, stable operation and high-speed operation cannot be obtained.
[0077]
FIG. 5 is a diagram showing an example of a memory cell circuit capable of performing a stable operation and a high-speed operation, which overcomes the above-described disadvantages of the memory cell circuit 51 shown in FIG.
[0078]
The storage circuit of the memory cell circuit 81 in the present embodiment is composed of a bit storage section 85 and transistors 86 and 87. Similar to the storage circuit in the memory cell circuit 51 shown in FIG. It is composed of a metal oxide semiconductor (Static Random Access Memory) cell.
[0079]
Next, the configuration of the arithmetic circuit will be described while describing an actual addition operation.
[0080]
The bit storage is input by setting the potential of the bit storage write line pair 88, 89 to a high potential / low potential or a low potential / high potential. Thus, the terminal 90 of the bit storage unit 85 holds the one-bit addend value “A”, while the terminal 91 holds the negative “A #” of the one-bit addend value “A”.
[0081]
On the other hand, as described in the third embodiment, by setting the potential of the bit line pair 82, 83 to the high potential / low potential or the low potential / high potential, the 1-bit addition value "B" is output from the bit line 82. While the bit line 83 receives the negation “B #” of the 1-bit addition value “B”. Then, the operation of the transistors 92 and 93 generates, at the terminal 94, “A # · B + A · B #”, that is, an exclusive OR of the addend A and the addend B. Similarly, the operation of the transistors 95 and 96 at the terminal 97 generates “A · B + A # · B #”, that is, the exclusive OR of the value A and the value B is negated.
[0082]
At this time, the signals representing the addends A and A # stored in the bit storage unit 85 are input only to the gates of the transistors 93 and 95 or 92 and 96. Therefore, the potential fluctuations of the terminals 90 and 91 are reduced, and the operation of the bit memory can be stably operated without breaking the bit memory application due to the intrusion of noise from the outside.
[0083]
In addition, since the transistors 92, 93, 95, and 96 use NMOS, when the potentials of the terminals 94 and 97 become low, they become the same level as the ground level. However, when the potentials of the terminals 94 and 97 are high, a voltage drop occurs due to the threshold voltage of the transistor. When a signal of this potential with a reduced voltage is input to the gates of the transistors 100 to 107 in the next stage, a malfunction may occur depending on the power supply voltage. Therefore, in this embodiment, the potentials of the terminals 94 and 97 are completely raised to the power supply voltage by the PMOS transistors 98 and 99 for pull-up.
[0084]
As described above, the “exclusive OR of the augmented value A and the added value B” obtained by the transistors 92 and 93 is input to the gates of the transistors 100 and 101, and obtained by the transistors 95 and 96. By inputting "Negation of exclusive OR of added value A and added value B" to the gates of transistors 104 and 105, a carry signal from the lower bit input from input-side carry line pairs 108 and 109 is input. Based on Ci and its negated Ci #, a carry signal Co to the upper bit and its negated Co # are generated. The carry signals Co and Co # to the upper bits generated in this manner are transmitted from output carry line pairs 110 and 111 to upper bits using clocked inverters 112 and 113 controlled by control signal CR and its negative CR # as buffers. Output to
[0085]
Here, the clocked inverters 112 and 113 are formed when the level of the signal on the high potential side of the carry signals Co and Co # input to the clocked inverters 112 and 113 becomes lower than the power supply voltage. Since both the PMOS transistor and the NMOS transistor are turned on, a through current flows. In order to prevent this, PMOS transistors 114 and 115 for pull-up are provided immediately before the clocked inverters 112 and 113, and the level of the carry signal on the high potential side dropped by the threshold voltage of each transistor is completely reduced to the power supply voltage. It is raised up to.
[0086]
The sum signal S and its negation S # are generated by the transistors 102 and 103 whose gates are commonly connected to the terminal 94, the transistors 106 and 107 whose gates are commonly connected to the terminal 97, and the inverters 119 and 120. . Writing of the generated sum signals S and S # to the bit storage unit 85 in the memory cell circuit 81 at the next stage controls on / off of the transistors 117 and 118 by the control signal SR from the bit storage write line 116. It is implemented by.
Also in this case, pull-up PMOS transistors 121 and 122 are provided immediately before the inverters 119 and 120, and the level of the sum signal on the high potential side dropped by the threshold voltage of each transistor is completely changed to the power supply voltage. Up to.
[0087]
FIG. 6 shows a timing chart for four clocks in the control signal, input data, and internal data for driving the memory cell circuit 81. 6A shows a control signal WL to the word line 84, FIG. 6B shows input data BL and BL # to the bit line pair 82 and 83, and FIG. 6C shows a control signal WL to the terminals 94 and 97. FIG. 6D shows the "exclusive OR of the augmented value A and the added value B" and "the negation of the exclusive OR of the augmented value A and the added value B". 6E shows the control signals SR and CR # for the bit storage write control line 116, and FIG. 6F shows the stored data A and A # of the bit storage unit 85.
[0088]
As described above, the memory cell circuit 81 according to the present embodiment is configured to be symmetrical left and right so that all operations are performed complementarily. Therefore, the time difference between the fastest operation pattern and the slowest operation pattern is reduced, and as a result, the speed is increased. The signal from the bit storage unit 85 is input only to the gates of the transistors 92, 93, 95, and 96. Therefore, when the transistors 92, 93, 95, and 96 are driven by the above signals, the capacitance to be driven by the terminals 90 and 91 of the bit storage unit 85 is reduced. Therefore, the potential fluctuations of the terminals 90 and 91 are reduced, so that noise can be prevented from entering the bit storage unit 85 from the outside and stable operation can be performed.
[0089]
Further, a circuit for generating an “exclusive OR of the augmented value A and the added value B” and a “negation of an exclusive OR of the augmented value A and the added value B”, a carry signal Co, A pull-up PMOS transistor is provided after the generation circuit for Co # and the generation circuit for the sum signals S and S #. Therefore, the level on the high potential side of each signal input to the final-stage inverters 112, 113, 119, and 120 can be completely raised to the power supply voltage, and the through current can be eliminated. As a result, the memory cell circuit 81 in this embodiment can operate more stably by the buffer action of the inverters 112, 113, 119, and 120.
[0090]
In this embodiment, when the generated sum signals S and S # are written into the bit storage unit 85 in the memory cell circuit 81 in the next stage, the transistors 117 and 118 that are turned on / off by the control signal SR are used. are doing. However, the present invention is not limited to this. As shown in FIG. 7, similarly to the case of carry signals Co and Co # to upper bits, control signal SR from bit storage / write control line 124 is provided. And a pair of clocked inverters 125 and 126 controlled by the negative SR # may be implemented as buffers.
[0091]
<Sixth embodiment>
The present embodiment is an embodiment relating to a memory cell array which can execute m-bit arithmetic / logical operations using the memory cell circuit in the fifth embodiment simultaneously and in parallel.
[0092]
FIG. 8 shows the structure of a memory cell array in which m × n memory cell circuits 81 as shown in FIG. 5 are arranged in a grid pattern. ₁₁ ~ C _mn It is represented by In the figure, reference numeral 127 denotes a carry signal output unit composed of clocked inverters 112 and 113 and pull-up transistors 114 and 115 in each memory cell circuit 81, and is controlled by control signals CR and CR #. Output carry line pair 110, 111 (see FIG. 5) from carry signal output section 127 is connected to input carry line pair 108, 109 (see FIG. 5) in memory cell circuit 81 of the upper bit. ing. Reference numeral 128 denotes a sum signal output unit including the transistors 117 and 118 in each memory cell circuit 81, which is controlled by a control signal SR. The sum signal line pair from the sum signal output unit 128 is connected to a bit storage write line pair 88, 89 (see FIG. 5) in the next-stage memory cell circuit 81.
[0093]
FIG. 9 shows a timing chart of control signals, input data, and internal data for driving the memory cell array. 9A to 9E show the bit line pair 82. ₁ , 83 ₁ 1st memory cell circuit C connected to ₁₁ ~ C _1n Bit line 82 according to ₁ , The control signal of each carry signal output unit 127, the control signal of the sum signal output unit 128, and the data stored in the bit storage unit. 9 (f) to 9 (i) show bit line pairs 82. ₂ , 83 ₂ Memory cell circuits C in the second column connected to ₂₁ ~ C _2n Bit line 82 according to ₂ , The control signal of each carry signal output unit 127, and the data stored in the bit storage unit. 9 (j) and 9 (k) show the bit line pair 82. ₃ , 83 ₃ Memory cell circuits C in the third column connected to ₃₁ ~ C _3n Bit line 82 according to ₃ And the control signal of each carry signal output unit 127.
[0094]
The memory cell array having the above configuration operates according to a timing chart as shown in FIG. 9 and performs full addition collectively for each column in a bit serial manner sequentially from the first column. At that time, the memory cell circuit C _ij (I = 1 to m, j = 1 to n) carry signal Co _ij , Co _ij # Is a control signal CR to the carry signal output unit 127 _j , CR _j #, The upper bit memory cell circuit C _{i + 1j} Is output to On the other hand, the memory cell circuit C _ij Signal S generated by _ij , S _ij # Is a control signal SR to the sum signal output unit 128 _j As a result, the next-stage memory cell circuit C _{ij + 1} Is output to However, in FIG. _j Is common. As a result, the bit line 82 ₁ ~ 82 _m M-bit input data BL ₁ ~ BL _m Is input, the full addition of n m bits can be performed simultaneously and in parallel.
[0095]
At this time, the individual memory cell circuits 81 are configured symmetrically in the figure so that all operations are performed in a complementary manner, and the signal from the bit storage unit 85 is Input is made to only the gates 93, 95 and 96. Therefore, the full addition of n m bits performed simultaneously in parallel is performed at high speed and stably.
In this embodiment, the memory cell circuits C arranged in a lattice pattern ₁₁ ~ C _nm May be the memory cell circuit 123 shown in FIG.
[0096]
【The invention's effect】
As apparent from the above description, in the semiconductor memory cell circuit according to the first aspect of the present invention, the arithmetic circuit performs one-bit arithmetic operation or logical operation on the input data input from the bit line and the storage data stored in the storage circuit. Perform the operation, Include carry information Since the operation result is output from the operation result output terminal, a semiconductor memory cell circuit having a 1-bit operation function can be provided.
[0097]
The arithmetic circuit in the semiconductor memory cell circuit according to the second aspect of the present invention includes a sum signal generation circuit and a carry signal generation circuit, and performs a 1-bit operation based on input data, storage data, and a carry signal. Since the addition operation is performed to generate a sum signal and a carry signal to the upper bits and output from the operation result output terminal and the carry signal output terminal, a semiconductor memory cell circuit having a 1-bit full addition function can be provided. .
[0098]
According to a third aspect of the present invention, there is provided a memory cell array in which the semiconductor memory cell circuits according to the first aspect of the present invention are arranged in a lattice, and a plurality of semiconductor memory cell circuits forming a column of the lattice are connected to the same bit line. Because of the connection, the plurality of semiconductor memory cell circuits connected to the same bit line perform an operation on one input data input from the bit line and a plurality of storage data stored in each semiconductor memory cell circuit. Can be executed in parallel.
[0099]
According to a fourth aspect of the present invention, there is provided a memory cell array in which the semiconductor memory cell circuits according to the second aspect of the present invention are arranged in a grid, and a plurality of semiconductor memory cell circuits forming a column of the grid are connected to the same bit line. On the other hand, since the carry signal output terminal and the carry signal input terminal of the semiconductor memory cell circuits adjacent to each other in a row of the lattice are connected, each semiconductor memory cell circuit is connected to the semiconductor memory cell circuit of the lower bit. And carries out a 1-bit addition operation, and the generated carry signal can be sent to the higher-order semiconductor memory cell circuit.
Therefore, according to the present invention, a full addition operation of one input data input from the bit line and a plurality of storage data stored in each semiconductor memory cell circuit can be performed simultaneously in parallel.
[0100]
In the memory cell array according to the fifth aspect of the present invention, the operation results from the operation circuits of the respective semiconductor memory cell circuits are stored in the shift register. They can be stored in the storage means in parallel.
Therefore, each semiconductor memory cell circuit can continue the operation with the next input data without sending the obtained operation result to the external processing means each time.
[0101]
Further, since the storage circuit in the semiconductor memory cell circuit according to the sixth and seventh aspects of the present invention has a write data input terminal for inputting write data, the storage data to be operated is It is rewritable.
[0102]
Further, in the arithmetic circuit in the semiconductor memory cell circuit according to the invention of claim 8, all the circuit elements including the transistor which is turned on / off by a signal from the storage circuit are used. Symmetry When a 1-bit addition operation is performed using stored data, a signal from the storage circuit is input only to the gate of the transistor. No output is made and the terminal potential of the memory circuit does not become an intermediate potential. Therefore, the memory circuit operates stably without external noise entering the memory circuit.
Furthermore, the arithmetic circuit performs the operation by performing the operation complementarily during the 1-bit addition operation, so that the time difference between the fastest operation and the slowest operation is small, and as a result, the operation speed is increased.
[0103]
In a memory cell array according to a ninth aspect of the present invention, the semiconductor memory cell circuits according to the sixth aspect of the present invention are arranged in a lattice, and a plurality of semiconductor memory cell circuits forming a column of the lattice are arranged on the same bit line. The connection and the connection of the operation result output terminal and the write data input terminal allow the plurality of semiconductor memory cell circuits connected to the same bit line to simultaneously execute the operation of the input data and the plurality of storage data in parallel. And the obtained operation result can be stored in the storage circuit of the next-stage semiconductor memory cell circuit.
Therefore, each semiconductor memory cell circuit can continue the operation with the next input data without sending the obtained operation result to the external processing means each time.
[0104]
According to a tenth aspect of the present invention, there is provided a memory cell array in which the semiconductor memory cell circuits according to the seventh or eighth aspect are arranged in a grid pattern, and a plurality of semiconductor memory cell circuits forming a column of the grid are identical. And the connection between the operation result output terminal and the write data input terminal, and the connection between the carry signal output terminal and the carry signal input terminal of the semiconductor memory cell circuit forming the row of the lattice. Therefore, each semiconductor memory cell circuit can execute the full addition operation of the input data and the storage data simultaneously and in parallel, and store the obtained operation result in the storage circuit of the next-stage semiconductor memory cell circuit.
Therefore, each semiconductor memory cell circuit can continue the full addition operation with the next input data without sending the obtained operation result to the external processing means each time.
[0105]
At this time, when the semiconductor memory cell circuits arranged in a lattice are the semiconductor memory cell circuits of the invention according to claim 8, the signal from the storage circuit in each semiconductor memory cell circuit constitutes an arithmetic circuit. Only the gates of the transistors are input, and the arithmetic circuit operates complementarily to perform the addition operation when performing a 1-bit addition operation, so that the memory cell array can perform full addition at high speed and stably.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory cell circuit of the present invention.
FIG. 2 is a diagram showing a memory cell array using the memory cell circuit shown in FIG.
FIG. 3 is a circuit diagram of a memory cell circuit different from FIG.
FIG. 4 is a diagram showing a memory cell array using the memory cell circuit shown in FIG.
FIG. 5 is a circuit diagram of a memory cell circuit different from FIGS. 1 and 3;
6 is a timing chart of various signals for driving the memory cell circuit shown in FIG.
FIG. 7 is a diagram showing a modification of the memory cell circuit shown in FIG. 5;
8 is a diagram showing a memory cell array using the memory cell circuit shown in FIG.
9 is a timing chart of various signals for driving the memory cell array shown in FIG.
FIG. 10 is a circuit diagram of a conventional memory cell circuit.
11 is a diagram showing a memory cell array using the memory cell circuit shown in FIG.
[Explanation of symbols]
21, 51, 81, 123 ... memory cell circuit,
22, 23, 52, 53, 82, 83 ... bit lines,
24, 54, 84 ... word lines,
25, 55, 108, 109 ... input side carry line,
26, 56, 85 ... bit storage unit,
37, 67, 110, 111 ... output carry line,
38, 68, 69 ... sum signal line, 43 ... shift register,
72, 73, 88, 89 ... bit storage write lines,
74, 116, 124 ... bit storage write control lines,
112, 113, 125, 126 ... clocked inverter,
127: carry signal output unit; 128: sum signal output unit.

Claims (10)

In a semiconductor memory cell circuit having a static storage circuit,
A 1-bit arithmetic or logical operation between input data input from the bit line and storage data stored in the storage circuit, having a calculation result output terminal connected to the bit line and the storage circuit; And an arithmetic circuit for outputting an arithmetic result including carry information from the arithmetic result output terminal. 2. The semiconductor memory cell circuit according to claim 1,
The arithmetic circuit has a carry signal input terminal and a carry signal output terminal,
A 1-bit addition operation is performed based on the input data input from the bit line, the storage data stored in the storage circuit, and the carry signal input from the carry signal input terminal to generate a sum signal. A sum signal generation circuit that outputs the result from the operation result output terminal;
A semiconductor memory cell comprising: a carry signal generation circuit that generates a carry signal to an upper bit based on the input data, the stored data, and the carry signal, and outputs the carry signal from the carry signal output terminal. circuit. 2. A memory cell array, wherein the semiconductor memory cell circuits according to claim 1 are arranged in a lattice, and a plurality of semiconductor memory cell circuits forming a column of the lattice are connected to the same bit line. The semiconductor memory cell circuits according to claim 2 are arranged in a grid pattern, and a plurality of semiconductor memory cell circuits forming a column of the grid are connected to the same bit line, while being adjacent to each other in a row of the grid. A memory cell array in which the carry signal output terminal of the semiconductor memory cell circuit on the lower bit side is connected to the carry signal input terminal of the semiconductor memory cell circuit on the upper bit side. In the memory cell array according to claim 3 or 4,
A shift register connected to the operation result output terminal of each of the semiconductor memory cell circuits arranged in the lattice pattern and storing the operation result from the operation circuit in the corresponding semiconductor memory cell circuit. Memory cell array. 2. The semiconductor memory cell circuit according to claim 1,
A semiconductor memory cell circuit, wherein the storage circuit has a write data input terminal, and the storage data can be rewritten by write data input from the write data input terminal. 3. The semiconductor memory cell circuit according to claim 2,
A semiconductor memory cell circuit, wherein the arithmetic circuit has a write data input terminal, and the stored data can be rewritten by write data input from the write data input terminal. The semiconductor memory cell circuit according to claim 7,
The arithmetic circuit has a transistor that is turned on / off by a signal from the storage circuit, and all circuit elements including the transistor are arranged to operate symmetrically and complementarily,
When a 1-bit addition operation is performed by the arithmetic circuit using the storage data stored in the storage circuit, a signal input from the storage circuit to the arithmetic circuit is input only to the gate of the transistor, and A semiconductor memory cell circuit wherein the circuits operate complementarily to execute an operation. 7. The semiconductor memory cell circuits according to claim 6, which are arranged in a grid pattern, a plurality of semiconductor memory cell circuits forming a row of the grid are connected to the same bit line, and are adjacent to each other in a row of the grid. A memory cell array, wherein the operation result output terminal of one semiconductor memory cell circuit in the semiconductor memory cell circuit is connected to the write data input terminal of the other semiconductor memory cell circuit. The semiconductor memory cell circuits according to claim 7 or 8 are arranged in a grid pattern,
A plurality of semiconductor memory cell circuits forming the lattice column are connected to the same bit line, and the operation result output terminal of one of the semiconductor memory cell circuits in the adjacent semiconductor memory cells forming the lattice column is connected. And the write data input terminal of the other semiconductor memory cell circuit.
The carry signal output terminal of the semiconductor memory cell circuit on the lower bit side and the carry signal input terminal of the semiconductor memory cell circuit on the upper bit side in the semiconductor memory cell circuits which are adjacent to each other in a row of the lattice are connected. A memory cell array, comprising:

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