JP3595591B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
[Industrial applications]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit that can reduce a timing margin caused by an internal signal when testing burn-in is performed at the time of manufacturing a semiconductor chip.
[0002]
[Prior art]
Conventionally, when testing a manufactured semiconductor chip, the semiconductor chip is usually tested at 27 ° C. to 80 ° C., whereas burn-in is performed under a bad condition of 120 ° C. However, burn-in has been performed without monitoring the burn-in state, which is the operating state of the semiconductor chip during the burn-in.
[0003]
Therefore, a testing burn-in apparatus for testing a semiconductor chip while monitoring the burn-in state of the semiconductor chip has recently been used. FIG. 8 is a schematic block diagram showing an example of a signal flow mainly concerning a row decoder of a conventional dynamic operation type RAM (hereinafter referred to as DRAM). Here, in FIG. 8, a conventional example will be described by taking as an example the operation of each unit and the flow of signals when a row decoder performs a write operation on a memory cell. When a column decoder performs a write operation on a memory cell, the operation principle of the column decoder is the same as that of a row decoder except that the column decoder performs a write operation on the memory cell via a sense amplifier. I do.
[0004]
In FIG. 8, signals designating addresses input from a plurality of address input terminals A0 to An (n is 0 and a positive integer) are respectively input to an address buffer 1, and the address buffer 1 includes a column decoder 2 and a row decoder. A signal indicating the word line and the bit line of the address of the memory cell 4 is output from the signal input from each of the address input terminals A0 to An to the decoder 3, and the row decoder 3 is input from the RX generation circuit 6, When an enable signal RX (hereinafter, referred to as an RX signal), which is a signal for activating the word line of the memory cell 4, is input, the word line indicated by the signal input from the address buffer 1 is activated. The column decoder 2 outputs a signal indicating a bit line to the memory cell 4 via the sense amplifier 5.
[0005]
An RAS buffer 7 for outputting an RXT signal, which is a signal for activating the RX signal, is connected to the RX generation circuit 6. The RAS buffer 7 has a RAS buffer 7 for activating the RXT signal. An RXTF generating circuit 8 for outputting an RXTF signal, which is a signal, is connected. The RXTF generating circuit 8 is a signal necessary for activating the RXTF signal, and outputs a word line block selection signal XA (hereinafter referred to as XA signal) for selecting a word line block to be activated in the memory cell 4. The row address buffer 9 is connected to the address buffer 1.
[0006]
Data relating to the row of the address in the memory cell 4 from the signal input to the address buffer 1 is input from the address buffer 1 to the row address buffer 9, and the XA signal is output from the row address buffer 9 to the RXTF generation circuit 7. The RXTF generating circuit 7 outputs the RXTF signal to the RAS buffer 7. The RAS buffer 7 receives, via an external input terminal / exRAS, a row address strobe signal (hereinafter, referred to as an / exRAS signal) sent from an external circuit at a timing at which a write operation to the memory cell 4 is to be started, and the RXTF The RXT signal is output to the RX generation circuit 6 from the signal.
[0007]
Further, a write signal (hereinafter, referred to as an / exWE signal) for setting a memory cell at a specified address for a write operation is switched from “H” to “L” via an external input terminal / exWE, and the external circuit WE outputs the signal. Input to the buffer 10. When the input / exWE signal switches from “H” to “L”, the WE buffer 10 changes the WDE signal, which is a control signal for the input buffer 11, to “permit writing to the input buffer 11”. In addition to switching from "L" to "H" and outputting, the DBR signal which is a control signal for the output buffer 12 is switched from "H" to "L" and output in order to inhibit the output buffer 12 from reading.
[0008]
The input buffer 11 to which the write enable signal has been input outputs signal information for writing to the memory cell 4 from the external circuit to the sense amplifier 5 via the external input / output terminals DQ1 to DQm (m is a natural number). Information is written to a memory cell at an address specified by a signal from the column decoder 2 and the row decoder 3.
[0009]
Here, the process of outputting the RXT signal of the RAS buffer 7 will be described in more detail. FIG. 9 is a circuit example of the RAS buffer 7. In FIG. 9, the RAS buffer 7 includes four inverter circuits 50, 51, 52, 53 and one NAND circuit 54, and the inverter circuits 50, 51, 52 are the same. The input of the inverter circuit 50 is connected to the / exRAS terminal, and the / exRAS signal input from the / exRAS terminal is output from the output of the inverter circuit 52 via the inverter circuit 51 to the NAND circuit. The signal is input to one of the input terminals 54 and is referred to as an intRAS signal. An RXTF generating circuit 8 is connected to the other input of the NAND circuit 54, and receives the RXTF signal. The NAND circuit 54 is connected to the RX generation circuit 6 via the inverter circuit 53.
[0010]
[Problems to be solved by the invention]
FIG. 10A is a timing chart of the circuit shown in FIG. 9, and FIG. 10B is a testing burn-in device used for performing the manufacturing inspection of the DRAM shown in FIG. FIG. 10 is a timing chart for the circuit shown in FIG. By comparing FIGS. 10A and 10B, it can be seen that the waveform of FIG. 10B is rounded with respect to FIG. 10A. As described above, since the above-described testing burn-in apparatus measures a large number of semiconductor devices at the same time, the difference in the length of wiring on a device board on which the semiconductor devices are mounted, the capacity of each semiconductor device, and the skew of the testing burn-in apparatus, For example, if the skew is 1 ns in the current burn-in device, the skew is 10 ns to 20 ns in the testing burn-in device, so that when measuring the operating characteristics of the semiconductor chip, the waveform showing the characteristics becomes blunt.
[0011]
As described above, when the testing burn-in device is used, the operating characteristics of the semiconductor chip are measured, for example, by a write enable signal / exWE (hereinafter, referred to as an / exWE signal) externally via an external input terminal / exWE in FIG. For example, when the leading time tRWL of the write command with respect to the / exRAS signal is measured, the waveform indicating the characteristic becomes rounded, and the tRWL increases due to the threshold value of the device of the semiconductor integrated circuit in the semiconductor chip. However, when testing a timing margin of an internal signal in a semiconductor chip, there is a problem that it is not possible to measure an accurate operating characteristic by reducing the margin.
[0012]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has been made in consideration of a timing margin due to an internal signal of a semiconductor chip in a test of the semiconductor chip performed by using a testing burn-in apparatus when manufacturing the semiconductor chip. And a semiconductor integrated circuit capable of accurately measuring operating characteristics.
[0013]
[Means for Solving the Problems]
The present invention includes a first internal signal output means for generating and outputting a first internal signal for changing a binary state in response to a binary state change of an external input signal from a first external terminal, A timing margin between an external input signal from a second external terminal and the external input signal from the first external terminal when the first internal signal output from the first internal signal output means is within a predetermined timing margin; In the semiconductor integrated circuit of the semiconductor chip, the second internal signal for changing the binary state of the input signal from the second external terminal is changed to generate the first internal signal output means. When a predetermined signal is input to a second internal signal output means for outputting a predetermined signal to a third external terminal including at least one external terminal, the binary state is changed and the predetermined signal is input. 3rd shown It generates a strobe signal is to provide a semiconductor integrated circuit having a third internal signal output means for outputting to said first internal signal outputting means.
[0014]
In the invention described in claim 2 of the present application, the first internal signal output means in claim 1 selects a timing at which the state change of the first internal signal is performed in response to the state change of the second internal signal. Means for performing the operation.
[0015]
In the invention according to claim 3 of the present application, the means for selecting timing according to claim 2 is configured by connecting a fuse in series to a plurality of delay circuits set with different delay times. The second internal signal is input to the input of each of the delay circuits, and the fuse of an unselected delay circuit is cut to select a desired delay circuit. A timing for changing the state of the first internal signal in response to a state change of the second external signal input from the second external terminal via the selected delay circuit is set.
[0016]
In the invention according to claim 4 of the present application, the third internal signal of the first aspect identifies, at each of the external terminals of the third external terminal, an external terminal to which a predetermined signal is input. It is an identification signal.
[0017]
In the invention according to claim 5 of the present application, the first internal signal output means according to claim 4 corresponds to the identification signal, wherein the first internal signal output means responds to the identification signal by changing the state of the second internal signal. And means for varying the timing of changing the state of (1).
[0018]
In the invention according to claim 6 of the present application, the means for varying the timing of claim 5 includes a plurality of delay circuits set at different delay times, and the second internal signal is: While being input to the input of each of the delay circuits, the first internal signal output means selects each of the delay circuits in accordance with the identification signal, and receives an input from a second external terminal via the selected delay circuit. The timing of changing the state of the first internal signal in response to the state change of the second external signal is changed.
[0019]
In the invention described in claim 7 of the present application, the first internal signal output means of claim 6 includes switching means in each of the delay circuits as means for selecting each of the delay circuits. By switching the switching means corresponding to the signal, a delay circuit corresponding to the identification signal is selected.
[0020]
[Action]
The semiconductor integrated circuit according to claim 1, wherein the second internal signal output means changes the binary state of the signal input from the second external terminal when the binary state is changed. An internal signal is generated and output to the first internal signal output means. When a predetermined signal is input to a third external terminal including at least one external terminal by the third internal signal output means, a binary state is generated. To generate a third internal signal indicating that the predetermined signal has been input, and output the generated signal to the first internal signal output means. Even when the state of the first external signal is not changed, the third internal signal is output. The first internal signal output means responds to a change in the state of the second internal signal output from the second internal signal output means and a change in the state of the third internal signal output from the third internal signal output means. Generates and outputs a binary first internal signal that changes state That.
[0021]
In the semiconductor integrated circuit according to a second aspect of the present invention, the first internal signal output means according to the first aspect is configured such that the first internal signal output means receives the first internal signal with respect to a change in the state of the second internal signal by the means for selecting the timing. Select the timing to change the signal state.
[0022]
According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the second internal signal is input to an input of each of the delay circuits and is not selected. By cutting the fuse and selecting a desired delay circuit, the first internal signal output means is connected to the second external signal input from the second external terminal via the selected delay circuit. The timing for changing the state of the first internal signal in response to the state change is set.
[0023]
According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the third internal signal causes the first internal signal output means to output a predetermined signal at each of the third external terminals. Identifies the external terminal to which the signal has been input.
[0024]
In the semiconductor integrated circuit according to the fifth aspect of the present invention, the first internal signal output means according to the fourth aspect corresponds to the third internal signal which is the identification signal by means for changing timing. Thus, the timing at which the state of the first internal signal is changed in response to the state change of the second internal signal is varied.
[0025]
In the semiconductor integrated circuit according to a sixth aspect of the present invention, the first internal signal output unit is configured to change the timing of each of the delay circuits in accordance with the identification signal. And changes the timing of changing the state of the first internal signal with respect to the state change of the second external signal input from the second external terminal via the selected delay circuit.
[0026]
In a semiconductor integrated circuit according to a seventh aspect of the present invention, the first internal signal output means according to the sixth aspect includes switching means in each of the delay circuits as means for selecting each of the delay circuits, The switching means selects a delay circuit corresponding to the identification signal.
[0027]
【Example】
Next, the present invention will be described in detail based on embodiments shown in the drawings.
Embodiment 1 FIG.
FIG. 1 is a schematic block diagram showing an example of a signal flow mainly concerning a row decoder of a DRAM using a semiconductor integrated circuit according to a first embodiment of the present invention. First, FIG. An outline of the operation of each unit and the flow of signals when a write operation is performed on a memory cell for a row decoder of a DRAM using the circuit of the first embodiment will be described. In FIG. 1, the same components as those in FIG. 8 of the conventional example are denoted by the same reference numerals. Here, only the differences from FIG. 8 will be described, and when a column decoder performs a write operation on a memory cell, The operation principle of the column decoder is the same as that of the row decoder except that the column decoder performs a write operation on the memory cell via the sense amplifier, and thus the description is omitted.
[0028]
1 differs from FIG. 8 in that an address key circuit 30A that outputs an ADK signal indicating that a signal designating an address has been input to the address buffer 1 from any of the address input terminals A0 to An is provided. The buffer further receives the ADK signal and the WDE signal output from the WE buffer 10, and outputs the / exRAS signal as an external signal, the RXTF signal input from the RXTF generation circuit 8, the ADK signal and the WDE signal. Since the binary state of the RXT signal is switched and output, the RAS buffer 7A is used, and accordingly, the DRAM 20 is set to 20A.
[0029]
In FIG. 1, signals designating addresses inputted from address input terminals A0 to An are respectively inputted to an address buffer 1. The address buffer 1 supplies the above signals to a column decoder 2, a row decoder 3 and an address key circuit 30A. A signal indicating the word line and bit line of the address of the memory cell 4 is output from the signals input from the address input terminals A0 to An. The address key circuit 30A detects whether a signal designating an address is inputted to the address buffer 1 from the signal inputted from the address buffer 1, and detects that a signal designating an address is inputted to the address buffer 1. During this time, the ADK signal is switched from "L" to "H" and output to the RAS buffer 7A.
[0030]
Also, when the / exWE signal for setting the memory cell at the designated address to the write operation is switched from "H" to "L" via the external input terminal / exWE and input to the WE buffer 10 from the external circuit. When the / exWE signal is input, the WE buffer 10 switches the WDE signal, which is a control signal for the input buffer 11, from "L" to "H" in order to permit writing to the input buffer 11. , RAS buffer 7A and input buffer 11. The RAS buffer 7A changes the binary state of the RXT signal from the ADK signal and the WDE signal in addition to the / exRAS signal and the RXTF signal, and outputs it to the RX generation circuit 6.
[0031]
Here, the process of outputting the RXT signal of the RAS buffer 7A will be described in more detail. FIG. 2 is a diagram showing a circuit example of the RAS buffer 7A. In FIG. 2, the same components as those in FIG. 9 are denoted by the same reference numerals. The RAS buffer 7A includes an inverter circuit 53 and a NAND circuit 54 in FIG. 9, six inverter circuits 60, 61, 62, 64, 66, and 67, two NAND circuits 63 and 65, and a p-channel MOS transistor ( A pMOS transistor (hereinafter referred to as a pMOS transistor) 68 and an n-channel MOS transistor (hereinafter referred to as an nMOS transistor) 69 are provided.
[0032]
The inverter circuits 60, 61, and 62 are connected in series in the same direction to form a delay circuit, and the input of the inverter circuit 60 is connected to the / exRAS terminal, and the input of the inverter circuit 60 from the date input terminal / exRAS. Is input from the output of the inverter circuit 60 to the input of the inverter circuit 62 via the inverter circuit 61, and further from the output of the inverter circuit 62 to one input of the NAND circuit 63.
[0033]
The connection between the output of the inverter circuit 60 and the input of the inverter circuit 61 is connected to the drain of the nMOS transistor 69, and the source of the nMOS transistor 69 is connected to the other input of the NAND circuit 63. The connection portion is further connected to the source of the pMOS transistor 68. The gate of the nMOS transistor 69 is connected to the gate of the pMOS transistor 68, and the drain of the pMOS transistor 68 is grounded.
[0034]
The inverter circuits 66 and 67 are connected in series in the same direction to form a delay circuit. The input of the inverter circuit 66 is connected to the output of the NAND circuit 65, and the output of the inverter circuit 67 is connected to the pMOS transistor 68 and The nMOS transistor 69 is connected to a connection between both gates. One input of the NAND circuit 65 is connected to the WE buffer 10, and receives the WDE signal. The other input of the NAND circuit 65 is connected to the address key circuit 30A, and receives the ADK signal.
[0035]
An output of the NAND circuit 63 is connected to one input of the NAND circuit 54 via an inverter circuit 64. A signal output from the output of the inverter circuit 64 and input to one input of the NAND circuit 54 is referred to as an intRAS signal. I do. The other input of the NAND circuit 54 is connected to the RXTF generation circuit 8 and receives the RXTF signal. The NAND circuit 54 is connected to the RX generation circuit 6 via an inverter circuit 53, and the output of the inverter circuit 53 outputs the RXT signal to the RX generation circuit 6.
[0036]
In the first embodiment, the external input terminal / exRAS is the first external terminal, the / exRAS signal is the first external signal, and the inverter circuits 60, 61, 62, 64, 66, 67, NAND in the RAS buffer 7A. The circuits 63 and 65, the pMOS transistor 68, and the nMOS transistor 69 form a first internal signal output unit, and the intRAS signal forms a first internal signal. The external input terminal / exWE is a second external terminal, the / exWE signal is a second external signal, the WE buffer 10 is a second internal signal output means, and the WDE signal is a second internal signal. Further, the address input terminals A0 to An form a third external terminal, the address key circuit 30A forms a third internal signal output means, and the ADK signal forms a third internal signal. Strictly speaking, the third internal signal output means includes an address buffer 1.
[0037]
FIG. 3 is a timing chart of the circuit shown in FIG. 2, and the operation of the circuit shown in FIG. 2 will be described with reference to FIGS. 2 and 3, when the / exWE signal is "H", the WDE signal output from the WE buffer 10 is "L", and no signal for specifying an address is input to the address buffer 1, and the address key When the ADK signal output from the circuit 30A is “L”, a “H” signal is input to both gates of the pMOS transistor 68 and the nMOS transistor 69, the pMOS transistor 68 is turned off, and the nMOS transistor 69 Turn on.
[0038]
As a result, the output of the inverter circuit 60 is connected to the other input of the NAND circuit 63 via the drain and source of the nMOS transistor 69. When the / exRAS signal is “H”, one input of the NAND circuit 63 is connected to the other input. An “L” signal is input from the inverter circuit 62 to the other input of the NAND circuit 63 via the nMOS transistor 69 to the other input of the NAND circuit 63, and the intRAS signal becomes “L”.
[0039]
At this time, when the / exRAS signal switches from "H" to "L", the intRAS signal switches from "L" to "H", and further, a signal designating an address is input to the address buffer 1, and When the RXTF signal output from the RXTF circuit 8 switches from “L” to “H”, both inputs of the NAND circuit 54 change to “H”, and the RXT signal switches to “H”, and the RX generation circuit 6 Is output to In the above, when a signal designating an address is input to the address buffer 1, the ADK signal switches from "L" to "H".
[0040]
Here, when the / exWE signal switches from "H" to "L" in order to switch to the write operation, the WE buffer 10 switches the WDE signal from "L" to "H" and outputs the same, and outputs the NAND signal of the RAS buffer 7A. The signal of “H” is input to the input of the circuit 65 and both inputs of the NAND circuit 65, and the output of the inverter circuit 67 switches from “H” to “L”. As a result, the nMOS transistor 69 is turned off and the pMOS transistor 68 is turned on, the other input of the NAND circuit 63 is grounded via the pMOS transistor 68 and becomes “L”, and the intRAS signal changes from “H” to “L”. The RXT signal switches from “H” to “L”.
[0041]
As described above, according to the circuit of the first embodiment of the present invention, the binary state of the intRAS signal in the RAS buffer has been switched by the conventional switching of the binary state of the / exRAS signal. On the other hand, a WDE signal formed from an externally input / exWE signal and an ADK signal indicating that an external signal designating an address has been input to the address buffer 1 from any of the address input terminals A0 to An. Thus, the binary state of the intRAS signal can be switched without switching the binary state of the / exRAS signal, and the intRAS signal falls before the rise of the external signal / exRAS signal. Can be.
[0042]
From this, when performing a test using the testing burn-in device, the rising point of the / exRAS signal can be made earlier to the falling point of the intRAS signal. And tRWL can be measured under severe conditions.
[0043]
In the first embodiment, a means for selecting and setting the delay time of the delay circuit formed by the serial circuit of the inverter circuits 66 and 67 of the RAS buffer 7A may be provided. A modification of the first embodiment of the present invention is provided by providing a means for selecting and setting the delay time of the delay circuit in the internal signal output means. FIG. 4 is a diagram showing a circuit example of the RAS buffer 7A showing a modification of the first embodiment. In FIG. 4, the same components as those in FIGS. 9 and 2 are denoted by the same reference numerals, and only the differences from FIG. 2 will be described.
[0044]
The difference between FIG. 4 and FIG. 2 is that, in addition to the series circuit of the inverter circuits 66 and 67 and the NAND circuit 65 of FIG. The input of the delay circuit is connected to the output of the corresponding NAND circuit, and the non-connection side of each fuse in each series circuit in which a fuse made of a polybit line or the like is connected to the output of each delay circuit, Further, one input of each NAND circuit is connected to each other, and the other input of each NAND circuit is also connected to each other to connect each series circuit of the NAND circuit, the delay circuit and the fuse in parallel, and to output the parallel circuit. Is connected to a connection portion connecting the gates of the pMOS transistor 68 and the nMOS transistor 69.
[0045]
In FIG. 4, in a series circuit in which the input of the inverter circuit 66 is connected to the output of the NAND circuit 65 and the input of the inverter circuit 67 is connected to the output of the inverter circuit 66, one end of the fuse 95 is connected to the output of the inverter circuit 67. To form a first series circuit. The output of the NAND circuit 80 is the input of the inverter circuit 81, the output of the inverter circuit 81 is the input of the inverter circuit 82, the output of the inverter circuit 82 is the input of the inverter circuit 83, and the output of the inverter circuit 83 is the inverter circuit. One end of a fuse 96 is further connected to the output of the inverter circuit 84 in the series circuit to which the input of the inverter 84 is connected to form a second series circuit.
[0046]
The input of the inverter circuit 86 is used as the output of the NAND circuit 85, the input of the inverter circuit 87 is used as the output of the inverter circuit 86, the input of the inverter circuit 88 is used as the output of the inverter circuit 87, and the output of the inverter circuit 88 is used as the output. In a series circuit in which the input of the inverter circuit 89 is connected to the input of the inverter circuit 90 to the output of the inverter circuit 89, and the input of the inverter circuit 91 is connected to the output of the inverter circuit 90, the output of the inverter circuit 91 is connected to the fuse 97. One end is connected to form a third series circuit.
[0047]
The other ends of the fuses 95, 96, and 97 of the first, second, and third series circuits are respectively connected, and the connection is connected to a connection connecting both gates of the pMOS transistor 68 and the nMOS transistor 69. You. One input of each of the NAND circuits 65, 80, and 85 is connected to each other, and the WE buffer 10 is connected to the connection, and the WDE signal is input. Further, the other inputs of the NAND circuits 65, 80, and 85 are also connected, and the connection portion is connected to the address key circuit 30A to input the ADK signal.
[0048]
In the above configuration, if a signal passes through the inverter circuit, a time delay occurs in the signal. If the signal passes through the one-stage inverter circuit and the delay time of the signal is 1 ns, the two-stage inverter circuit A passing signal can be delayed by 2 ns, and a four-stage inverter circuit can delay a passing signal by 4 ns. Similarly, a six-stage inverter circuit can delay a passing signal by 6 ns. For this reason, the first, second, and third series circuits each include a delay circuit that generates a different delay time.
[0049]
Here, each of the fuses 90, 91, and 92 is made of a polybit line, and among the first, second, and third series circuits, fuses other than the selected series circuit are cut by a laser cutter when the DRAM is manufactured. To select the delay time. The timing chart of the circuit shown in FIG. 4 is different from the timing chart shown in FIG. 3 in that the intRAS signal changes from “H” to “L” after the WDE signal switches from “L” to “H”. Since the switching time is the same except that it changes depending on the delay time of the delay circuit selected by cutting the fuse, the description is omitted.
[0050]
As described above, if the selected serial circuit, for example, the second serial circuit is selected by cutting the fuse of the unselected serial circuit with a laser cutter, the timing chart of FIG. 3 in the first embodiment is shown. A delay circuit formed by a series circuit of inverter circuits 81, 82, 83, 84 from the time when the WDE signal switches from "L" to "H" to the time when the intRAS signal switches from "H" to "L". , Ie, the timing for switching the / exRAS signal from “L” to “H” is determined, so that the timing margin of the tRWL can be adjusted.
[0051]
In the modification of the first embodiment, a case has been described as an example in which three types of delay circuits having different delay times are provided. However, the present invention is not limited to this. Are connected in series, any number of inverter circuits may be used as long as the number of inverter circuits is positive and different, and the first internal signal output means forms delay circuits of the same number as the number of inverter circuits. A series circuit can be provided.
[0052]
Embodiment 2. FIG.
Next, FIG. 5 is a schematic block diagram showing an example of a signal flow mainly concerning a row decoder of a DRAM using a semiconductor integrated circuit according to a second embodiment of the present invention. The operation of each section and the flow of signals when a write operation is performed on a memory cell to a row decoder of a DRAM using the circuit of the second embodiment will be described. In FIG. 5, the same components as those in FIGS. 1 and 8 are denoted by the same reference numerals, and only the differences from FIG. 1 will be described. When the write operation is performed by the column decoder, the operation principle is the same as that of the row decoder except that the column decoder performs the write operation on the memory cell via the sense amplifier, and therefore the description is omitted.
[0053]
5 differs from FIG. 1 in that the address key circuit 30A in FIG. 1 outputs an ADK signal indicating that a signal designating an address has been input to the address buffer 1 from any of the address input terminals A0 to An. On the other hand, the address key circuit 30B of FIG. 5 uses the address corresponding to the address input terminals A0 to An to indicate which of the address input terminals A0 to An has received the signal designating the address. Key signals ADK0 to ADKn (hereinafter referred to as ADK0 to ADKn signals) are to be output to the RAS buffer. Accordingly, the RAS buffer 7A in FIG. 1 is replaced with 7B, and the DRAM 20A in FIG. 1 is replaced with 20B.
[0054]
FIG. 6 is a diagram showing a circuit example of the RAS buffer 7B when there are three address input terminals A0 to A2. In FIG. 6, for comparison with the modification of the first embodiment, an example in which three types of delay circuits having different delay times are provided as in FIG. 4 will be described as an example. In the second embodiment, since the number of address key signals ADK0 to ADKn is equal to the number of the address input terminals A0 to An shown in FIG. 5, the first internal signal output means is provided for the address input terminals A0 to An. It is possible to provide a series circuit that forms as many delay circuits as the number of the inverter circuits by the number of terminals. 6, the same components as those in FIGS. 2 and 4 are denoted by the same reference numerals, and only the differences from FIG. 4 will be described.
[0055]
6 is different from FIG. 4 in that nMOS transistors 100, 101, and 102 are used instead of the fuses 95 to 97 in FIG. 4, and one of the nMOS transistors 100 to 102 is turned on to select a delay circuit. And that the delay time can be varied.
6, in the series circuit in which the input of the inverter circuit 66 is connected to the output of the NAND circuit 65 and the input of the inverter circuit 67 is connected to the output of the inverter circuit 66, the drain of the nMOS transistor 100 is further connected to the output of the inverter circuit 67. The gate of the nMOS transistor 100 is connected to one input of the NAND circuit 65, and the connection is connected to the address key circuit 30B to form a first series circuit.
[0056]
Next, in a series circuit in which inverter circuits 81, 82, 83 and 84 are connected in series to the output of the NAND circuit 80 in the same direction, the output of the inverter circuit 84 is further connected to the drain of the nMOS transistor 101. Is connected to one input of the NAND circuit 80, and the connection is connected to the address key circuit 30B to form a second series circuit.
[0057]
In a series circuit in which inverter circuits 86, 87, 88, 89, 90 and 91 are connected in series to the output of a NAND circuit 85 in the same direction, the output of the inverter circuit 91 is further connected to the drain of an nMOS transistor 102. The gate of 102 is connected to one input of the NAND circuit 85, and the connection is connected to the address key circuit 30B to form a third series circuit.
[0058]
The sources of the nMOS transistors 100 to 102 of the first, second and third series circuits are respectively connected, and the connection is connected to a connection connecting both gates of the pMOS transistor 68 and the nMOS transistor 69. The other inputs of the NAND circuits 65, 80, and 85 are connected to each other, and the WE buffer 10 is connected to the connection to input the WDE signal.
[0059]
At the connection between the input of the NAND circuit 65 and the gate of the nMOS transistor 100, an ADK0 signal indicating whether or not a signal designating an address has been input to the address input terminal A0 from the address key circuit 30B is provided. , At the connection between the input of the NAND circuit 80 and the gate of the nMOS transistor 101, an ADK1 signal indicating whether or not a signal designating an address has been input from the address key circuit 30B to the address input terminal A1. An ADK2 signal indicating whether or not a signal designating an address has been input to the address input terminal A2 from the address key circuit 30B is input to a connection between the input of the NAND circuit 85 and the gate of the nMOS transistor 102. ing.
[0060]
Further, the source of the nMOS transistor 103 is connected to a connection portion between one input of the NAND circuit 63 and the source of the pMOS transistor 68 and the source of the nMOS transistor 69, and the drain of the nMOS transistor 103 is connected to the + terminal of the DC power supply + DC It is connected to the. The gate of the nMOS transistor 103 is connected to the output of the three-input NOR circuit 104. The three inputs of the three-input NOR circuit 104 are connected to the address key circuit 30B, and the signals ADK0, ADK1 and ADK2. Signals are input corresponding to the three inputs of the three-input NOR circuit 104, respectively.
[0061]
FIG. 7 is a timing chart of the circuit shown in FIG. 6, and the operation of the circuit shown in FIG. 6 will be described with reference to FIGS. In FIGS. 6 and 7, when the / exWE signal is "H", the WDE signal output from the WE buffer 10 is "L", a signal for specifying an address is not input to the address buffer 1, and the address key When the signals ADK0 to ADK2 output from the circuit 30B are “L”, the nMOS transistors 100 to 102 are turned off. At this time, the output of the three-input NOR circuit 104 is turned “H” and the nMOS transistor 103 is turned on.
[0062]
From this, the signal of “H” is input to the input of the NAND circuit 63 in which the source of the pMOS transistor 68 and the source of the nMOS transistor 69 are connected via the nMOS transistor 103 from + DC which is the + terminal of the DC power supply. When the / exRAS signal is "H", a "L" signal is input from the inverter circuit 62 to the other input of the NAND circuit 63, and the intRAS signal becomes "L".
[0063]
At this time, when the / exRAS signal switches from "H" to "L", the intRAS signal switches from "L" to "H", and further, for example, a signal for specifying an address from the address input terminal A0 to the address buffer 1 Is input, the RXTF signal output from the RXTF circuit 8 switches from “L” to “H”, both inputs of the NAND circuit 54 change to “H”, and the RXT signal switched to “H” The signal is output to RX generation circuit 6.
[0064]
In the above, when a signal designating an address is input from the address input terminal A0 to the address buffer 1, the ADK0 signal switches from "L" to "H", the nMOS transistor 100 is turned on, and the three-input NOR The output of the circuit 104 becomes “L”, the nMOS transistor 103 is turned off, and the connection between the gates of the pMOS transistor 68 and the nMOS transistor 69 is connected to the inverter circuit via the drain and source of the nMOS transistor 100. 67 outputs are connected. At this time, the ADK1 signal and the ADK2 signal remain at “L”.
[0065]
Here, when the / exWE signal switches from "H" to "L" in order to switch to the write operation, the WE buffer 10 switches the WDE signal from "L" to "H" and outputs the same. 7B is input to the inputs of the NAND circuits 65, 80, and 85, and the ADK0 signal of “H” is input to one input of the NAND circuit 65 as described above. The signal “H” is input, and the output of the inverter circuit 67 switches from “H” to “L”. As a result, the nMOS transistor 69 is turned off and the pMOS transistor 68 is turned on, the other input of the NAND circuit 63 is grounded via the pMOS transistor 68 and becomes “L”, and the intRAS signal changes from “H” to “L”. The RXT signal switches from “H” to “L”.
[0066]
As described above, according to the circuit of the second embodiment of the present invention, the binary state of the intRAS signal of the RAS buffer has been switched by switching the binary state of the / exRAS signal. On the other hand, when a WDE signal formed from an externally input / exWE signal and an external signal designating an address to the address buffer 1 from any of the address input terminals A0 to An are input, an address key circuit is provided. It is possible to switch the binary state of the intRAS signal from the ADK0 to ADKn signals output from 30B corresponding to the address input terminal to which the signal is input, without switching the binary state of the / exRAS signal. it can.
[0067]
Further, since delay circuits having different delay times are selected in accordance with the signals ADK0 to ADKn, the WDE depends on which of the address input terminals A0 to An receives the signal designating the address. The delay time from when the signal switches from “L” to “H” to when the intRAS signal switches from “H” to “L” can be changed, that is, the timing margin of the tRWL can be adjusted. it can.
[0068]
In the above embodiment, the DRAM has been described as an example. However, the present invention can be applied to a case where a timing margin of a signal of an internal circuit in a semiconductor integrated circuit is checked. As described above, the present invention can be variously modified and is not limited to the above-described embodiments. It goes without saying that the scope of the present invention should be determined by the appended claims.
[0069]
【The invention's effect】
As is apparent from the above description, in the present invention, when a testing burn-in is performed using a testing burn-in device or an inaccurate test device in a semiconductor integrated circuit in a semiconductor chip, an input from the device is performed. Even when the test signal is distorted and the internal signal related to the test signal is distorted in the internal signal of the semiconductor integrated circuit, the test can be performed with a small timing margin of the internal signal. Operating characteristics can be measured. From this, it is possible to perform a test under severe conditions with a small timing margin, so that it is not necessary to determine a defective product as a non-defective product when manufacturing a semiconductor chip, and to determine a non-defective product as a defective product. Without having to do it.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing an example of a signal flow mainly concerning a row decoder of a DRAM using a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a circuit example of a RAS buffer 7A shown in FIG.
FIG. 3 is a timing chart of the circuit shown in FIG. 2;
FIG. 4 is a diagram showing another example of the circuit of the RAS buffer 7A shown in FIG.
FIG. 5 is a schematic block diagram showing an example of a signal flow mainly related to a row decoder of a DRAM using a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 6 is a diagram illustrating a circuit example of the RAS buffer 7B illustrated in FIG. 5;
FIG. 7 is a timing chart of the circuit shown in FIG. 6;
FIG. 8 is a schematic block diagram showing an example of a signal flow mainly related to a row decoder of a conventional DRAM.
9 is a diagram showing a circuit example of the RAS buffer 7 shown in FIG.
FIG. 10 is a timing chart of the circuit shown in FIG. 9;
[Explanation of symbols]
1 address buffer, 3 row decoder, 4 memory cells, 6 RX generation circuit, 7, 7A, 7B RAS buffer, 8 RXTF generation circuit, 9 address buffer, 10 WE buffer, 20, 20A, 20B DRAM, 30A, 30B address key Circuit, / exRAS, / exWE, A0-An External input terminal

Claims (7)

First internal signal output means for generating and outputting a first internal signal for changing a binary state in response to a state change of a binary first external signal input from a first external terminal;
When the first internal signal output from the first internal signal output means is within a predetermined timing margin, the binary second external signal input from the second external terminal and the binary external signal input from the first external terminal are input. In a semiconductor integrated circuit of a semiconductor chip in which a timing margin with a first external signal is checked,
A second internal signal output means for generating a second internal signal for changing a binary state when the state of the second external signal input from the second external terminal is changed and outputting the second internal signal to the first internal signal output means;
When a predetermined signal is input to a third external terminal including at least one external terminal, a binary state is changed to generate a third internal signal indicating that the predetermined signal has been input, and the third internal signal is generated. And third internal signal output means for outputting to the internal signal output means.
The first internal signal output means further comprises: a state change of the second internal signal output from the second internal signal output means even when there is no change in the state of the first external signal; A semiconductor integrated circuit, wherein the state of the first internal signal is changed and output in response to a change in the state of a third internal signal output from an output means. 2. The semiconductor integrated circuit according to claim 1, wherein said first internal signal output means includes means for selecting a timing at which a state change of said first internal signal is performed in response to a state change of said second internal signal. Semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the means for selecting the timing comprises connecting a fuse in series to each of a plurality of delay circuits set to different delay times, and wherein the second internal signal is: By cutting the fuse of an unselected delay circuit which is input to the input of each of the delay circuits and selecting a desired delay circuit, the first internal signal output means is passed through the selected delay circuit via the selected delay circuit. A timing for changing the state of the first internal signal in response to a state change of the second external signal input from the second external terminal. 2. The semiconductor integrated circuit according to claim 1, wherein the third internal signal is an identification signal for identifying an external terminal to which a predetermined signal has been input, at each of the external terminals of the third external terminal. Semiconductor integrated circuit. 5. The semiconductor integrated circuit according to claim 4, wherein the first internal signal output means changes a timing of changing a state of the first internal signal in response to a change of a state of the second internal signal in response to the identification signal. A semiconductor integrated circuit, comprising: 6. The semiconductor integrated circuit according to claim 5, wherein the means for changing the timing comprises a plurality of delay circuits set at different delay times, and wherein the second internal signal is input to an input of each of the delay circuits. And the first internal signal output means selects each of the delay circuits in response to the identification signal, and outputs the state of the second external signal input from the second external terminal via the selected delay circuit. A semiconductor integrated circuit, wherein a timing of changing a state of a first internal signal in response to a change is changed. 7. The semiconductor integrated circuit according to claim 6, wherein said first internal signal output means includes switching means for each delay circuit as means for selecting each delay circuit, and switches the switching means corresponding to said identification signal. Thereby selecting a delay circuit corresponding to the identification signal.

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