JP3596402B2 - Access right arbitration device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an access right arbitration for arbitrating an access right to an auxiliary data processing device among data processing devices when a plurality of data processing devices share the auxiliary data processing device.StopAbout the installation.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a multiprocessor system in which a plurality of processors (data processing devices) are operated in parallel, an expensive coprocessor (auxiliary data processing device) such as a memory for storing data commonly used by the processors or a floating point arithmetic unit is used. ) May be shared. Hereinafter, such a peripheral device is referred to as a shared peripheral device.
[0003]
In this case, the right to access the shared peripheral device is exclusively given to any one of the processors so that the data is not destroyed by a plurality of processors simultaneously writing to the same shared peripheral device. Arbitration for granting is required.
In such arbitration of access rights, an access request to a shared peripheral device is received from each processor, and when an access request conflicts, a processor to which the access right is given is selected, and an operation is performed on another conflicting processor. An arbitration circuit that sends a hold signal for instructing a halt is provided to perform arbitration by hardware, and a flag that indicates the use state of the shared peripheral device is provided, and each processor has a flag so that access conflict does not occur. A method is known in which arbitration is performed by software by performing an inquiry and an operation of the information.
[0004]
By the way, when a coprocessor (for example, a floating-point arithmetic unit or the like) is used as a shared peripheral device, a series of processes such as writing of data to be operated by the processor, execution of arithmetic processing by the coprocessor, and reading of operation result data by the processor are necessary. It becomes. If new data is written from another processor to the coprocessor during this series of processing, the processing sequence may be disrupted and a correct processing result may not be obtained.
[0005]
However, in the hardware arbitration method, it is general that each time the processor terminates the access to the shared peripheral device once, the access right is once released and the access request is made again. That is, when a coprocessor is used as a shared peripheral device, a mechanism for occupying a single processor with an access right until a series of operations is completed is required.
[0006]
To realize this, for example, JP-A-5-289987 discloses that, when an access request is continuously issued from the same processor within a certain priority period after an access is completed, the processor is continuously given to that processor. An apparatus for controlling access right is disclosed.
[0007]
[Problems to be solved by the invention]
However, in such a device, if the operation time in the coprocessor, that is, the time interval after writing of the data to be operated and before reading of the operation result data becomes long, the above-mentioned priority period is exceeded. There is a problem that the access right of the coprocessor may be transferred to another processor before the operation result data is read.
[0008]
Such a situation can be prevented by making the priority period sufficiently long. However, in this device, in order to transfer the access right to another processor, it is necessary to always wait for the priority period, so that the longer the priority period, the more wasteful waiting time increases. Also, increasing the priority period increases the possibility that a single processor will occupy the access right even when continuous access is not required, and increases the time that another competing processor is held in the hold state. Therefore, there is a problem that the processing efficiency of the entire system is reduced.
[0009]
Further, when such an access right is occupied, it becomes an obstacle when executing a process that requires a real-time property, such as a process that needs to return a response within a certain period of time, and the responsiveness of the process is reduced. There was also the problem of doing.
On the other hand, in the case of arbitration by software, it is possible to cause a specific processor to occupy the access right only for an arbitrary period by operating only the flag. Since processing for the operation is required, there is a problem that the processing efficiency is reduced accordingly.
[0010]
In order to solve the above problems, the present invention can efficiently use an auxiliary data processing device shared by a plurality of data processing devices, and the access right to the auxiliary data processing device is more than necessary by one data processing device. Access rights that will not be occupied for a long timeStopThe purpose is to provide a device.
[0011]
[Means for Solving the Problems]
The access right arbitration according to claim 1, which is an invention for achieving the above object.apparatusThenData processing equipmentFor auxiliary data processorTo write input dataStart sending write signalOr start of reading read signal to read output dataSet for the auxiliary data processor.To read the output dataThe processing request released by the completion of the transmission of the read signal isProcessing request setting means set for each data processing deviceI do. AndBy this processing request setting meansWhen setting a processing request, if a processing request of another data processing device has already been set,Hold setting means,The data processing device corresponding to the newly set processing request is set to the hold state.
[0012]
Furthermore,Hold release means,A non-hold state among the data processing devices to which the processing request is set is regarded as a first data processing device having an access right to the auxiliary data processing device, and the processing request of the first data processing device is released. At this time, if there is another processing request, one of them is selected, and the second data processing device corresponding to the selected processing request is released from the hold state. As a result, the right to access the auxiliary data processing device is transferred from the first data processing device to the second data processing device.
[0013]
In other words, the access right arbitration of the present inventionapparatusThen, a processing request is set by a write signal to the auxiliary data processing device, and the data processing device to which the access right has been granted based on the processing request is transmitted to the data processing device until the transmission of the read signal from the data processing device is completed. During this period, the access right to the auxiliary data processing device is unconditionally occupied.
[0014]
Therefore, according to the present invention, during a series of operations necessary to obtain a normal processing result from the auxiliary data processing device (started by writing input data and finished by reading output data), other data processing is performed. New input data is not written into the auxiliary data processing device by the device, and each data processing device using the auxiliary data processing device obtains a highly reliable processing result (output data) from the auxiliary data processing device. be able to.
[0015]
Further, according to the present invention, it is not necessary to provide a priority period as in the conventional device for determining whether or not to perform continuous access, and the access right is arbitrated in a minimum necessary time. The auxiliary data processing device can be efficiently used for the data processing device. Moreover, since the access right is released each time a series of operations on the auxiliary data processing device is completed, it is possible to reliably prevent a specific data processing device from occupying the access right more than necessary.
[0016]
Further, in the present invention, the arbitration of the access right is performed based on the write signal and the read signal from each data processing device, and it is not necessary to use any other arbitration-dedicated signal., DressThe configuration can be simplified.
[0018]
In the present invention,Processing requestConfigurationMeans areNot only does it start sending write signals,The processing request is set even when the transmission of the read signal starts.ToAccess right arbitration is also performed for a single read signal without a write signal.I can.
[0019]
In addition, the present inventionIn the access right arbitration device, when the processing request of the first data processing device is set within a predetermined period after the cancellation of the processing request of the first data processing device, the hold release prohibiting means is The access right is continuously given to the first data processing device by prohibiting the operation of the hold release means.
[0020]
Therefore, according to the access right arbitration device of the present invention, by sending the write signal to the auxiliary data processing device within a certain period after sending the read signal to the auxiliary data processing device, the auxiliary data The processing device can be used continuously. Note that, unlike the priority period of the conventional device, the fixed period according to the present invention can be set independently of the operation of the auxiliary data processing device. The processing efficiency does not significantly deteriorate.
[0021]
Further, in the access right arbitrating device of the present invention, the first continuous access restricting means includes a data processing device (first data processing device) having an access right and a data processing device designated by the device designating device. If not, the operation of the hold release prohibiting means is prohibited.
In other words, according to the access right arbitration device of the present invention, it is possible to continuously grant access rights to the auxiliary data processing device only to the data processing device designated by the device designation means. By designating a data processing device that is executing (eg, real-time processing) or the like by the device designating unit, the execution state of each data processing device as viewed from the entire system can be optimized.
[0022]
Next, in the access right arbitrating device according to the second aspect, when the access right is continuously given to the first data processing device, the second continuous access restricting means counts the number of times of continuous access. When the value reaches the upper limit, the operation of the hold release prohibition means is prohibited.
[0023]
In other words, according to the access right arbitrating device of the present invention, the number of times the access right is continuously granted to the same data processing device is limited to the above-mentioned upper limit number, so that the access right is occupied more than necessary. Can be reliably prevented.
[0024]
The specified contents of the device specifying means are defined in the claims.3As described, the configuration may be such that it can be changed by the designation changing means. Specifically, for example,4As described, it may be changed periodically according to a preset switching order, or may be arbitrarily changed according to an external setting or an instruction from a predetermined data processing device.
[0025]
In particular, when periodically changing according to a preset switching order, a claim may be made.5As described, the switching order may be changed by the order changing means. In this case, the access right to the auxiliary data processing device can be allocated to each data processing device at various ratios, and the processing state of each data processing device can be flexibly changed according to the time. .
[0026]
Next, claim6The access right arbitrating device described above includes a request priority setting unit that sets the priority of the processing request, and the hold release unit is specified by the request priority specifying unit when there are a plurality of target processing requests. The data processing device corresponding to the processing request having the highest priority is released from the hold state.
[0027]
Therefore, in the access right arbitration device of the present invention, the data processing device to which the access right should be given next can be determined according to the priority of the processing request. Note that the request priority designation means is, for example, a7As described, the priority may be set in accordance with the order in which the processing requests are generated. In addition, a fixed priority may be set corresponding to the data processing device that is the source of the processing request.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a multiprocessor system to which the present invention is applied.
[0031]
As shown in FIG. 1, the multiprocessor system includes a pair of processors P0 and P1 as data processing devices that operate independently, a coprocessor CP as an auxiliary data processing device shared by the processors P0 and P1, and a processor. An arbitration device 10 that performs arbitration for giving one of P0 and P1 an access right to the coprocessor CP is provided. The arbitrating device 10 is connected to each processor Pi via an individual bus BSi (i = 0, 1) and is connected to a coprocessor CP via a common bus BSC.
[0032]
The individual bus BSi includes a data bus for inputting / outputting data DTi to / from each processor Pi, and various controls for receiving an address signal ADi, a read signal RDi, and a write signal WRi supplied by each processor Pi. The common bus BSC supplies an address signal ADC, a read signal RDC, and a write signal WRC to the data bus for inputting and outputting data DBC to and from the coprocessor CP. And various control signal lines.
[0033]
Further, the arbitration device 10 outputs a hold signal HOLDi for instructing each processor Pi to stop the operation, and inputs an operation mode setting signal MOD for designating the operation mode of the arbitration device 10 from outside. It is configured as follows.
In the present embodiment, when the contention of an access request to the coprocessor CP occurs, the priority designation indicating whether or not the continuous grant of the access right to the same processor Pi is permitted is set for each processor by the operation mode setting signal MOD. In addition, when the priority designation is set, a continuous limit designation indicating whether to limit the number of consecutive grants of the access right is set, and when the access right is further limited, an upper limit count Cmax is set.
[0034]
Here, FIG. 2 is a block diagram illustrating an internal configuration of the arbitration device 10.
As shown in FIG. 2, the arbitrating device 10 includes a processing request generation circuit 12 that generates processing request signals RQ0 and RQ1 from read signals RD0 and RD1 and write signals WR0 and WR1, a processing request signal RQ0 and RQ1, and an operation mode setting. Based on the signal MOD, a processor to which an access right is to be given is selected, and a selection signal SL0. A selection circuit 14 for generating SL1, a hold control circuit 16 for setting and releasing the hold signals HOLD0 and HOLD1 based on the processing request signals RQ0 and RQ1 and the selection signals SL0 and SL1, and an individual bus according to the selection signals SL0 and SL1. A bus switching circuit 18 is provided for switching the connection state between BS0 and BS1 and the common bus BSC, that is, for performing switching. However, in the present embodiment, each of the signals WRi, RDi, RQi, SLi, and HOLDi is assumed to be active at a high level and inactive at a low level.
[0035]
Then, the processing request generation circuit 12 generates an OR circuit ORi for generating a logical sum of the write signal WRi and the read signal RDi, an inverting circuit INVi for inverting the read signal RDi, and a rising edge of the output of the OR circuit ORi. An SR flip-flop circuit SFi that is set and reset at the rising edge of the output of the inverting circuit INVi.
[0036]
That is, the processing request generation circuit 12 becomes high level at the transmission start timing (rising edge) of the write signal WRi or the read signal RDi and ends transmission timing of the read signal RDi (falling edge), corresponding to each processor Pi. ), A processing request signal RQi which becomes low level is generated.
[0037]
Next, the hold control circuit 16 latches the signal level of the processing request signal RQ1 at the rising edge of the processing request signal RQ0, and connects the flip-flop circuit FF0 connected so as to be reset when the selection signal SL0 is active; A flip-flop circuit FF1 is connected to latch the signal level of the processing request signal RQ0 at the rising edge of the processing request signal RQ1 and to be reset when the selection signal SL1 is active. Then, the output of each of these flip-flop circuits FFi is output as a hold signal HOLDi.
[0038]
That is, when the processing request signal RQi is set (becomes active) and the other processing request signal RQj (j ≠ i) is not set when the processing request signal RQi is set (becomes active), the hold signal HOLDi is held as inactive. If the other processing request signal RQj has already been set, it changes to active. This causes the processor Pi to transition to the hold state. The hold signal HOLDi set to active returns to inactive when the selection signal SLi becomes active. As a result, the processor Pi is released from the hold state.
[0039]
Further, the bus switching circuit 18 operates to connect the individual bus BSi and the common bus BSC when the selection signal SLi is active, and its configuration is well-known. Is omitted.
Next, the selection circuit 14 will be described. However, since the selection circuit 14 can be easily realized by various methods by a combination of logic circuits, only the operation thereof will be described here in the flowcharts shown in FIGS. 3 and 4 and the timing diagrams shown in FIGS. It is explained along.
[0040]
First, a process that is started when the processor Pi sends out the write signal WRi or the read signal RDi to change the processing request signal RQi to active will be described.
When this processing is started, as shown in FIG. 3, first, in S110, the other processing request signal RQj (that is, j = 1 if i = 0, j = 0 if i = 1) is set. If the other processing request signal RQj is not set, that is, if the other processing request signal RQj is not competing with the other processor Pj, the process proceeds to S120 and the selection signal SLi is activated (▲ in FIG. 5). 1 ▼).
[0041]
By the selection signal SLi, the individual bus BSi and the common bus BSC are connected in the bus switching circuit 18, and the flip-flop circuit FFi of the hold control circuit 16 is held in the reset state (that is, the hold signal HOLDi is inactive). As a result, the access right to the coprocessor CP is given to the processor Pi.
[0042]
In the following S130, the count value C indicating the number of consecutive grants of the access right to the same processor is set to 1, and this processing ends.
On the other hand, if it is determined in S110 that the other processing request signal RQj has been set, that is, if the processor Pj has already sent the write signal WRj or the read signal RDj to the coprocessor CP, Then, the present process is terminated (see (2) in FIG. 5). However, at this time, the hold signal HOLDi becomes active by the operation of the hold control circuit 16, and the processor Pi transits to the hold state.
[0043]
Next, a description will be given of a process which is started when the processing request signal RQi is released (changed to inactive) due to the inactive state of the read signal RDi sent from the processor Pi having the access right.
When this process is started, as shown in FIG. 4, first, in S210, it is determined whether or not the processor Pi corresponding to the canceled process request signal RQi is designated by the mode setting signal MOD as having priority. If not, the process proceeds to S260, where the selection signal SLi is set to inactive (see (3) and (4) in FIG. 5).
[0044]
Thereby, the connection between the individual bus BSi and the common bus BSC in the bus switching circuit 18 is released, and the access right to the coprocessor CP given to the processor Pi is released.
In subsequent S270, it is determined whether or not another processing request signal RQj is set, that is, whether or not there is a processor Pj that has been in a hold state in competition with the processor Pi. If it has not been set (see (4) in FIG. 5), this processing is terminated as it is.
[0045]
On the other hand, if another processing request signal RQj is set, the flow shifts to S280, where the selection signal SLj is activated (see (3) in FIG. 5).
As a result, in the bus switching circuit 18, the individual bus BSj and the common bus BSC are connected, and the operation of the hold control circuit 16 changes the hold signal HOLDj to inactive, thereby releasing the processor Pj from the hold state. Thereby, the access right to the coprocessor CP is given to the processor Pj.
[0046]
In S290, similarly to S130, the count value C indicating the number of continuous accesses is set to 1, and the process ends.
If it is determined in S210 that the processor Pi corresponding to the canceled processing request signal RQi has been designated with priority, the process proceeds to S220.
[0047]
In S220, it is determined whether or not the number of consecutive access right grants is limited by the mode setting signal MOD, and if not, the process proceeds to S240.
In S240, the processing request signal RQi released earlier is monitored for a preset fixed period (one clock period in the present embodiment) TC, and the processing request signal RQi is reset within this fixed period TC. Is determined.
[0048]
If not reset, the process goes to S260 to set and release the selection signals SLi and SLj and clear the count value C as described above (another processing request signal RQj is set). If not (S270-NO), (5) to (5) 'in FIG. 5; if another processing request signal RQj is set (S270-YES), (6) to (6) in FIG. ▼ ').
[0049]
As a result, if another processing request signal RQj is set, the right to access the coprocessor CP is transferred to the processor Pj after a certain period TC elapses after the cancellation of the processing request signal RQi.
If it is determined in step S240 that the processing request signal RQi has been reset, the process proceeds to step S250, where the count value C is incremented, and then the present process is terminated ((7) to (7) in FIG. 6). ▼ '). As a result, the access right to the coprocessor CP is continuously held by the processor Pi regardless of the presence or absence of the processing request signal RQj.
[0050]
If it is determined in step S220 that the number of consecutive access right grants is limited, the flow shifts to step S230 to determine whether the count value C is smaller than a limit value Cmax of the number of consecutive access right grants. to decide.
If the count value C is smaller than the limit value Cmax (C <Cmax), the process proceeds to S240, and performs processing according to the presence or absence of the resetting of the processing request signal RQi as described above (there is resetting). In this case (S240-YES), see (7)-(7) 'in FIG. 6, and when there is no resetting (S240-NO), see (8)-(8)' in FIG. 6).
[0051]
On the other hand, if the count value C has reached the limit value Cmax (S230-NO), the process proceeds to S260 without monitoring the processing request signal RQi, and sets the selection signals SLi and SLj as described above. , Cancellation, and clearing of the count value C (see (9) in FIG. 6).
[0052]
As a result, if another processing request signal RQj is set, the access right to the coprocessor CP is immediately transferred to the processor Pj without waiting for a certain period TC after releasing the processing request signal RQi. become.
In the present embodiment, the processing request generation circuit 12ConfigurationMeans, the hold control circuit 16 is the hold setting means, S270 and S280 are the hold release means, S240 is the hold release prohibiting means, and S220 and S230 are the hold release means.2S210 is the second consecutive access restricting means.1Corresponds to the continuous access restricting means.
[0053]
As described above, in the arbitrating device 10 of the present embodiment, the processing request signal RQi set at the start of the transmission of the write signal WRi or the read signal RDi to the coprocessor CP and released at the end of the transmission of the read signal RDi is A processor Pi is generated for each processor Pi, and based on the processing request signal RQi, a processor Pi to which the access right to the coprocessor CP is to be given is selected, and once the access right is given, the processing request signal RQi is released. During this time, the access right is occupied.
[0054]
Therefore, according to the arbitrating device 10 of the present embodiment, during a series of operations (started by writing input data and finished by reading output data) necessary to obtain a normal processing result from the coprocessor CP, The access right of the coprocessor CP is not transferred to another processor, and the processor Pi having the access right can obtain a highly reliable processing result from the coprocessor CP.
[0055]
According to the arbitrating device 10 of the present embodiment, the access right is unconditionally granted to the same processor while the processing request signal RQi is active, that is, while a series of operations on the coprocessor CP are performed. Therefore, the coprocessor CP can be used more efficiently as compared with a conventional device that determines whether or not continuous access can be performed for each access.
[0056]
In addition, when priority setting is not performed by the operation mode setting signal, the access right is released each time this series of operations is completed, so that the specific processor Pi continues to occupy the access right more than necessary. Can be reliably prevented.
Further, in the present embodiment, even when setting the priority designation, the fixed period TC for determining whether to permit continuous access can be set short regardless of the operation of the coprocessor CP. In this embodiment, it is also possible to limit the upper limit of the number of consecutive grants of the access right, so that the unnecessary occupation of the unnecessary access right by the specific processor Pi can be restricted. It can be reliably prevented.
[0057]
In the present embodiment, priority designation for designating whether or not to allow the processor to continuously grant the access right can be individually set for each processor by the operation mode setting signal MOD. A configuration may be adopted in which only one of the processors Pi is designated with priority, and the processor Pi to be designated with priority is alternately switched every time a predetermined time elapses.
[0058]
In this case, as shown in FIG. 6B, when the processor having the access right is designated with priority ({circle over (7)} in the figure), the access right is continuously granted, and after a certain period of time, the priority is given. When the processing request signal RQi is released after the designation is switched, if another processing request signal RQj is set, the processing request signal RQi is immediately sent to the processor Pj corresponding to the processing request signal RQj without waiting for a certain period TC. Access right is granted ([9] in the figure).
[0059]
However, the switching of the priority designation may be performed by allocating the same time or unequal time, and furthermore, it may be configured such that the ratio of the assigned time of the priority designation can be set by the operation mode setting signal MOD. Good. In this case, the storage device that stores the processor specified with priority corresponds to the device specifying device, and the process of rewriting the contents of the storage device corresponds to the specification changing device.
[Second embodiment]
Next, a second embodiment will be described.
[0060]
In the first embodiment, the arbitration device 10 in the case where one coprocessor CP is shared by two processors P0 and P1 has been described. However, in the present embodiment, one coprocessor CP is composed of n + 1 processors P0 to Pn. The arbitration device 20 when sharing is described below.
[0061]
As shown in FIG. 7, the arbitration device 20 of the present embodiment includes a processing request generation circuit 22, a selection circuit 24, a hold control circuit 26, and a bus switching circuit 28, like the arbitration device 10 of the first embodiment. .
The processing request generation circuit 22 generates the processing request signal RQi from the read signal RDi and the write signal WRi, and the individual circuits are exactly the same as the processing request generation circuit 22 of the first embodiment. n + 1 are provided.
[0062]
The hold control circuit 26 includes a flip-flop circuit FFi for each hold signal HOLDi, latches the signal level applied to the data input terminal at the rising edge of the processing request signal RQi, and is reset by the selection signal SLi. Is exactly the same as the hold control circuit 16 of the first embodiment, but the data input terminal of the flip-flop circuit FFi is connected via the OR circuit OR1i to all the processing request signals RQj ( j ≠ i) is applied. That is, when any one of the processing request signals RQj of the other processors Pj is set when the processing request signal RQi is set, the hold signal HOLDi to the processor Pi becomes active.
[0063]
The bus switching circuit 28 connects the individual buses BSi and the common bus BSC when the selection signal SLi is active, similarly to the bus switching circuit 18 of the first embodiment, except that the number of the individual buses BS0 to BSn is large. Works to connect.
Then, the selection circuit sets RQj in S110 and S270 to all processing requests other than RQi, and in S280, activates the selection signal SLk corresponding to the processing request signal RQk having the highest priority among RQj. It is exactly the same except for thinking as.
[0064]
However, here, the priority of the processing request signal RQ is set higher as the priority is set earlier. The processing for setting the priority of the processing request signal RQ corresponds to the request priority setting means of the present invention.
The arbitration device 20 of the present embodiment configured as described above is completely different from the arbitration device 10 of the first embodiment except that the access right of the coprocessor CP can be arbitrated for n + 1 processors P0 to Pn. Similar effects can be obtained.
[0065]
By the way, as in the arbitration device 20 of the present embodiment, when there are a large number of processors P0 to Pn to be arbitrated, only one of the processors Pi is designated as priority and the priority designation is sequentially switched. it can.
An example of this priority designation switching process (corresponding to the designation change means of the present invention) will be described with reference to the flowchart shown in FIG.
[0066]
That is, in S310, it is determined whether or not a predetermined time that has been set in advance has elapsed, and if it has not elapsed, the process waits by repeatedly executing the same step. After a lapse of the predetermined time, the flow shifts to S320 to increment a designated value p indicating a processor to be preferentially designated. In S330, it is determined whether or not the designated value is larger than n representing the number of processors. If it is larger, the process proceeds to S340 and resets the designated value p to 0, and returns to S310. If it is smaller, the process returns to S310 as it is.
[0067]
Thereby, the processor Pp represented by the newly set p is designated by priority for a predetermined time.
In this case, the priority designation switching is always performed in a fixed order. For example, a table in which a plurality of switching orders are written is prepared in advance, switching is performed according to the table, and the operation mode setting signal MOD is used. The switching order may be configured to be specified, or the switching order may be appropriately changed according to a change in the situation. The process of changing the switching order corresponds to the order changing means of the present invention.
[0068]
Further, in the present embodiment, when the processing request signals RQ0 to RQn compete, priority is given in the order of occurrence, but this priority may be linked to the above-mentioned priority designation.
[Third embodiment]
Next, a third embodiment will be described.
[0069]
The arbitration device 30 of the present embodiment differs from the arbitration device 10 of the first embodiment only in part of the configuration.
However, in the first embodiment, the coprocessor CP performs input / output of data using the same data bus. However, the coprocessor CPa used in the present embodiment has an input register for holding input data. An RGI and an output register RGO for holding output data are provided independently. Simultaneous access to both registers RGI and RGO, that is, reading of output data as a processing result in the previous processing, The configuration is such that writing of input data to be processed next can be performed simultaneously.
[0070]
When accessing the coprocessor CP, each of the processors P0 and P1 always performs writing of the operation target data and reading of the operation result data in a pair, and the read signal is transmitted to the coprocessor independently. Shall not be supplied by
As shown in FIG. 9, in the arbitrating device 30 of the present embodiment, the bus switching circuit 18a supplies the address signal ADC, the read signal RDC, and the write signal WRC to the coprocessor CPa, and inputs the data WDT to the coprocessor CPa. And output data RDT from the coprocessor CPa are input / output via separate data buses. When the selection signals SL0 and SL1 are simultaneously activated, one of the individual buses BS0 and BS1 is used as the data bus for the input data WDT and the other is used as the data bus for the output data RDT in accordance with the read signal RD and the write signal WR. It is configured to connect to the bus simultaneously.
[0071]
Further, the processing request generation circuit 12a includes only an SR flip-flop circuit SFi that is set at the rising edge of the write signal WRi and reset at the rising edge of the read signal RDi.
Then, as shown in FIG. 10, when the processing request signal RQi is released, the selection circuit SLi does not inactivate the selection signal SLi at the same time as this, but the transmission end timing of the read signal RD0 (falling edge). ) (See period X in the figure).
[0072]
Thereby, when another processing request signal RQj is set when the processing request signal RQi is released, the two selection signals SLi and SLj are simultaneously activated, so that the processor Pi reads data from the coprocessor CP, and Writing of data to the coprocessor CP by Pj is performed simultaneously.
[0073]
As described above, according to the arbitration device 30 of the present embodiment, the reading of the result data and the writing of the data to be processed next can be simultaneously performed on the coprocessor CP. CP utilization efficiency can be improved.
Further, since the configuration of the processing request generation circuit 12a is simplified, the size of the apparatus can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a multiprocessor system.
FIG. 2 is a block diagram illustrating an internal configuration of an arbitration device according to the first embodiment.
FIG. 3 is a flowchart illustrating an operation of a selection circuit when a processing request signal is set.
FIG. 4 is a flowchart illustrating an operation of a selection circuit when a processing request signal is released.
FIG. 5 is a timing chart showing the operation of each part of the arbitration device.
FIG. 6 is a timing chart illustrating the operation of each part of the arbitration device.
FIG. 7 is a block diagram illustrating a configuration of an arbitration device according to a second embodiment.
FIG. 8 is a flowchart illustrating the contents of a priority designation switching process.
FIG. 9 is a block diagram illustrating a configuration of an arbitration device according to a third embodiment.
FIG. 10 is a timing chart illustrating the operation of each part of the arbitration device.
[Explanation of symbols]
10, 20, 30 ... arbitration device, 12, 12a, 22 ... processing request generation circuit, 14, 14a, 24 ... selection circuit, 16, 26 ... hold control circuit, 18, 18a, 28 ... bus switching circuit, BS0, BS1 ... Individual bus, BSC... Common bus, CP, CPa... Coprocessor, FF0 to FFn... Flip-flop circuit, INV0 to INVn... ... Input register, RGO ... Output register, SF0 to SFn ... SR flip-flop circuit

Claims (7)

When the auxiliary data processing device that generates a processing result according to the input data as output data when the input data is written is shared by a plurality of data processing devices, the data processing device sends the auxiliary data processing device to the auxiliary data processing device. An access right arbitration device for arbitrating access rights of
The data processing device is set by starting transmission of a write signal for writing the input data to the auxiliary data processing device , or by starting transmission of a read signal for reading the output data, and reading the output data. Processing request setting means for setting a processing request released by the completion of transmission of the read signal for each data processing device ;
When a processing request is set by the processing request setting unit, if a processing request of another data processing device has already been set, a hold setting unit that sets a data processing device corresponding to the newly set processing request to a hold state; ,
A data processing device for which a processing request has been set by the processing request setting means, which is in a non-hold state, is defined as a first data processing device having access right to the auxiliary data processing device, and At the time of canceling the processing request of the apparatus, if there is another processing request, one of the processing requests is selected, and the second data processing apparatus corresponding to the selected processing request is released from the hold state, so that the second processing request is released. Hold release means for giving the data processing device of claim 2 access to the auxiliary data processing device;
After the processing request of the first data processing device is released, if the processing request of the first data processing device is set again within a predetermined period of time, the operation of the hold release unit is performed. Hold release prohibition means to prohibit,
Device specifying means for specifying any of the data processing devices;
First continuous access restricting means for prohibiting the operation of the hold release prohibiting means when the specification of the apparatus specifying means does not match the first data processing apparatus;
An access right arbitration device comprising: The access right arbitration device according to claim 1 ,
When the access right is continuously given to the first data processing device, the number of times of continuous access is counted, and when the count value reaches a preset upper limit number, the operation of the hold release prohibiting means is prohibited. An access right arbitration device comprising second continuous access restriction means. 3. The access right arbitration device according to claim 1, further comprising a designation change unit that changes the designation content of the device designation unit. 4. The access right arbitrating device according to claim 3 , wherein the designation changing means periodically changes the designated contents in accordance with a preset switching order. Access arbitration equipment according to claim 4, characterized in that it comprises a sequence changing means for the override means for changing the switching sequence used in the change of the specified contents. In the access arbitration device according to any claims 1 to 5,
Comprising request priority setting means for setting the priority of the processing request,
The hold release unit releases the data processing device corresponding to the processing request with the highest priority set by the request priority setting unit from the hold state when a plurality of the processing requests exist. Access right arbiter. The access right arbitration device according to claim 6 ,
The access right arbitrating device, wherein the request priority setting means sets a priority in accordance with an order in which the processing requests are generated.

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