JP3597744B2 - Interrupt factor signal flag register device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an interrupt factor signal flag register circuit, and more particularly to a device for detecting and clearing an asynchronous interrupt factor signal incorporated in an LSI (Large Scale Integrated Circuit).
[0002]
[Prior art]
FIG. 4 is a schematic block diagram of a first conventional interrupt factor signal flag register circuit (device).
The factor signal flag register circuit includes a flag register 1 having eight flag bit registers 1a to 1h corresponding to each interrupt factor, and reading / writing of the flag register 1 based on various control signals from a control means (controller) 3. When an interrupt factor occurs, data is held in the flag bit registers 1a to 1h corresponding to the interrupt factor, the occurrence of the interrupt is notified to the controller 3, and the occurrence of the interrupt is generated. Controller 3 that has received the notification notifies the address decoder 2 to read out the data held in the flag register 1 and detect the data content to determine the interrupt factor that has occurred and to control the corresponding interrupt. And
[0003]
Further, the controller 3 controls the address decoder 2 to write predetermined data to the flag bit registers 1a to 1h in order to return the contents of the flag bit registers 1a to 1h to the state before the occurrence in accordance with the execution of the interrupt control. (Clear).
Note that the number of flag bit registers in the flag register 1 will be described as eight for convenience of description, but the number can be appropriately determined according to specification conditions and is not limited.
[0004]
As shown in FIG. 4, each of the flag bit registers 1a to 1h has an interrupt request line 106a to 106h for notifying an interrupt generation signal INTa to INTh, and an input data bus for transmitting input data sent from the controller 3. 100 and a write control line 108 for transmitting a write enable signal WCS (hereinafter abbreviated as “write signal WCS”) enabling writing of the input data from the address decoder 2 are input terminals in this order. They are connected to the INTRRG terminal, the data terminal, and the WCS terminal, respectively.
[0005]
An output terminal DOUT for outputting data in the flag bit register 1 is connected to an output data bus 101 connected to the controller 3 via two-input AND circuits 4a to 4h, and the AND circuits 4a to 4h Is connected to a read control line 107 for transmitting a read enable signal RCS (hereinafter, abbreviated as “read signal RCS”) from the address decoder 2 based on the active / inactive state of the read signal RCS. The reading of all data in the flag bit register 1 to the controller 3 is controlled.
[0006]
The address decoder 2 includes an address bus 102 for transmitting an address signal from the controller 3, an I / O read signal line 103 for transmitting an I / O read signal, and an I / O write signal line for transmitting an I / O write signal. Reference numeral 104 is connected to each input terminal, and a write control line 108 for transmitting a write signal WCS to the flag bit register 1 and a read control line 107 for transmitting a read signal RCS are connected to each output terminal.
[0007]
Also, the interrupt request lines 106a to 106h for notifying the interrupt factor generation signals INTa to INTTh are provided via the AND circuit 5 when the interrupt factor signal is "L" active and the OR circuit when the interrupt factor signal is "H" active. It is connected to an interrupt line 105 that transmits an interrupt generation signal INT to the controller 3.
[0008]
FIG. 5 shows an example of a block diagram for realizing the operation of the flag bit registers 1a to 1h.
The flag bit register includes a selector circuit 13 and a D flip-flop 14, and selects and outputs data to be held in the D flip-flop 14 by the selector circuit 13 based on an input signal.
[0009]
That is, the selector circuit 13 has three data input terminals (1), (2), and (3), two switching control terminals A and B, and one output terminal (4). .
The data input terminal (1) receives a feedback output signal from the D flip-flop 14, and the terminal (2) receives an interrupt factor signal INTx (x is any one of 0 to 7; Similarly, the inverted interrupt factor signal / INTx inverted through the inverter 10 is input, and both input signals input to the terminal write WCS and the data input terminal are output to the terminal (3) via the AND circuit 11. The signal is connected.
The switching control terminal A is connected to an interrupt factor signal INTx from the terminal INTRFG, and the switching control terminal B receives the input signal of the WCS terminal after being inverted by the inverter 12. The output terminal (4) is connected to the input terminal D of the D flip-flop 14.
[0010]
As described above, the D flip-flop 14 uses the output signal of the selector circuit 13 as an input signal and feeds back an output signal obtained by delaying the input signal in accordance with the clock signal input to the data input terminal (1) of the selector circuit 13. At the same time, the held data is output from the DOUT terminal, which is an output terminal, as data in the flag bit register.
[0011]
The selection operation of the selector circuit 13 will be described below.
First, when "0" is input to the control terminal A, the terminal (2) is selectively connected to the output terminal (4).
When "1" is input to the control terminal A, the control terminal B is further referred to. When "0" is input to the control terminal B, the terminal (3) is connected to the output terminal (4). Select connection.
When "1" is input to the control terminal A and "1" is input to the control terminal B, the terminal (1) is selectively connected to the output terminal (4).
[0012]
FIG. 6 shows an example of a logic circuit for realizing the selecting operation of the selector circuit 13.
An AND gate 132 for taking a logical product of a signal obtained by inverting the input signal of the control terminal A by the inverter 131 and an input signal of the input terminal (2); a signal obtained by inverting the input signal of the control terminal B by the inverter 133; A three-input AND gate 134 for the input signal of A and the input terminal (3) and a three-input AND gate 135 for the input signals of the control terminals A and B and the input signal of the terminal (1) are provided. Further, an OR circuit 136 for taking the logical sum of the output signals of the three AND gates 132 to 135 is provided, and the output of the OR circuit 136 is used as the output signal of the output terminal (4).
[0013]
According to the configuration of the selector circuit 13 described above, when the interrupt factor signal INTx from the terminal INTRFG is “0” (when an interrupt factor signal is generated), “0” is input to the control terminal A of the selector circuit 13 and output is performed. The input terminal (2) is selected as the terminal (4), but since the input signal of the input terminal (2) is "1", the output terminal (4) outputs "1" and the D flip-flop 14 outputs "1". 1 "is written.
[0014]
Conversely, when the interrupt factor signal INTx from the terminal INTRFG is “1” (when no interrupt factor signal is generated) and the write signal WSC is “1”, the inverter 12 sets “0” to the control terminal B. Is input and the input terminal {circle around (3)} is selected as the output terminal {circle around (4)}. Since the data signal is input to the input terminal {circle around (3)} via the AND circuit 11, the output terminal {circle around (4)} is A data signal is output, and the data signal is written to D flip-flop.
For example, when the data signal is "0", "0" is written to the D flip-flop 14, and the D flip-flop 14 becomes "0".
[0015]
When the interrupt factor signal INTx from the terminal INTRFG is “1” (when no interrupt factor signal is generated) and when the write signal WCS is “0”, the control signal B of the selector circuit 13 is controlled by the inverter 12. Becomes "1", the input terminal (1) is selected as the output terminal (4), the output Q of the D flip-flop 14 is input to the input terminal (1), and the input D of the D flip-flop 14 is again input. Is input to
Therefore, the value of the D flip-flop 14 does not change, and the state of DOUT is maintained.
[0016]
A single address is assigned to the interrupt factor signal flag register 1 without distinction between read and write.
[0017]
Next, the configuration of the address decoder 2 will be described with reference to FIG.
FIG. 7 is a block diagram of the conventional address decoder 2 described above, and includes a decoder 21, an OR circuit 22, and two AND circuits 23 and 24.
The address signal transmitted by the address bus 102 is decoded by the decoder 21, and a decoded address signal corresponding to the flag bit register is output (one of the decode signal lines 21a to 21h is activated to "H"). After being converted into one control signal via the circuit 22, the read signal RCS, which is a read control signal, can be output together with the I / O read signal to the AND circuit 23, and the control signal is output together with the I / O write signal. The write signal WCS which is a write control signal that is input to the AND circuit 24 can be output.
Therefore, the address decoder 2 outputs a read signal RCS when an address signal and an I / O read signal are input, and outputs a write signal WCS when an address signal and an I / O write signal are input.
[0018]
Next, the process from detection of an interrupt factor to clearing of the flag register will be described with reference to the flowchart of FIG.
When detecting the interrupt factor, when the controller 3 receives the notification of the occurrence of the interrupt (S1), the controller 3 outputs the address signal and the I / O read signal assigned to the interrupt factor signal flag register 1 to the address decoder 2. Then, the read signal RCS of the address decoder 2 is set to active “H”, input to all the AND circuits 4 a to 4 h via the read control line 107, and outputs all the data signals stored in the flag bit registers 1 a to 1 h. Output to the data bus 101. The data signal on the output data bus 101 is sent to the controller 3 to enable detection of an interrupt factor (S2).
[0019]
The content of the interrupt factor signal flag register 1 is such that the flag bit at which an interrupt has occurred is "H" and the other flag bits are "L". The interrupt factor is recognized based on the data contents, and the data contents are stored in the controller 3 (S3).
[0020]
After recognizing the interrupt factor, the controller 3 determines which interrupt factor (flag) is to be processed (S4), and changes only the flag for processing the internally held register contents to "zero". (S5) The changed contents held in the register are written to the interrupt factor signal flag register 1 (S6).
[0021]
The means by which the controller 3 writes (clears) the interrupt factor signal flag register 1 means that the controller 3 outputs the address signal, the I / O write signal, and the input data to be written which are allocated to the interrupt factor signal flag register 1. The address decoder 2 activates the write WCS signal from the address signal and the I / O write signal and transmits the signal to the flag bit registers 1a to 1h, thereby setting the flag bit registers 1a to 1h in a writable state. Is written to all flag bit registers 1a to 1h.
[0022]
In the above-described series of interrupt factor detection and clear processing, the content of the interrupt factor signal flag register 1 read internally by the controller 3 is temporarily held because the controller 3 writes all the flags when writing to the interrupt factor signal flag register 1. This is because the value of the input data bus 100 is written to the bit registers 1a to 1h, so that the value of the flag bit register that is not desired to be changed before and after writing is not changed.
In other words, if there are two interrupt cause signals read by the controller 3, even if the contents of the flag bit register are uniformly cleared with one interrupt process, the controller can recognize and process the remaining interrupt processes. This is because
[0023]
A second prior art interrupt factor signal flag register circuit (device) is disclosed in Japanese Unexamined Patent Application Publication No. Hei 8-44572. When an interrupt factor register is read by a higher-level device (such as a controller). Then, the register is simultaneously reset.
[0024]
[Problems to be solved by the invention]
However, in the first conventional interrupt detection means, since the controller 3 changes and writes only the bit to be cleared based on the data at the time of reading the interrupt factor signal flag register 1, it does not know when it will occur. When the asynchronous interrupt factor signal is generated after the controller 3 performs the read operation on the interrupt factor signal flag register 1 and before the write operation, the interrupt factor signal in the interrupt factor signal flag register 1 corresponds to the interrupt factor signal. Although the flag bit register changes to "H", "L" is written by the controller 3, and there is a problem that it is not possible to recognize and specify the interrupt factor generated between this read and write.
[0025]
Further, in the second conventional example, when a plurality of interrupt causes occur, all of them are cleared at the time of reading once, so that the controller cannot control the clearing of the interrupt cause signal flag register, and the controller becomes an interrupt cause. If interrupt factors occur one after another during the process that caused the problem, it is necessary to hold the data of the interrupt factor signal flag register in the controller each time, and the scale of the hardware also increases. was there.
[0026]
The present invention has been made in order to solve the above-mentioned problem, and it is intended that when the interrupt occurs after the controller reads the interrupt factor signal flag register and writes the interrupt factor signal flag register, Even if an unknown asynchronous interrupt cause signal is generated, the interrupt cause signal is held in the interrupt cause signal flag register as a flag, and the flag held by a subsequent write operation by the controller to the interrupt cause signal flag register is cleared. An object of the present invention is to provide an interrupt factor signal flag register device which can control the generation of an interrupt factor signal without being performed.
[0027]
[Means for Solving the Problems]
In the present invention, in order to achieve the above object, a plurality of flag bit registers that hold a pulse generated by an interrupt factor signal as flag bits, a flag register having an address assigned to each flag bit register,
Controlling the flag bits held in each flag bit register in the flag register based on an address signal of an address related to the flag register transmitted from the control unit and a read signal instructing reading of the flag bit in the flag register Flag reading means for transmitting to the unit;
An address signal of a flag bit register holding a processing flag bit corresponding to or corresponding to the interrupt processing corresponding to the control unit in the flag bits transmitted to the control unit, and instructing clearing of the flag bit to the flag register Flag reset means for resetting only the flag bit register holding the processing flag bit based on the write signal to be processed,
The flag reset means has an output terminal for each flag bit register, and activates only an output terminal of the flag bit register corresponding to an input address signal. The decoder resets the write signal for each output terminal of the decoder. AND gate that takes the logical product of
The present invention is characterized in that each AND gate output signal is connected to a flag bit register corresponding to an address signal.
[0029]
According to the present invention, in order to read a flag bit of a flag register, when reading by specifying an address from the control unit, regardless of which address address is assigned to each flag bit register, The state of all flag bit registers can be read by a single read operation.
Thereafter, when the control unit specifies the address from the control unit and writes "zero" to clear the flag bit of the flag bit register holding the processing flag bit corresponding to or corresponding to the interrupt processing, When the control unit designates a specific address assigned to each flag bit register, the write operation is performed only on the specific flag bit of the flag register, and the write operation is not performed on the other flag bit registers.
[0030]
As a result, even if an asynchronous interrupt factor signal is generated from the controller which performs the read operation of the interrupt factor signal flag register to the write operation of the interrupt factor signal flag register, it is not possible to determine when the asynchronous interrupt factor signal occurs. The cause signal is held as a flag in the interrupt cause signal flag register, and the held flag is not cleared by a subsequent write operation to the interrupt cause signal flag register by the control unit, so that the interrupt cause signal can be generated reliably. Can be grasped by the controller.
[0031]
Further, only the output terminal of the flag bit register having the corresponding processing flag bit from the address signal input by the decoder becomes active, and the output terminals of the other flag bit registers become inactive.
Therefore, of the AND gates provided for each output terminal of the decoder, only the output of the AND gate corresponding to the flag bit register having the processing flag bit becomes active, and only the corresponding flag bit register can be cleared.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted.
FIG. 1 is a block diagram of an interrupt factor signal flag register circuit according to an embodiment of the present invention. The configuration of the address decoder 2a is different from that of the first conventional example (FIG. 4).
[0033]
When reading the flag bit registers 1a to 1h in the flag register 1 by designating an address from the controller 3, the address decoder 2a designates one of the address addresses allocated to each of the flag bit registers 1a to 1h. Also, when the read decoder CS is activated in the address decoder 2a, the state of all the flag bit registers 1a to 1h can be read by a single read operation, and when the specific flag bit register of the flag register 1 is cleared, the controller When 3 designates a specific address assigned to each flag bit register, only the write CS connected to the specific flag bit register is activated, only the specific flag bit register is written, and the other flag bit registers are written. Is a write operation Is set to I no configuration.
[0034]
As a result, even if the asynchronous interrupt factor signals INTa to INTTh which are not known when they occur during the period after the controller 3 performs the read operation of the interrupt factor signal flag register 1 and performs the write operation, the interrupt factor signals Is held in the interrupt factor signal flag register 1 as a flag, so that the controller 3 can reliably recognize the generation of the interrupt factor signal.
[0035]
In this embodiment, as the address decoder 2a that realizes the above operation, the read signal WCS is commonly input to each of the AND circuits 4a to 4h, and the write signal RCS is independently provided for each of the flag bit registers 1a to 1h. Write is performed by activating only the write control line connected to the desired flag bit register for writing via the write control lines 108a to 108h.
In this embodiment, the interrupt factor signals INTa to INTh are "L" active, the read signal RCS is "H" active, and the write signal WCS is "H" active.
[0036]
FIG. 2 shows a detailed block diagram of the address decoder 2a.
The address decoder 2a outputs a decode address signal (one of the output signal lines 21a to 21h is active "H") corresponding to the flag bit register from the address of the flag bit register, and the logic of all the decode address signals. An OR gate 22 for taking a sum, an AND gate 23 for taking a logical product of an output signal of the OR gate 22 and an I / O read signal, and an I / O write signal for each of the decode signal signal output signal lines 21a to 21h. AND gates 24a to 24h for obtaining a logical product are provided, and the outputs thereof are write control lines 108a to 108h.
[0037]
The output signal of the AND gate 23 becomes the read signal RCS, and the output signal of the AND gates 24a to 24h becomes the write signal WSC output to the flag bit register corresponding to the address data.
[0038]
When the controller 3 specifies an address corresponding to the flag bit register according to the above configuration, the address decoder 2a, when writing to the interrupt factor signal flag register 1, writes the write signal connected to the specific flag bit register to be written. When only the WCS is activated and the interrupt factor signal flag register 1 is read, only a single read signal RCS connected to all flag bit registers is activated.
[0039]
Next, the overall operation of the interrupt factor signal flag register circuit according to the embodiment of the present invention will be described with reference to the circuit diagram of FIG. 1 and the flowchart of FIG.
When the interrupt factor signals INTa to INTh are generated, the interrupt factor signal INT is notified to the controller 3 through the AND circuit 3, and "H" is held in the flag bit registers 1a to 1h corresponding to the interrupt factor signals.
[0040]
When the controller 3 receives the interrupt factor generation signal INT (S1), it outputs the address data allocated to the interrupt factor signal flag register 1 and an I / O read signal. The active state is set to "H", and all the output signals DOUT of the flag bit registers 1a to 1h are output to the output data bus 101 through the AND circuits 4a to 4h, and the contents of the interrupt factor signal flag register 1 are read (S2).
[0041]
The contents of the interrupt factor signal flag register 1 are such that the flag bit where an interrupt has occurred is “H” and the other flag bits are “L”, and the controller 3 reads the output data bus 101 The state of the interrupt factor signal flag register 1 can be grasped.
[0042]
After recognizing the interrupt factor, the controller 3 determines which interrupt factor causes the process to be performed (S4). Further, the controller 3 writes a "zero" signal to the specific flag bit register in order to clear the contents of the flag bit register corresponding to the processing to be performed thereafter (S7).
[0043]
The controller 3 writes an address signal assigned to the specific flag bit register, an I / O write signal, and “zero” input data, which is a write content, in order to write the specific flag bit register. Output.
The address decoder 2 receiving the address signal and the I / O write signal activates only the write signal WCS corresponding to the address signal to "H", so that the input data is written only to the corresponding flag bit register. Since the write signal WCS is inactive, the flag bit registers other than the specific flag bit register are not written with input data, and the state is maintained.
Further, in the above processing (FIG. 3), the processing of S3 and S5 of the conventional processing (FIG. 8) is eliminated, which is useful for shortening the processing time and simplifying the program of the controller.
[0044]
Although the preferred embodiment of the present invention has been described in the above embodiment, the present invention is of course not limited to this.
For example, the configuration of the address decoder 2a is not limited to the configuration shown in FIG. 2, but may be any circuit configuration that can provide a write signal WCS for each flag bit register and activate only a specific write signal WCS. .
[0045]
【The invention's effect】
As described above, according to the present invention, when reading the interrupt factor signal flag register, the control unit can read all the flag bits by specifying the address assigned to the flag bit register. When writing (clearing), only a specific flag bit can be cleared.
As a result, even if an asynchronous interrupt factor signal is generated from the time when the control unit reads the interrupt factor signal flag register and clears the interrupt factor signal flag register, even if an asynchronous interrupt factor signal is generated, the interrupt is not interrupted. The cause signal is held as a flag in the interrupt cause signal flag register, and the held flag is not erased by the subsequent clearing operation of the interrupt cause signal flag register by the control unit, so that the interrupt cause signal is reliably generated. Can be grasped by the control unit.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of an interrupt factor signal flag register circuit according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of an address decoder according to the embodiment of the present invention.
FIG. 3 is a flowchart of an interrupt factor signal flag register circuit according to the embodiment of the present invention.
FIG. 4 is an explanatory diagram of an interrupt factor signal flag register circuit of Conventional Example 1.
FIG. 5 is an explanatory diagram of a flag bit register.
FIG. 6 is an explanatory diagram of a selector circuit.
FIG. 7 is an explanatory diagram of an address decoder of Conventional Example 1.
FIG. 8 is a flowchart of an interrupt factor signal flag register circuit according to Conventional Example 1.
[Explanation of symbols]
1 flag register 1a-1h flag bit register 2a address decoder 3 controller 4a-4h 2 input AND circuit 100 input data bus 101 output data bus 102 address bus 103 I / O read signal line 104 I / O write signal line 107 read control line INTa to INTh Interrupt factor signals 108a to 108h Write control line 21 Decoders 21a to 21h Decode address signals 24a to 24h Two-input AND circuit

Claims (1)

A plurality of flag bit registers for holding generated pulses of the interrupt factor signal as flag bits, and a flag register having an address assigned to each flag bit register;
Controlling the flag bits held in each flag bit register in the flag register based on an address signal of an address related to the flag register transmitted from the control unit and a read signal instructing reading of the flag bit in the flag register Flag reading means for transmitting to the unit;
An address signal of a flag bit register holding a processing flag bit corresponding to or corresponding to the interrupt processing corresponding to the control unit in the flag bits transmitted to the control unit, and instructing clearing of the flag bit to the flag register based on the write signal and which includes a flag resetting means for resetting only the flag bit register which holds the processing flag bits,
The flag reset means has an output terminal for each flag bit register, and activates only an output terminal of the flag bit register corresponding to an input address signal. The decoder resets the write signal for each output terminal of the decoder. AND gate that takes the logical product of
An interrupt factor signal flag register device, wherein each of the AND gate output signals is connected to a flag bit register corresponding to an address signal.

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