JP3601334B2 - Method of manufacturing semiconductor device having trench element isolation region - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an element isolation groove.
[0002]
[Background Art]
In recent years, with miniaturization of semiconductor elements, for example, MOS transistors, it is necessary to miniaturize a region for separating between semiconductor elements. In order to achieve the miniaturization of this region, a trench element isolation technique for providing a groove (hereinafter referred to as a “trench”) on a substrate between semiconductor elements and filling the trench with an insulating material to separate the semiconductor elements is studied. Have been. An example of this technique will be described below.
[0003]
24 to 28 are cross-sectional views schematically showing steps of forming a trench element isolation region 123 using a conventional trench element isolation technique.
[0004]
First, as shown in FIG. 24, after a pad layer 112 and a stopper layer 114 are sequentially deposited on a silicon substrate 110, a resist pattern R10 having a predetermined pattern is formed on the stopper layer 114. Is used as a mask to etch stopper layer 114.
[0005]
Next, as shown in FIG. 25, the resist layer R10 is removed by ashing, and the silicon substrate 110 is etched using the stopper layer 114 as a mask to form a trench. Thereafter, the exposed surface of silicon substrate 110 in trench 116 is thermally oxidized to form trench oxide film 118.
[0006]
Next, an insulating layer 120 is deposited on the entire surface so as to fill the trench 116, and as shown in FIG. 26, the insulating layer 120 is planarized using the stopper layer 114 as a mask. Next, the stopper layer 114 is removed using hot phosphoric acid.
[0007]
In a subsequent step, a portion of the insulating layer 120 protruding from the level of the upper surface of the silicon substrate 110 is isotropically etched to form a trench isolation region 123 as shown in FIG.
[0008]
However, when the trench element isolation region 123 is formed as described above, a depression 125 is generated at the upper end of the insulating layer 120 as shown in FIG.
[0009]
As shown in FIG. 28, the depression 125 has a steep slope of the silicon substrate 110 and the insulating layer 120 in the depression 125. If the inclination is steep, the gate electrode material remains in the recess 125 in the etching of the gate electrode material for forming the gate electrode. If the gate electrode material remains in the recess 125, a problem such as a short circuit occurs.
[0010]
[Problems to be solved by the invention]
An object of the present invention is to provide a method of manufacturing a semiconductor device having a trench element isolation region, in which an insulating layer in a trench element isolation region is satisfactorily embedded.
[0011]
[Means for Solving the Problems]
A method for manufacturing a semiconductor device having a trench element isolation region according to the present invention includes the following steps (a) to (k).
(A) forming a pad layer on the surface of a silicon substrate;
(B) forming a stopper layer for chemical mechanical polishing on the surface of the pad layer;
(C) forming a resist layer having a predetermined pattern on the surface of the stopper layer;
(D) ion-implanting an oxygen-based substance into the stopper layer from a direction oblique to the surface of the stopper layer using the resist layer as a mask;
(E) etching and patterning the stopper layer and the pad layer using the resist layer as a mask;
(F) using the stopper layer as a mask, etching the silicon substrate to form an element isolation groove;
(G) forming a protective film at an end of the stopper layer by thermal oxidation;
(H) forming an insulating layer filling the isolation trenches on the entire surface;
(I) a step of planarizing the insulating layer by a chemical mechanical polishing method using the stopper layer as a stopper;
(J) removing the stopper layer;
(K) forming a trench element isolation region by etching the portion of the insulating layer and the protective film, which protrude from a surface of a region of the silicon substrate where an element is to be formed;
[0012]
The features of the present invention are mainly the following two points.
[0013]
(1) First, a step (k) is performed by forming a protective film covering the side surface of the protruding portion.
[0014]
By forming the protective film, in the step (k), the protective film protects the side surface of the protruding portion, so that the upper end of the insulating layer is less likely to be recessed. As a result of suppressing the occurrence of the depression, a defect in the transistor characteristics, for example, an inverse narrow channel effect and a hump can be prevented. In addition, since the electrode material does not accumulate in the depression, the patterning of the gate electrode is performed well, and a short circuit can be prevented.
[0015]
(2) Second, mainly, a protective film is formed in step (d) and step (g). That is, except that the step (d) was added, the protective film was formed without including any special steps. Therefore, according to the present invention, a dense protective film can be easily formed.
[0016]
The ion implantation of the oxygen-based material in the step (d) is preferably performed under the following conditions from the viewpoint of forming a better protective film.
[0017]
The oxygen-based material is preferably oxygen or ozone. The energy is preferably ^{15 to} 30 keV, and the dose is preferably 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² . The angle between the surface of the stopper layer and the traveling direction of the ions of the oxygen-based material is preferably 45 to 80 degrees.
[0018]
The method of performing thermal oxidation in the step (g) can mainly include the following two thermal oxidation methods from the viewpoint of forming a better protective film.
[0019]
(1) First, there is a method of performing thermal oxidation in the presence of steam (hereinafter referred to as "wet oxidation"). This wet oxidation has an advantage that a short processing time is sufficient because the oxidation rate is high and the oxidation can be performed at a low temperature. The temperature of the thermal oxidation in the wet oxidation is preferably 800 to 950 ° C. in view of the controllability of the film thickness.
[0020]
(2) Second, a method of performing thermal oxidation in an atmosphere of oxygen or a mixed gas of oxygen and an inert gas (hereinafter referred to as “dry oxidation”). Although this dry oxidation requires oxidation at a high temperature, it has an advantage that the wet etching resistance of the buried oxide film can be improved, and depressions are less likely to occur. The temperature of the thermal oxidation in the dry oxidation is preferably 1000 to 1150 ° C. from the viewpoint of improving the wet etching resistance of the buried oxide film.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0022]
(Device structure)
A semiconductor device having a trench element isolation region obtained by the manufacturing method of the present invention will be described.
[0023]
FIG. 23 shows a semiconductor device (hereinafter, referred to as “semiconductor device”) 100 having a trench element isolation region obtained by the manufacturing method of the present invention.
[0024]
The semiconductor device 100 shown in FIG. 23 includes a trench element isolation region 23, an n-type MOS element 80, and a p-type MOS element 82.
[0025]
The trench element isolation region 23 is a region formed by filling the trench 16 provided in the silicon substrate 10 with the insulating layer 20. The trench element isolation region 23 has a role of isolating between MOS elements and defining an element region. With the trench element isolation region 23 as a boundary, a p-type retrograde well 32 is formed in one element region, and an n-type retrograde well 30 is formed in the other element region.
[0026]
An n-type MOS element 80 is formed on the p-type retrograde well 32, and a p-type MOS element 82 is formed on the n-type retrograde well 30.
[0027]
The n-type MOS device 80 has a gate oxide film 28, a gate electrode 46, and an n-type impurity diffusion layer 50.
[0028]
Gate oxide film 28 in n-type MOS element 80 is formed on p-type retrograde well 32. On this gate oxide film 28, a gate electrode 46 is formed. The gate electrode 46 includes a polycrystalline silicon layer 40 and a metal silicide layer 42 formed on the polycrystalline silicon layer 40. Then, a sidewall insulating film 70 is formed so as to cover the gate oxide film 28 and the side wall of the gate electrode 46.
[0029]
The n-type impurity diffusion layer 50 constitutes a source / drain region. The n-type impurity diffusion layer 50 includes a low-concentration n-type impurity diffusion layer 50a and a high-concentration n-type impurity diffusion layer 50b, and has an LDD structure.
[0030]
The p-type MOS element 82 has a gate oxide film 28, a gate electrode 46, and a p-type impurity diffusion layer 60.
[0031]
Gate oxide film 28 in p-type MOS element 82 is formed on n-type retrograde well 30. The details of the gate electrode 46 and the sidewall insulating film 70 are the same as those of the n-type MOS device 80.
[0032]
The p-type impurity diffusion layer 60 is the same as the n-type impurity diffusion layer 50 except that it is p-type.
[0033]
(Manufacturing process)
Next, a manufacturing process of the semiconductor device 100 shown in FIG. 23 will be described. 1 to 22 show the manufacturing process of the semiconductor device 100.
[0034]
(1) Formation of Trench and Protective Film First, description will be made with reference to FIG. A pad layer 12 is formed on a silicon substrate 10. The material of the pad layer 12 may be, for example, SiO ₂ , SiON, or the like. When the pad layer 12 is made of SiO _{2, the} pad layer 12 can be formed by a thermal oxidation method, a CVD method or the like, and when the pad layer 12 is made of SiON, it can be formed by a CVD method or the like. The thickness of the pad layer 12 is, for example, 5 to 20 nm.
[0035]
Next, the stopper layer 14 is formed on the pad layer 12. Examples of the stopper layer 14 include a silicon nitride layer, a multilayer structure of a silicon nitride layer and a polycrystalline silicon layer or an amorphous silicon layer, and a known method such as a CVD method. Can be mentioned. The stopper layer 14 has a thickness sufficient to function as a stopper in the subsequent CMP, for example, a thickness of 50 to 150 nm.
[0036]
On the stopper layer 14, a resist pattern R1 having a predetermined pattern is formed. The resist layer R1 is opened above a region where the trench 16 is to be formed.
[0037]
Next, as shown in FIG. 2, an oxygen-based substance is ion-implanted into the stopper layer 14 from an oblique direction with respect to the exposed surface of the stopper layer 14 using the resist layer R1 as a mask. By this ion implantation, an oxygen-based substance is implanted not only in the stopper layer 14 in the opening of the resist layer R1 but also in the region of the stopper layer 14 below the resist layer R1. The oxygen-based substances are oxygen and ozone. Regarding the conditions of the ion implantation, the energy is preferably 15 to 30 keV, more preferably 20 to 25 keV, and the dose is preferably 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² , more preferably 1 × 10 ¹⁵ to 2. It is 2 × 10 ¹⁵ cm ⁻² . The angle between the exposed surface of the stopper layer and the traveling direction of the ions of the oxygen-based material is preferably 45 to 80 degrees, more preferably 50 to 70 degrees.
[0038]
Next, as shown in FIG. 3, the stopper layer 14 and the pad layer 12 are etched using the resist layer R1 as a mask. This etching is performed by, for example, dry etching. In the case of dry etching, the etchant may be, for example, a mixed gas of Cl ₂ and O ₂ .
[0039]
An oxygen-based substance is ion-implanted into the end 14a of the stopper layer 14.
[0040]
Next, the resist layer R1 is removed by ashing. Next, as shown in FIG. 4, the silicon substrate 10 is etched using the stopper layer 14 as a mask to form a trench 16. The depth of the trench 16 varies depending on the device design, but is, for example, 300 to 500 nm. The etching of the silicon substrate 10 can be performed by dry etching.
[0041]
Although not shown, the end of the pad layer 12 interposed between the silicon substrate 10 and the stopper layer 14 is etched.
[0042]
Next, as shown in FIG. 5, the exposed surface of the silicon substrate 10 in the trench 16 is oxidized by a thermal oxidation method to form an oxide film (hereinafter, referred to as “trench oxide film”) 18.
[0043]
In this thermal oxidation, the oxygen resulting from the ion-implanted oxygen-based material promotes the oxidation of the end portion 14a of the stopper layer 14, so that the protective film 90 is formed.
[0044]
Further, since the edge of the pad layer 12 is etched, the upper edge of the silicon substrate 10 forming the trench 16 is oxidized and rounded by this thermal oxidation. When the upper edge portion of the silicon substrate 10 is rounded, a depression at an upper end portion of the insulating layer 20 described later is less likely to occur. The method of this thermal oxidation is not particularly limited, but wet oxidation (a method of thermal oxidation in the presence of water vapor) and dry oxidation (a method of thermal oxidation in an atmosphere of oxygen or a mixed gas of oxygen and an inert gas). preferable. Wet oxidation has the advantage of requiring a short processing time because the oxidation rate is high and oxidation at low temperatures is possible. Dry oxidation requires oxidation at a high temperature, but has the advantage that the wet etching resistance of the trench oxide film (buried oxide film) 18 can be improved, and depressions are less likely to occur. The temperature of the thermal oxidation in wet oxidation is preferably from 800 to 950 ° C., more preferably from 900 to 950 ° C., from the viewpoint of controllability of the film thickness. The temperature of the thermal oxidation in the dry oxidation is preferably from 1000 to 1150 ° C., more preferably from 1100 to 1150 ° C., from the viewpoint of improving the wet etching resistance of the trench oxide film (buried oxide film) 18. As the inert gas in the dry oxidation, for example, helium, neon, argon, krypton and the like can be mentioned.
[0045]
As shown in FIG. 6, an insulating layer 20 is deposited on the entire surface so as to fill the trench 16. The thickness of the insulating layer 20 is such that it fills the trench 16 and covers at least the stopper layer 14, for example, 500 to 800 nm. The material of the insulating layer 20 is made of, for example, silicon oxide. Examples of a method for depositing the insulating layer 20 include a high-density plasma CVD method, a thermal CVD method, and a TEOS plasma CVD method.
[0046]
Next, as shown in FIG. 7, the insulating layer 20 is planarized by a CMP method. This planarization is performed until the stopper layer 14 is exposed. That is, the insulating layer 20 is planarized using the stopper layer 14 as a stopper. Next, as shown in FIG. 8, the stopper layer 14 is removed using, for example, a hot phosphoric acid solution.
[0047]
Next, as shown in FIG. 9, the protrusion 22 and the protective film 90 are isotropically etched. At the time of this etching, the side surface of the protruding portion 22 is protected by the protective film 90, and the lateral etching is suppressed. As a result, a depression is less likely to occur at the upper end of the insulating layer 20. Therefore, the trench element isolation region 23 in which the insulating layer is satisfactorily embedded is formed. Examples of the etchant include an etchant containing hydrofluoric acid. During this etching, the pad layer 12 is also etched away.
[0048]
(2) Formation of Well Next, as shown in FIG. 10, a sacrificial oxide film 24 is formed on the exposed surface of the silicon substrate 10 by a thermal oxidation method. The thickness of the sacrificial oxide film 24 is, for example, 10 to 20 nm.
[0049]
Subsequently, a resist layer R2 having a predetermined pattern is formed on the surface of the insulating layer 20 filling the sacrificial oxide film 24 and the trench 16. The resist layer R2 is opened so that the surface of the region to be the n-well is exposed. Using the resist layer R2 as a mask, an n-type retrograde well 30 is formed in the silicon substrate 10 by injecting n-type impurities such as phosphorus and arsenic into the silicon substrate 10 one or more times. The retrograde well refers to a well having a well impurity concentration peak at a deep position in the silicon substrate 10.
[0050]
As shown in FIG. 11, a resist layer R3 is formed on the surface of the insulating layer 20 filling the sacrificial oxide film 24 and the trench 16. The resist layer R3 is opened so that the surface of the region to be the p-well is exposed. By using the resist layer R3 as a mask, a p-type impurity such as boron is implanted into the silicon substrate 10 one or more times to form a p-type retrograde well 32 in the silicon substrate 10.
[0051]
Next, as shown in FIG. 12, the sacrificial oxide film 24 is isotropically etched. At this time, if the protruding portion 22 and the protective film 90 still remain, the protruding portion 22 and the protective film 90 are also isotropically etched. Examples of the etchant include an etchant containing hydrofluoric acid.
[0052]
(3) Formation of Gate Electrode Next, as shown in FIG. 13, an oxide film 26 is formed on the device region defined by the trench device isolation region 23. Part of this oxide film 26 becomes a gate oxide film 28.
[0053]
As shown in FIG. 14, a polycrystalline silicon layer 40 is formed on insulating layer 20 and oxide film 26 by a CVD method or the like. The polycrystalline silicon layer 40 is doped.
[0054]
On the surface of the polycrystalline silicon layer 40, a metal silicide layer 42 is formed. Examples of the material of the metal silicide layer 42 include silicide such as tungsten, titanium, and molybdenum, and a method of forming the metal silicide layer 42 may include a stapling method.
[0055]
Thereafter, a silicon oxide layer 44 is formed on the surface of the metal silicide layer 42. As a method for forming the silicon oxide layer 44, for example, a CVD method or the like is given.
[0056]
As shown in FIG. 15, a resist layer R4 is formed on the silicon oxide layer 44 so as to cover a region where the gate electrode 46 is to be formed. Next, the silicon oxide layer 44 is etched using the resist layer R4 as a mask.
[0057]
Thereafter, as shown in FIG. 16, the resist layer R4 is removed by ashing.
[0058]
Next, as shown in FIG. 17, using the silicon oxide layer 44 as a mask, the metal silicide layer 42 and the polycrystalline silicon layer 40 are etched. Thus, a gate electrode 46 composed of the polycrystalline silicon layer 40 and the metal silicide layer 42 is formed.
[0059]
(4) Formation of Source / Drain As shown in FIG. 18, a resist layer R5 covering the n-type retrograde well 30 is formed. Using the resist layer R5 as a mask, phosphorus or the like is ion-implanted into the p-type retrograde well 32, and the low-concentration n-type impurity diffusion layer 50a constituting the source / drain region is formed in the p-type retrograde well 32. Form.
[0060]
After removing the resist layer R5, a resist layer R6 covering the p-type retrograde well 32 is formed as shown in FIG. Using the resist layer R6 as a mask, boron or the like is ion-implanted into the n-type retrograde well 30, and the low-concentration p-type impurity diffusion layer 60a forming the source / drain region is formed in the n-type retrograde well 30. Form.
[0061]
Next, after removing the resist layer R6, an insulating layer (not shown), for example, a silicon nitride film or a silicon oxide film is formed on the entire surface by a CVD method or the like. Next, as shown in FIG. 20, the insulating layer is anisotropically etched by reactive ion etching or the like to form a sidewall insulating film 70.
[0062]
Next, as shown in FIG. 21, a resist layer R7 covering the n-type retrograde well 30 is formed. Using the resist layer R7, the gate electrode 46, and the sidewall insulating film 70 as a mask, an impurity such as phosphorus is ion-implanted into the p-type retrograde well 32 to form a high-concentration n-type impurity diffusion layer 50b. I do. Thus, an n-type impurity diffusion layer 50 having an LDD structure is formed.
[0063]
Next, after removing the resist layer R7, a resist layer R8 covering the p-type retrograde well 32 is formed as shown in FIG. Using the resist layer R8, the gate electrode 46, and the sidewall insulating film 70 as a mask, an impurity such as boron is ion-implanted into the n-type retrograde well 30 to form a high-concentration p-type impurity diffusion layer 60b. I do. Thus, the p-type impurity diffusion layer 60 having the LDD structure is formed.
[0064]
Next, by ashing and removing the resist layer R8, the semiconductor device 100 according to the present embodiment as shown in FIG. 23 is completed.
[0065]
The present embodiment mainly has the following two features.
[0066]
(1) First, the protection film 90 covering the side surface of the protrusion 22 is formed, and the protrusion 22 is isotropically etched.
[0067]
By forming the protective film 90, in the step of isotropically etching the protruding portion 22, the protection film 90 protects the side surface of the protruding portion 22, so that the recess at the upper end of the insulating layer 20 is less likely to occur. Become. As a result of suppressing the occurrence of the depression, a defect in the transistor characteristics, for example, an inverse narrow channel effect and a hump can be prevented. Further, for example, when a gate electrode is formed, a problem such as accumulation of an electrode material at an upper end portion of the insulating layer 20 can be suppressed, so that a circuit short circuit does not easily occur.
[0068]
(2) Secondly, mainly, a step of ion-implanting an oxygen-based substance into the stopper layer 14 obliquely to the exposed surface of the stopper layer 14 and thermally oxidizing the exposed surface of the silicon substrate 10 in the trench 16. That is, the protective film 90 was formed in the steps. That is, the protective film 90 is formed without including a special process except that a process of implanting an oxygen-based material into the stopper layer 14 is added. Therefore, according to the method of the present embodiment, the dense protective film 90 can be easily formed.
[0069]
Further, the above-described embodiment can be variously modified without departing from the gist of the present invention.
[Brief description of the drawings]
FIG. 1 is a sectional view schematically showing steps of a method for manufacturing a semiconductor device according to an embodiment.
FIG. 2 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.
FIG. 3 is a cross-sectional view schematically showing steps of a method of manufacturing the semiconductor device according to the embodiment.
FIG. 4 is a cross-sectional view schematically showing steps of a method of manufacturing the semiconductor device according to the embodiment.
FIG. 5 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.
FIG. 6 is a cross-sectional view schematically showing a step of a method of manufacturing the semiconductor device according to the embodiment.
FIG. 7 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.
FIG. 8 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.
FIG. 9 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.
FIG. 10 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 11 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 12 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.
FIG. 13 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 14 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 15 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 16 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 17 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 18 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 19 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 20 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 21 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 22 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.
FIG. 23 is a cross-sectional view schematically showing a semiconductor device according to an embodiment.
FIG. 24 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.
FIG. 25 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.
FIG. 26 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.
FIG. 27 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.
FIG. 28 is a schematic cross-sectional view in which the depression in FIG. 27 is enlarged.
[Explanation of symbols]
Reference Signs List 10 silicon substrate 12 pad layer 14 stopper layer 16 trench 18 trench oxide film 20 insulating layer 22 protrusion 23 trench element isolation region 24 sacrificial oxide film 26 oxide film 28 gate oxide film 30 n-type retrograde well 32 p-type retrograde Well 40 polycrystalline silicon layer 42 metal silicide layer 44 silicon oxide layer 46 gate electrode 50 n-type impurity diffusion layer 50a low concentration n-type impurity diffusion layer 50b high concentration n-type impurity diffusion layer 60 p-type impurity diffusion layer 60a low concentration P-type impurity diffusion layer 60b high-concentration p-type impurity diffusion layer 70 sidewall insulating film 80 n-type MOS element 82 p-type MOS element 90 protective film 100 semiconductor device

Claims (9)

(A) forming a pad layer on a silicon substrate;
(B) forming a stopper layer for chemical mechanical polishing on the pad layer;
(C) forming a resist layer having a predetermined pattern on the stopper layer;
(D) ion-implanting an oxygen-based substance into the stopper layer from a direction oblique to the surface of the stopper layer using the resist layer as a mask;
(E) etching and patterning the stopper layer and the pad layer using the resist layer as a mask;
(F) using the stopper layer as a mask, etching the silicon substrate to form an element isolation groove;
(G) forming a protective film at an end of the stopper layer by thermal oxidation;
(H) forming an insulating layer filling the isolation trenches on the entire surface;
(I) a step of planarizing the insulating layer by a chemical mechanical polishing method using the stopper layer as a stopper;
(J) removing the stopper layer;
(K) projecting Ri by surface area element of the silicon substrate is formed, wherein a portion of the insulating layer, and etching said protective film to form a trench isolation region, and
The method of manufacturing a semiconductor device, wherein the step (d) is performed in a state where the pad layer and the stopper layer are formed above the silicon substrate on which the element isolation trench is formed. In claim 1,
The method of manufacturing a semiconductor device having a trench element isolation region, wherein the oxygen-based material in the step (d) is oxygen or ozone. In claim 1 or claim 2,
The method for manufacturing a semiconductor device having a trench element isolation region, wherein the conditions of the ion implantation in the step (d) are an energy of ^{15 to} 30 keV and a dose of 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² . In any one of claims 1 to 3,
The method of manufacturing a semiconductor device having a trench element isolation region, wherein the angle between the surface of the stopper layer and the traveling direction of the ions of the oxygen-based material in the step (d) is 45 to 80 degrees. In any one of claims 1 to 4,
The method of manufacturing a semiconductor device having a trench element isolation region, wherein the method of thermally oxidizing the stopper layer in the step (g) is a method of thermally oxidizing the stopper layer in the presence of water vapor. In claim 5,
A method for manufacturing a semiconductor device having a trench element isolation region, wherein the temperature of the thermal oxidation in the step (g) is 800 to 950 ° C. In any one of claims 1 to 4,
The method of manufacturing a semiconductor device having a trench element isolation region, wherein the method of thermally oxidizing the stopper layer in the step (g) is a method of performing thermal oxidation in an atmosphere of oxygen or a mixed gas of oxygen and an inert gas. . In claim 7,
The method of manufacturing a semiconductor device having a trench element isolation region, wherein the temperature of the thermal oxidation in the step (g) is 1000 to 1150 ° C. In any one of claims 1 to 8,
  Further comprising a step of etching an end of the pad layer between the step (f) and the step (g);
  A method for manufacturing a semiconductor device, wherein an upper edge portion of the element isolation groove is oxidized by the thermal oxidation in the step (g).

Images