JP3601428B2 - selector - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a selector, and in particular, to provide an effective selector when the circuit scale is large.
[0002]
[Prior art]
In recent years, with an increase in communication capacity, a switch circuit used for setting a communication line, bypassing a failed path, and the like has been increased in scale. One of the circuit elements constituting such switches is a selector. For example, in an SDH (Synchronous Digital Hierarchy) system, assuming a switch having an input capacity of 40 Gbps and an output capacity of 40 Gbps, and a switching unit of which is an STS (Synchronous Transfer Signal) -1 of a 52 Mbps pair of an SDH hierarchy, is configured. The number of switches is 40 Gbps / 52 Mbps = 768, and in this case, a 768 × 768 matrix switch is required.
[0003]
However, when the matrix switch is realized by an LSI, the selector occupies most of the area of the LSI (about 50 to 70%). Therefore, it is desirable that the circuit size of the selector is as small as possible. In addition, not only the circuit size of the selector section but also the number of wirings is an important factor, which directly affects the layout and occupation area of the LSI. Therefore, not only the circuit size but also the number of wirings are required to be small. . In addition, since the number of logic stages increases as the selector becomes larger, a design considering the processing speed is required. Therefore, realization of a selector having a small number of logic stages is desired.
[0004]
Considering the above example of the SDH system, as a method for efficiently realizing a 768 × 768 matrix switch by an LSI, a method using a 768 to 1 selector, a time division process, and multiplexing of an address signal to perform address selector multiplexing. Methods to reduce the number are conceivable. When time division processing is performed, for example, if 12 time division is performed, the number of selectors becomes 768/12 = 64, and the above system can be constructed with a 64-to-1 selector.
[0005]
FIG. 5 shows the configuration of the most general selector. FIG. 5 shows an example of an 8-to-1 selector. Reference numerals 50 to 56 denote 2-to-1 selectors, each of which is composed of a 2 × 2 input type AND-NOR circuit for selecting and outputting one of two inputs. ing. In general, in the case of an 8-to-1 selector, 8 has a relationship of 2 to the power of 3, so that 6 address input signals are required to select and output 1 input, but 3 address input signals b2 and b1 , B0 are generated as complementary address signals by inverters 57 to 59 and supplied to two-to-one selectors 50 to 56.
[0006]
There is also a method of realizing a large-scale matrix switch by optimizing from the transistor level without using a general selector as shown in FIG. FIG. 6 shows a cross-point switch circuit and a semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 8-65719 as a conventional technique using this method.
[0007]
FIG. 6 is a configuration diagram of a cross point switch in which the configuration of the input terminal and the output terminal is 4 * 4. In FIG. 6, I1 to I4 are input terminals, O1 to O4 are output terminals, Q1 (1) to Q6 (1), Q1 (2) to Q6 (2), Q1 (3) to Q6 (3) and Q1 ( 4) to Q6 (4) are NMOS transistors, which constitute switches and decoder unit units 1 (1) to 1 (4), respectively.
[0008]
Further, IV1 (1) to IV4 (1), IV1 (2) to IV4 (2), IV1 (3) to IV4 (3) and IV1 (4) to IV4 (4) are inverters, NI1 (1), NI2 (1), NI1 (2), NI2 (2), NI1 (3), NI2 (3), NI1 (4), and NI2 (4) are non-inverters, and IV1 (1) to IV4 (1) and NI1 (1), NI2 (1), IV1 (2) to IV4 (2) and NI1 (2), NI2 (2), IV1 (3) to IV4 (3) and NI1 (3), NI2 (3) and IV1 (4) to IV4 (4), NI1 (4), and NI2 (4) constitute address buffer unit units 2 (1) to 2 (4), respectively.
[0009]
FIG. 7 is a configuration diagram of the cross point switch in the case where the number of outputs is set to 2 with respect to 4 inputs, and the number of outputs is set to の of the number of inputs. The same parts as those in FIG. 6 are denoted by the same reference numerals. In FIG. 7, reference numerals 5a to 5d denote multiplexing unit units, and address signals A1 (1) and A1 (2), A2 (1) and A2 (2), A1 (3) and A1 (4), A2 (3) ) And an address signal multiplexing circuit for performing time division multiplexing at twice the frequency of A2 (4), and multiplexed address signals A1 [1], A2 [1], A1 [2], A2 [ 2] are output.
[0010]
According to the method of FIG. 7, in order to realize a function equivalent to the 4 * 4 cross point switch of FIG. 6, the address signals A1 (1), A1 (2), A2 (1), A2 (2), A1 (3), A1 (4), A2 (3) and A2 (4) are operated at twice the input signal frequency, and outputs A1 [1], A2 [1], A1 [2] and A2 [2] It is output in a form multiplexed at twice the frequency of the input signal.
[0011]
FIG. 8 is a logical configuration diagram of the multiplexing unit unit 5a in FIG. 7, and FIG. 9 is a timing chart of the cross point switch in FIG. In FIG. 7, the multiplexing unit 5a multiplexes the address signals A1 (1) and A1 (2), and the multiplex logic shown in FIG. (1) is passed, AND2 is passed during the low level period of the switching pulse MP, and AND2 is passed, and OR1 is the logical sum of AND1 and AND2 to output the multiplexed address signal A1 [1]. It is configured.
[0012]
Next, the operation of the cross point switch of FIG. 7 will be briefly described with reference to FIGS. The description of the operation of the switches and the decoder unit units 1 (1) and 1 (2) in FIG. 7 is omitted.
[0013]
In FIG. 9, multiplexed address signals A1 [1] and A2 [1] sequentially select input terminals I3, I2, I1, I3,... In synchronization with a change in the level of the switching pulse MP. [2] and A2 [2] sequentially select the input terminals I4, I1, I2, I4... In synchronization with the level change of the switching pulse MP. At this time, the input from I3, I2, I1, I3... Is sequentially output to the output terminal O1, and the input from I4, I1, I2, I4. You.
[0014]
That is, in the cross point switch of FIG. 7, the output signal is output in two cycles during one cycle of the input signal by performing the time division multiplexing, so that the switch and the decoder unit 1 (3), 1 in FIG. (4) The cross-point switch is configured by reducing the physical circuit scale.
[0015]
[Problems to be solved by the invention]
However, in the above-described conventional cross point switch of FIG. 7, the clock signal is inevitably required because the address signal is time-division multiplexed to reduce the number of elements. That is, when the time-division multiplexing method is used as a measure for reducing the circuit scale of a large-scale matrix switch, the required clock frequency is determined by the number of divisions. It is an effective means. However, since the required clock frequency is special depending on the number of divisions, it is difficult to generate it, and there is a limit depending on the performance of the device, so it is not necessarily effective as a measure to reduce the circuit scale of large matrix switches. Absent.
[0016]
Further, in the conventional cross point switch of FIG. 7, since the circuit from the transistor level constituting the switch is also optimized at the same time, minimization of the transistor itself and the like are necessary to realize a large-scale cross point switch. Various approaches can be applied.
[0017]
On the other hand, with the progress of LSI process technology, device performance such as circuit accommodation scale and power consumption has been remarkably improved. Therefore, there is an idea that a design once is reused as an IP (Intellectual Property). Specifically, from the viewpoint of macro registration in-house, sharing of design and core design, it is more realistic to reduce the circuit size of the matrix switch by designing at the gate level using a general basic selector. It is suitable, and is effective in many cases in consideration of reduction of development cost and development period.
[0018]
Therefore, the present invention has been made to solve such a problem, and an object of the present invention is to provide a large-scale selector having a small number of logic stages and a small number of wirings, a small circuit scale, and low power consumption. It is in.
[0019]
[Means for Solving the Problems]
According to the present invention, there is provided a selector for selecting one of eight input signals in accordance with an address input, wherein the selector is selectively activated in accordance with a combination pattern of upper two bits of the address input. Address decoding means for generating first to fourth selection control signals; first and second two-to-one signals which receive two of the input signals as inputs and are selectively controlled by the first and second selection control signals Selector means; third and fourth two-to-one selector means which also receives two of the input signals as inputs and is selectively controlled by the third and fourth selection control signals; and the first to fourth two-to-one selector means. And a four-to-one selector means which takes four outputs of the one-to-one selector means as inputs and selectively selects according to a pattern of a third bit from the upper bit of the address input. Can be
[0020]
Further, according to the present invention, there is provided a selector for selecting one of eight input signals in accordance with an address input, wherein the most significant bit of the address input and the positive and negative phases of the second bit from the upper bit. Means for respectively generating two signals of the input signals, and first and second signals selectively controlled by the positive and negative phase signals of the most significant bit and the positive phase signal of the second bit. A two-to-one selector means, which receives two of the input signals as input, and selectively controls the positive and negative phase signals of the most significant bit and the negative phase signal of the second bit to control the third and fourth signals; Four-to-one selector means and four-to-one selector which selects four outputs of the first to fourth two-to-one selector means as inputs and selectively selects according to a pattern of the third bit from the upper bit of the address input. Selector means; Selector is obtained characterized by.
[0021]
According to the present invention, there is provided a selector for selecting one of n input signals (n is a multiple of 8 and excluding 1) in accordance with an address input, wherein Address decoding means for generating first to fourth selection control signals which are selectively activated according to a 2-bit combination pattern; and the first and second input signals each having two input signals as inputs. First and second two-to-one selector means selectively controlled by a selection control signal; third and fourth two-to-one selector means selectively controlled by the third and fourth selection control signals; , The four outputs of the fourth 2-to-1 selector means are used as inputs, and a set of 4-to-1 selector means for selectively selecting according to the pattern of the third bit from the upper bit of the address input is set as n / Eight selector arrays, Selector means for receiving n / 8 outputs of the selector array as inputs and selecting n / 16 lines in accordance with the pattern of the fourth bit from the higher order of the address input. .
[0022]
Further, according to the present invention, there is provided a selector for selecting one of n input signals (n is a multiple of 8 and excluding 1) in accordance with an address input, Means for respectively generating a positive-phase signal and a negative-phase signal of a second bit from an upper bit and an upper bit, and inputting each of the two input signals as input, the positive- and negative-phase signals of the most significant bit and the second bit First and second two-to-one selector means selectively controlled by the positive-phase signal of the input signal, similarly receiving two of the input signals as inputs, the positive- and negative-phase signals of the most significant bit and the second bit, respectively. The third and fourth 2-to-1 selector means selectively controlled by the negative-phase signal, the third output from the first to fourth 2-to-1 selector means as inputs, and the third bit from the upper bit of the address input. Select according to the pattern of N / 8 sets of selector arrays each having a 4: 1 selector means, and n / 16 outputs of the selector arrays as inputs, and n / 16 sets according to the pattern of the fourth bit from the upper bit of the address input. And a selector unit for selecting a book.
[0023]
The two-to-one selector means includes two AND circuits each having two input signals as one input and the selection control signal as another input, and each output of these AND circuits having two inputs. And a NOR circuit that performs the operation.
[0024]
The two-to-one selector means includes two AND circuits each of which receives two of the input signals as one input and receives the positive and negative phase signals of the most significant bit as other inputs. A NOR circuit that uses each output of the circuit as first and second inputs and uses the positive-phase or negative-phase signal of the second bit from the higher order as a third input, respectively.
[0025]
The operation of the present invention will be described. When the scale of the selector is large, for example, when configuring an 8: 1 selector, four 2: 1 selectors are arranged in the first column, and one 2: 1 selector is arranged in the second column. The upper two bits of the address input are combined, and two of the selector inputs in the first column are selected according to the four control signals obtained by the address decoder. Next, one of the two inputs is selected and output by the third bit from the upper bit of the address input. Thus, the number of logic stages can be reduced without increasing the number of address inputs, and a selector having a small circuit size can be obtained. In particular, in an n (n is a multiple of 8) to 1 selector, the larger the value of n, the more the circuit reduction effect is exhibited.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a circuit diagram of an 8: 1 selector as one embodiment of the present invention. Referring to FIG. 1, the 8-to-1 selector according to the present invention includes a 2-to-1 selector 1 to 4 in a first column, a 2-to-1 selector 5 in a second column, and an address input signal b2 of the selectors 1 to 5. , B1, b0 and a two-to-four decoder 6 for generating address control signals B4, B3, B2, B1 by a combination of b2, b1, which are the upper two bits of the address input signal.
[0027]
The selector 1 receives the input signals 7 and 6, the selector 2 receives the input signals 5 and 4, the selector 3 receives the input signals 3 and 2, and the selector 4 receives the input signals 1 and 0, respectively. Has been entered. The selectors 1 and 3 receive the address control signals B4 and B3, and the selectors 2 and 4 receive the address control signals B2 and B1, respectively. Further, the output selected by the selectors 1 to 4 is input to the selector 5, and the input of 1 is selected by a complementary signal of the inverter 37 of the third highest-order address input signal b0.
[0028]
Next, the operation of the 8: 1 selector shown in FIG. 1 will be described in detail. In FIG. 1, in selecting the input signals 7 to 0 input to the selectors 1 to 4, a logical operation is performed on the address input signals b2 and b1 by using the 2-to-4 decoder 6, and B4, B3, B2 and B1 are calculated. The selector operation is performed by generating four address control signals and controlling the addresses of the selectors 1 to 4 using the address control signals.
[0029]
For example, when the address input signal is b2 = 1, b1 = 1, and b0 = 1, b2 = 1 and b1 = 1, so that the outputs of the 2-to-4 decoder 6 are B4 = 1, B3 = 0, and B2 = 0, B1 = 0. That is, since the address control signal B4 = 1, two signals of the input signal 7 and the input signal 3 are selected by the selectors 1 and 3 based on the address input signals b2 and b1. These two signals are input to the selector 5, and furthermore, since the address input signal b0 = 1, the input signal 7 is finally selected and output.
[0030]
Hereinafter, by considering the combination of the address input signals b2 and b1 by the same procedure,
When b2 = 0 and b1 = 1, B3 = 1 (B1 = B2 = B4 = 0), and the input signal 6 and the input signal 2 are selected.
When b2 = 1 and b1 = 0, B2 = 1 (B1 = B3 = B4 = 0), and the input signal 5 and the input signal 1 are selected.
When b2 = 0 and b1 = 0, B1 = 1 (B2 = B3 = B4 = 0), and the input signal 4 and the input signal 0 are selected.
Eventually, two of the eight input signals are selected by the selectors 1 to 4. Further, since one input signal is selected according to the value of the address input signal b0, the eight-to-one selector finally selects an arbitrary one input signal.
[0031]
FIG. 2 shows a circuit diagram of a 64-to-1 selector in which eight 8-to-1 selectors shown in FIG. The same parts as those in FIG. 1 are indicated by the same reference numerals. In FIG. 2, 11 to 18 are 8-to-1 selectors, 21 to 27 are 2-to-1 selectors, and 28 is a logic matching inverter. In the case of FIG. 2, 64 has a relationship of 2 to the power of 6, so that 12 address input signals are required to select and output one input. The two-to-one selectors 1 to 4 in the first column and the two-to-one selector 5 in the second column that constitute the eight-to-one selectors 11 to 18 have the same configuration as the eight-to-one selector in FIG.
[0032]
Next, the operation of the 64-to-1 selector of FIG. 2 will be described. The two-to-four decoder 6 performs a logical operation on the upper two bits b5 and b4 of the address input signal, and the address control signals B4, B3, B2 and B1 are commonly input to the selectors in the first column.
[0033]
In the second column, the third highest-order address input signal b3 is commonly input as a complementary signal, and the two-to-one selectors 1 to 28 of the eight-to-one selectors 21 to 28 forming the 64-to-1 selector are used. One of the two signals selected from 4 is selectively output. After that, the outputs of the 8: 1 selectors 11 and 12 are selected by the 2: 1 selector 21 using the complementary signal of the address input signal b2 from among the 1 signals selected for each of the 8: 1 selectors 11-18, and the 8: 1 The outputs of the 1 selectors 13 and 14 are selected by the 2: 1 selector 22, the outputs of the 8: 1 selectors 15 and 16 are selected by the 2: 1 selector 23, and the outputs of the 8: 1 selectors 17 and 18 are selected by the 2: 1 selector 24, respectively. Output. The four signals thus obtained are similarly selected by the two-to-one selectors 25, 26 and 27 using complementary signals of the address input signals b1 and b0, and finally one signal is passed through the logic matching inverter 28. Selected output.
[0034]
Here, the number of gates is compared and calculated between the case where the 64-to-1 selector is configured by the 8-to-1 selector according to the present invention and the conventional case of a general selector as shown in FIG. In the case of a two-to-four decoder according to the present invention, the number of gates in the first column of the 64-to-1 selector is determined by the selector section.
2 × 2 input type AND-NOR gates * 4 * 8 stages = 2 gates * 4 * 8 = 64 gates,
2 input AND gates * 4 = 2 gates * 4 = 8 gates, inverter * 2 = 1 gate * 2 = 2 gates.
[0035]
The number of gates in the second column is determined by the selector unit.
3x2 input type AND-NOR gate * 1 * 8 stages = 3 gates * 1 * 8 = 24 gates, address input section
Inverter * 1 = 1 gate * 1 = 1 gate.
[0036]
Further, the number of gates in the third column is determined by the selector unit.
2 × 2 input type AND-NOR gates * 4 = 2 gates * 4 = 8 gates, and the address input section is
Inverter * 1 = 1 gate * 1 = 1 gate.
[0037]
The number of gates in the fourth column is determined by the selector unit.
2 × 2 input type AND-NOR gates * 2 = 2 gates * 2 = 4 gates, and the address input section is
Inverter * 1 = 1 gate * 1 = 1 gate.
[0038]
The number of gates in the fifth column is determined by the selector unit.
2 × 2 input type AND-NOR gate * 1 = 2 gates * 1 = 2 gates, and the address input section is
Inverter * 1 = 1 gate * 1 = 1 gate.
[0039]
Finally, as a logic matching inverter
Inverter x 1 = 1 gate * 1 = 1 gate, and the total number of gates constituting the 64-to-1 selector of the present invention is 117 gates.
On the other hand, when a general selector as shown in FIG. 5 is used, the number of gates in the first column is calculated by referring to FIG.
2 × 2 input type AND-NOR gates * 4 * 8 stages = 2 gates * 4 * 8 = 64 gates, address input section
Inverter * 1 = 1 gate * 1 = 1 gate.
[0040]
The number of gates in the second column is determined by the selector unit.
2 × 2 input type AND-NOR gates * 2 * 8 stages = 2 gates * 2 * 8 = 32 gates, and the address input section is
Inverter * 1 = 1 gate * 1 = 1 gate.
[0041]
Further, the number of gates in the third column is determined by the selector unit.
2x2 input type AND-NOR gate * 1 * 8 stages = 2 gates * 1 * 8 = 16 gates, address input section
Inverter * 1 = 1 gate * 1 = 1 gate.
[0042]
The number of gates in the fourth column is determined by the selector unit.
2 × 2 input type AND-NOR gates * 4 = 2 gates * 4 = 8 gates, and the address input section is
Inverter * 1 = 1 gate * 1 = 1 gate.
[0043]
The number of gates in the fifth column is determined by the number of selectors.
2 × 2 input type AND-NOR gates * 2 = 2 gates * 2 = 4 gates, and the address input section is
Inverter * 1 = 1 gate * 1 = 1 gate.
[0044]
Finally, the number of gates in the sixth column is
2 × 2 input type AND-NOR gate * 1 = 2 gates * 1 = 2 gates, and the address input section is
Inverter * 1 = 1 gate * 1 = 1 gate, and when a general selector is used, the total number of gates constituting the 64-to-1 selector is 132 gates.
[0045]
Therefore, if the 2-to-4 decoder according to the present invention is used, the number of gates of the 64-to-1 selector is 117/132 = 0.89, and an effect of reducing the number of gates by about 11% can be obtained.
[0046]
FIG. 3 shows a circuit diagram of an 8: 1 selector using an output enable function as another embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description of those parts will be omitted. In FIG. 3, reference numerals 30 to 33 denote 2 × 3 input type AND-NOR circuits, which constitute a 2: 1 selector. An address input signal b2 is input to one of the addresses of the selectors 30 to 33, and an inverted signal of the address input signal b2 is input to the other.
[0047]
The address input signal b1 is input to the three-input NOR circuits in the selectors 30 and 32, and the inverted signal of the address input signal b1 is input to the three-input NOR circuits in the selectors 31 and 33, respectively. The input signals 7 to 0 are input to the selectors 30 to 33 as in the case of FIG. 1 of the above embodiment. Reference numerals 35 to 37 denote inverters, which generate inverted signals of the address input signals b2, b1, and b0.
[0048]
Next, the operation of the 8: 1 selector shown in FIG. 3 will be briefly described. One of the inputs 7, 5, 3, 1 or the inputs 6, 4, 2, 0 is selected in the selectors 30 to 33 by the address signal b2 or its inverted signal. Of the four signals, the outputs of the selectors 30 and 32 or the outputs of the selectors 31 and 33 are selected by the address signal b1 or its inverted signal, and these two signals are finally selected by using the complementary signal of the address signal b0. Selectively output signals.
[0049]
In other words, the 8: 1 selector of FIG. 3 employs the configuration of the 2: 1 selectors 30 to 33 in the first column as a 2 × 3 input type AND-NOR circuit, which is shown in FIG. 1 of the above embodiment. This is to reduce the number of selector circuits without using a 2-to-4 decoder. As described above, when the selectors 30 to 33 having the output enable function are prepared in advance, the effect of reducing the number of gates can be obtained by using the selectors.
[0050]
FIG. 4 shows still another embodiment of the present invention. FIG. 4 is a circuit diagram of an 8-to-1 selector having the same function as that of FIG. 3 when the output enable function is not provided as a selector. 1 and 3 are denoted by the same reference numerals. 4 differs from FIG. 3 in that the address input signal b1 is supplied to the 2-input and 1-output AND circuits in the 2-to-1 selectors 40 and 42, and the address is supplied to the 2-input and 1-output AND circuits in the 2-to-1 selectors 41 and 43. The input of the three-input one-output NOR circuit is obtained by inputting the inverted signal of the input signal b1. Even with such a 2 × 3 AND-NOR circuit configuration, an output enable function can be realized, and an effect of reducing the number of gates can be obtained.
[0051]
In configuring the selector circuit, the method using the output enable function shown in FIGS. 3 and 4 and the method using the 2-to-4 decoder shown in FIG. 1 can be used together. By using these two methods together, options for minimizing the circuit scale and the number of logic stages are expanded, and a more optimal circuit can be configured.
[0052]
It is apparent that the present invention is not limited to the above-described embodiment, but can be appropriately modified within the scope of the technical idea of the present invention. For example, in the above embodiment, the address control signal obtained by the 2-to-4 decoder is input only to the selector in the first column to reduce the circuit size. , Can be widely applied to selectors in the second and subsequent columns.
[0053]
In addition, since the size of each basic gate, that is, the number of gates, differs depending on the manufacturer and the LSI process to be used, it is also necessary to consider this point and determine the number of columns in which a 2-to-4 decoder is most effective for reducing the circuit size. It is good to apply. Further, the address decoder is not limited to an AND circuit, and can be widely applied to circuits such as NAND, OR, and NOR if the logic is devised.
[0054]
Further, in the above-described embodiment, the AND-NOR type circuit is described as the configuration of the two-to-one selector. Obviously, any configuration is applicable.
[0055]
Also, in the example of FIG. 2, a 64-to-1 selector that receives 64 input signals 0 to 63 is shown, but in general, n (n is a multiple of 8 and excluding 1) is 1: 1. Applicable to selectors. Further, instead of the address decoder 6 in FIG. 2, a circuit using a positive-phase signal and a negative-phase signal which are complementary signals of the upper two bits shown in FIGS.
[0056]
【The invention's effect】
As described above, according to the present invention, by controlling the address of the selector using the signal obtained by combining the upper two bits of the address input, the number of logic stages of the selector can be increased without increasing the number of address input signals at all. Can be reduced. Therefore, when the matrix switch is implemented by an LSI, if the circuit size reduction measure of the present invention is applied to the n-to-1 selector, it is necessary to add an AND circuit to the 2-to-4 decoding unit, but the number is four. And is independent of n. Therefore, as n is larger, the circuit size of the selector unit can be made smaller, and the effects of reducing power consumption and increasing processing speed in proportion to the amount of circuit size reduction can be obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an 8-to-1 selector of the present invention.
FIG. 2 is a circuit diagram in which an 8-to-1 selector of the present invention is applied to a 64-to-1 selector.
FIG. 3 is a circuit diagram of an 8: 1 selector according to another embodiment of the present invention.
FIG. 4 is a circuit diagram of an 8: 1 selector according to still another embodiment of the present invention.
FIG. 5 is a configuration diagram of the most general selector.
FIG. 6 is a configuration diagram of a conventional cross point switch.
FIG. 7 is a configuration diagram of a conventional time-division multiplexed cross point switch.
FIG. 8 is a logical configuration diagram of a conventional multiplexing unit.
FIG. 9 is a timing chart of a conventional time-division multiplexed cross point switch.
[Explanation of symbols]
1-4, 21-27 2-to-1 selector (2 × 2 input type AND-NOR circuit)
5 2: 1 selector (3 × 2 input type AND-NOR circuit)
6 2 to 4 decoder
11-18 8-to-1 selector
28 Logic matching inverter
37 Inverter

Claims (6)

A selector for selecting one of the eight input signals according to an address input,
Address decoding means for generating first to fourth selection control signals selectively activated according to a combination pattern of the upper two bits of the address input;
First and second two-to-one selector means which receives two of the input signals as inputs and is selectively controlled by the first and second selection control signals; Third and fourth two-to-one selector means selectively controlled by third and fourth selection control signals;
A 4-to-1 selector which receives four outputs of the first to fourth 2-to-1 selectors as inputs, and selectively selects according to a pattern of a third bit from a higher order of the address input;
A selector comprising: A selector for selecting one of the eight input signals according to an address input,
Means for respectively generating the most significant bit of the address input and the positive and negative phase signals of the second bit from the upper bit;
First and second two-to-one selectors, each of which receives two of the input signals as inputs and is selectively controlled by the positive and negative phase signals of the most significant bit and the positive phase signal of the second bit; Third and fourth two-to-one selectors, each of which receives two input signals as input and is selectively controlled by the positive and negative phase signals of the most significant bit and the negative phase signal of the second bit;
A 4-to-1 selector which receives four outputs of the first to fourth 2-to-1 selectors as inputs, and selectively selects according to a pattern of a third bit from a higher order of the address input;
A selector comprising: a selector for selecting one of n input signals (n is a multiple of 8 and excluding 1) according to an address input;
Address decoding means for generating first to fourth selection control signals selectively activated according to a combination pattern of the upper two bits of the address input;
First and second two-to-one selector means which receive two of the input signals as inputs and are selectively controlled by the first and second selection control signals, and selection control by the third and fourth selection control signals And the four outputs of the first to fourth two-to-one selectors are selected as inputs and selected according to the pattern of the third bit from the higher-order address input. N / 8 sets of selector arrays in which a set of four-to-one selector means for selecting one is provided;
Selector means for receiving n / 8 outputs of the selector array as inputs and selecting n / 16 outputs in accordance with a pattern of the fourth bit from the higher order of the address input;
A selector comprising: a selector for selecting one of n input signals (n is a multiple of 8 and excluding 1) according to an address input;
Means for respectively generating the most significant bit of the address input and the positive and negative phase signals of the second bit from the upper bit;
First and second two-to-one selectors, each of which receives two of the input signals as input and is selectively controlled by the positive and negative phase signals of the most significant bit and the positive phase signal of the second bit; Third and fourth two-to-one selectors, each of which receives two input signals as inputs and is selectively controlled by the positive and negative phase signals of the most significant bit and the negative phase signal of the second bit; , The four outputs of the fourth 2-to-1 selector means are used as inputs, and a set of 4-to-1 selector means for selectively selecting according to the pattern of the third bit from the upper bit of the address input is set as n / Eight selector arrays,
Selector means for receiving n / 8 outputs of the selector array as inputs and selecting n / 16 outputs in accordance with a pattern of the fourth bit from the higher order of the address input;
A selector comprising: The two-to-one selector means includes two AND circuits each having one of the two input signals as one input and another input of the selection control signal, and a NOR circuit having two outputs each of the AND circuits. 4. The selector according to claim 1, further comprising a circuit. The two-to-one selector means includes two AND circuits each of which receives two of the input signals as one input and receives the positive-phase and negative-phase signals of the most significant bit as other inputs, respectively. 5. The NOR circuit according to claim 2, further comprising: a NOR circuit that uses each output as first and second inputs and uses the positive-phase or negative-phase signal of the second bit from the higher order as a third input. The described selector.

Images