JP3602463B2 - Method for manufacturing transistor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a MIS transistor. In particular, the present invention improves the crystallinity by irradiating a semiconductor with laser or equivalent strong light such as laser annealing or lamp annealing after introducing impurities into a semiconductor region by irradiating fast ions. About the method.
[0002]
[Prior art]
A structure in which a thin insulating film (I) and a control (metal) electrode (M) are provided on a semiconductor (S) is called an MIS structure, and a transistor that controls a current flowing through a semiconductor by such a structure is called an MIS transistor. . When a silicon oxide film is used as the insulating film, it is called a MOS transistor.
[0003]
Conventionally, in such a MIS transistor, an activation step after impurity introduction (that is, a step of recovering a crystal defect generated at the time of impurity introduction) is performed by thermal annealing. Needed. In recent years, in response to a demand for lowering the temperature of the process, a method that replaces such thermal annealing at a high temperature has been studied. Among them, a prominent method is a method of activating by irradiating strong light such as a laser, and is called laser annealing or lamp annealing depending on a light source to be used.
[0004]
An example of manufacturing a MIS transistor using conventional laser annealing will be described with reference to FIGS. A base insulating film 302 is deposited on a substrate 301, a substantially intrinsic crystalline semiconductor film is further deposited, and this is patterned to form an island-shaped semiconductor region 303. Then, an insulating film 304 functioning as a gate insulating film is deposited, and further, a gate electrode 305 is formed. (FIG. 3 (A))
[0005]
If necessary, the gate electrode is anodized to form anodic oxide 306 on the top and side surfaces of the gate electrode and wiring. The method of forming such an anodic oxide and its merits are described in detail in Japanese Patent Application Nos. 4-30220, 4-34194, 4-38637 and the like. Of course, it is needless to say that such an anodic oxidation step may not be used if unnecessary. (FIG. 3 (B))
After that, impurity doping is performed by an ion implantation method or an ion (plasma) doping method. That is, the substrate is placed in a high-speed ion stream, and impurities are implanted in a self-aligned manner into the island-shaped semiconductor region 303 using the gate electrode portion, that is, the gate electrode and the surrounding anodic oxide as a mask. 307 is formed. (FIG. 3 (C))
[0006]
Further, the semiconductor region is irradiated with intense light such as laser light to recover the crystallinity of the semiconductor region whose crystallinity has been deteriorated by the previous impurity implantation step. (FIG. 3 (D))
Thereafter, an interlayer insulator 308 is deposited, contact holes are provided in the interlayer insulator 308, and source and drain electrodes 309 are formed and completed. (FIG. 3 (E))
[0007]
[Problems to be solved by the invention]
In the above method, it is preferable that the thickness of the gate insulating film be large in order to improve the breakdown voltage of the gate insulating film of the transistor. However, this requires simultaneously increasing the acceleration voltage of the impurity ions and extending the doping time. In particular, when a shallow impurity region is formed, a monochromatic ion beam having extremely uniform energy is required, but the dose per unit time is significantly reduced.
[0008]
On the other hand, if the gate insulating film is removed and the semiconductor surface is exposed in order to perform doping efficiently, the surface becomes rough when activated by irradiating strong light such as laser light, which may cause contact failure. became. The present invention has been made in view of such a problem, and provides a method for efficiently performing doping and laser activation.
[0009]
[Means for Solving the Problems]
In the present invention, an insulating film formed as a gate insulating film is etched in a self-aligned manner using a gate electrode portion as a mask to reduce the thickness to a level that allows ions of appropriate energy to pass therethrough. Introduce to the area. Thereafter, annealing is achieved by irradiating laser irradiation or strong light equivalent thereto. Prior to laser irradiation, a transparent insulating film may be formed on the semiconductor surface. By adopting such a method, doping efficiency does not decrease as mentioned above, and doping and subsequent activation can be achieved very efficiently.
[0010]
【Example】
Embodiment 1 FIG. 1 shows this embodiment. A silicon oxide film having a thickness of 100 nm is deposited as a base insulating film 102 on a non-alkali glass substrate 101 such as Corning 7059 or the like, and a substantially intrinsic amorphous silicon semiconductor film (having a thickness of 150 nm) is deposited. This was crystallized by annealing for 12 hours. This was patterned to form an island-shaped semiconductor region 103. Then, a silicon oxide film 104 having a thickness of 120 nm was deposited as a gate insulating film, and a gate electrode 105 was formed using aluminum having a thickness of 600 nm. (Fig. 1 (A))
[0011]
Thereafter, the gate electrode was anodized to form an anodic oxide 106 on the top and side surfaces of the gate electrode and wiring. The method of forming such an anodic oxide and the merits thereof are described in detail in JP-A-4-30220, JP-A-4-34194, and JP-A-4-38637. Of course, it is needless to say that such an anodic oxidation step may not be used if unnecessary. (FIG. 1 (B))
[0012]
After that, the gate insulating film was etched by a dry etching method. Carbon tetrafluoride or the like was used as an etching gas. At this time, the anodic oxide (alumina) was not etched, and as a result, portions of the gate insulating film other than those present below the gate electrode portion (the gate electrode 105 and the anodic oxide 106) were etched. Etching was interrupted when the gate insulating film 104 became 50 nm, and a thin insulating film 107 was formed. Then, by irradiating a phosphorus / hydrogen plasma stream accelerated to 15 to 50 keV, for example, 30 keV, phosphorus is implanted into the island-shaped semiconductor region 103 in a self-aligned manner, thereby forming an impurity region (to become a source and a drain) 108. . (Fig. 1 (C))
[0013]
Then, KrF excimer laser light (wavelength: 248 nm) was irradiated to recover the crystallinity of the semiconductor region 108 whose crystallinity was deteriorated by the previous impurity implantation step. At this time, the energy density of, 150~300mJ / cm ^2, for example, was 200 mJ / cm ^2. (Fig. 1 (D))
Thereafter, an interlayer insulator 109 was deposited, a contact hole was provided in the interlayer insulator 109, and source and drain electrodes 110 were formed to complete the process. Through the above steps, an N-channel transistor was formed (FIG. 1E).
[0014]
Similarly, a P-channel transistor can be formed. If a known CMOS technology is used, an N-channel transistor and a P-channel transistor can be mixedly mounted on the same substrate. For example, a typical mobility of a MOS transistor fabricated by the method described in this Example was 80 cm ² / Vs at 120 cm ² / Vs, P-channel type N-channel type. In addition, in a CMOS shift register (5 stages) manufactured by forming an N-channel transistor and a P-channel transistor on the same substrate, 15 MHz synchronization was confirmed at a drain voltage of 20 V.
[0015]
Embodiment 2 FIG. 2 shows this embodiment. A silicon oxide film having a thickness of 100 nm is deposited as a base insulating film 202 on a non-alkali glass substrate 201, and a substantially intrinsic amorphous silicon semiconductor film (thickness: 50 nm) is further deposited by a known laser annealing method. Was crystallized. This was patterned to form an island-shaped semiconductor region 203. Then, a silicon oxide film 204 having a thickness of 120 nm was deposited as a gate insulating film, and a gate electrode 205 was formed using aluminum having a thickness of 600 nm. Thereafter, the gate electrode was anodized to form an anodic oxide 206 on the top and side surfaces of the gate electrode and wiring. (Fig. 2 (A))
[0016]
After that, the gate insulating film was etched by a dry etching method. Carbon tetrafluoride or the like was used as an etching gas. At this time, the anodic oxide (alumina) was not etched, and as a result, portions of the gate insulating film other than those under the gate electrode portion (the gate electrode 205 and the anodic oxide 206) were etched. Etching was stopped when the gate insulating film 204 became 50 nm. As a result, a thin insulating film 207 was formed. Then, by irradiating a phosphorus / hydrogen plasma stream accelerated to 15 to 50 keV, for example, 30 keV, phosphorus is implanted into the island-shaped semiconductor region 203 in a self-aligned manner, thereby forming an impurity region (source and drain) 208. . (FIG. 2 (B))
[0017]
Then, a 500-nm-thick silicon oxide film is deposited as an interlayer insulator 209, and KrF excimer laser light (wavelength: 248 nm) is irradiated thereon to reduce the crystallinity of the semiconductor region 107 whose crystallinity has deteriorated by the previous impurity implantation step. I recovered. At this time, the energy density of, 150~300mJ / cm ^2, for example, was 200 mJ / cm ^2. In the state where only a thin insulating film covers the semiconductor surface during laser irradiation as in Embodiment 1, the surface becomes rough due to the impact at the time of crystallization of the semiconductor, which causes a problem when forming a contact. Such a problem did not occur in a state where a thick insulating film was formed. (Fig. 2CD)
[0018]
Thereafter, a contact hole was provided in the interlayer insulator 209, and the source and drain electrodes 210 were formed to complete the process. Through the above steps, an N-channel transistor was formed (FIG. 2D).
[0019]
Note that in this embodiment, a thick insulating film which also functions as an interlayer insulating film is deposited over the thin insulating film 207, but after the thin insulating film is completely removed, a thick insulating film is deposited. Is also good. When the impurity ions are irradiated, many impurities are taken into the insulating film and cause absorption of laser light. Thus, by completely removing the insulating film containing such impurities, the efficiency of the subsequent laser annealing can be improved.
[0020]
【The invention's effect】
The present invention provides a method for efficiently performing ion implantation or ion doping and laser annealing or lamp annealing. It will be apparent that the present invention contributes to lowering the temperature of the process, and that the industrial benefits therefrom are great. In the embodiments, the present invention has been described with respect to a MIS transistor having a thin film active layer, that is, a so-called thin film transistor. This is because a low-temperature process is indispensable particularly for a thin film transistor which is easily restricted by a substrate. However, it will be apparent that a similar effect can be obtained by applying the present invention to a MIS transistor formed on a single crystal semiconductor substrate.
[0021]
In the present invention, the type of semiconductor constituting the semiconductor region can be silicon, germanium, silicon carbide, a silicon-germanium alloy, gallium arsenide, or the like. Further, as a material constituting the gate electrode, doped silicon, molybdenum, tungsten, titanium, aluminum, and alloys, silicides, nitrides, and the like thereof are used. In the present invention, when a laser is used, an excimer laser such as an ArF laser (wavelength 193 nm), a KrF laser (248 nm), a XeCl laser (308 nm), a XeF laser (350 nm), an Nd: YAG laser (wavelength 1064 nm), The second harmonic (532 nm), the third harmonic (355 nm), the fourth harmonic (266 nm), and the like are suitable, but it goes without saying that the use of other lasers and light sources is also included in the scope of the present invention. No.
[Brief description of the drawings]
FIG. 1 shows a manufacturing process of an example.
FIG. 2 shows a manufacturing process of an example.
FIG. 3 shows a conventional manufacturing process.
[Explanation of symbols]
101, 201, 301 ... substrates 102, 202, 302 ... base insulating films 103, 203, 303 ... island-shaped semiconductor regions 104, 204, 304 ... gate insulating films 105, 205, 305 ... Gate electrodes 106, 206, 306 anodic oxides 107, 207 thin insulating films 108, 208, 307 impurity regions 109, 209, 308 interlayer insulators 110, 210, 309 ..Source and drain electrodes

Claims (2)

A semiconductor thin film including a source region, a drain region, and a channel formation region on a glass substrate, a gate insulating film over the semiconductor thin film, and a method for manufacturing a transistor having a gate electrode over the gate insulating film,
Forming a semiconductor thin film on the glass substrate,
Forming a gate insulating film on the semiconductor thin film,
Forming the gate electrode on the gate insulating film,
Using the gate electrode as a mask, the gate insulating film is etched and thinned,
After thinning the gate insulating film, using the gate electrode as a mask, adding an N-type impurity to the semiconductor thin film;
After the addition of the impurities, the portion of the gate insulating film thinned by the etching is removed,
After removing the gate insulating film, an interlayer insulating film is formed to cover the semiconductor thin film and the gate electrode,
Manufacturing a transistor, wherein the semiconductor thin film to which the impurity is added is activated by irradiating a second harmonic, a third harmonic, or a fourth harmonic of a Nd: YAG laser through the interlayer insulating film. Method. 2. The method according to claim 1, wherein the semiconductor thin film is made of any one of silicon, germanium, silicon carbide, a silicon germanium alloy, and a gallium arsenide alloy.

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