JP3603055B2 - Semiconductor storage device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an improvement in a semiconductor memory device having a redundant memory cell space.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a chip of a large-capacity memory such as a DRAM, a defect remedy technique of a memory cell has been adopted as the chip becomes larger. As a result, defective memory cells are relieved, and non-defective chips are secured.
[0003]
In addition, the chip rescue rate by the defect remedy technique for the memory cell is also very important in consideration of the total inspection cost. Tests are also performed on memory cells to improve the rescue rate.
[0004]
FIG. 6 is a block diagram showing an example of a multi-bit semiconductor memory device equipped with a redundant replacement circuit for replacing a defective memory cell with a redundant memory cell. In the semiconductor memory device of FIG. 1, the number of input / output data I / O (0) to I / O (7) in the normal mode is a total of 8 input / output data, and the additional address for the test mode is used in the test mode. One data input / output PDI / O (0) is performed by adding and decoding. It is assumed that the defect is not relieved by fuse trimming or the like.
[0005]
In FIG. 6, 1 is a normal memory cell, 2 is a redundant memory cell, 10 is a redundancy judgment signal for replacing a defective memory cell having a defect in the normal memory cell 1 with the redundant memory cell 2, and 14 is a redundant memory cell A redundant memory cell selection signal 3 for making it possible to access 2 is a redundancy determining circuit for replacing a defective memory cell with a redundant memory cell 2 according to the redundancy determining signal 10.
[0006]
4 is a normal mode input / output circuit for inputting / outputting data in the normal mode, 13 is a test mode additional address for expanding the address space in the test mode to reduce the number of input / output data, and 6 is a test mode. Input / output circuit for inputting / outputting data of a normal memory cell 1 or a redundant memory cell 2 at a decoded address in a test mode by adding the test mode additional address to an address in a normal mode. It is. 8 is redundant memory cell data which is data from the redundant memory cell 2, 9 is a test mode selection signal for switching a mode between a normal mode and a test mode, 11 is input / output data in a normal mode, and 12 is input / output data in a test mode. Input / output data 7 is normal memory cell data which is data from the normal memory cell 1.
[0007]
Next, the operation of the semiconductor memory device of FIG. 6 will be described. The mode shifts to the test mode according to the test mode selection signal 9. In the test mode, when the redundant memory cell selection signal 14 is inactive, only the data of the normal memory cell 1, which is a normal memory space, is accessed. On the other hand, when the redundant memory cell selection signal 14 is active, the redundant memory cell 2 can be accessed, whereby the test of the redundant memory cell 2 is performed.
[0008]
[Problems to be solved by the invention]
However, in the conventional semiconductor memory device, when testing the redundant memory cell space, the redundant memory cell selection signal 14 for accessing the redundant memory cell space is necessary because it needs to be distinguished from the normal memory cell space. Met. Here, an example of the internal configuration of the redundancy judgment circuit 3 receiving the redundant memory cell selection signal 14 is shown in FIG. In the redundancy judgment circuit 3 of FIG. 3, when the redundancy memory cell selection signal 14 is inactive, the memory cell 1 side is selected as shown in FIG. On the other hand, when the redundant memory cell selection signal 14 is active, a part of the normal memory cell 1 is cut off and the redundant memory cell 2 is selected as shown in FIG. That is, the entire redundant memory cell 2 and normal memory cell 1 are not simultaneously selected.
[0009]
As a result, it is difficult to test the normal memory cell 1 and the redundant memory cell 2 at the same time, and the test efficiency is reduced. Further, there is a technical problem that a test pattern for detecting a short circuit between the normal memory cell 1 and the redundant memory cell 2 becomes very complicated, and a large number of development steps are required.
[0010]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device having a redundant memory cell space in which a redundant memory cell space and a normal memory cell space can be collectively tested, thereby improving test efficiency and improving test performance. To improve the defect detection rate.
[0011]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, in the semiconductor memory device of the present invention, in a test mode, a data input / output unit dedicated to a redundant memory cell space is provided, whereby a normal memory cell and a redundant memory cell are collectively inspected. It can be so.
[0012]
That is, according to the semiconductor memory device of the present invention, there is provided a semiconductor memory device having a redundant replacement means for replacing a defective memory cell included in a normal memory cell with a redundant memory cell. Input / output means, wherein the test input / output means is divided into a wide area address space and a narrow area address space to which addresses are individually assigned, and the wide area address space stores a part of the normal memory cells. Test addresses of the normal memory cells except for the normal memory cells are allocated, and in the narrow area address space, test addresses of the partial normal memory cells are allocated and test addresses of the redundant memory cells are allocated. It is characterized by.
[0013]
In addition, according to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, a number other than a power of two is used as normal input / output data for testing a power of two of the normal input / output data. address is allocated to the wide area address space of said test input means, test address of the remaining normal input and output data, excluding the power number of the 2 from the total number of the normal input data are input for the test It is characterized by being allocated to the narrow area address space of the output means .
[0014]
According to a third aspect of the present invention, in the semiconductor memory device according to the first aspect, data of a redundant memory cell allocated to an address in a narrow area address space of the test input / output unit is stored in the redundant replacement unit. The signal is transmitted to both of the test input / output means.
[0015]
As described above, in the semiconductor memory device according to the first to third aspects of the present invention, in the test mode, the access to the redundant memory cell is performed through the input / output means dedicated to the redundant memory cell. The space and the space can be tested at the same time, and the efficiency of the test can be improved. In addition, since the normal memory cell space and the redundant memory cell space can be tested at the same time, a short circuit between these two cells can be detected.
[0016]
According to the first to third aspects of the present invention, when the number of data inputs / outputs in the normal mode is a number other than a power of two, the address space of the test input / output unit is Since the address of the redundant memory cell is allocated to the narrow area address space among the wide area address space and the narrow area address space, the input / output means dedicated to the redundant memory cell becomes unnecessary in addition to the above operation. The circuit is simplified.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
(First Embodiment)
FIG. 1 is a block diagram of a semiconductor memory device according to the first embodiment of the present invention. In the semiconductor memory device of FIG. 7, the number of input / output data in the normal mode is a total of 8 input / output data I / O (0) to I / O (7), and an additional test address is added in the test mode. Then, by decoding, a total of two data PDI / O (0) and PDI / O (1) are input / output. Here, it is assumed that defect relief by fuse trimming or the like has not been performed.
[0019]
In FIG. 1, 1 is a normal memory cell, 2 is a redundant memory cell, 10 is a redundancy judgment signal for replacing a defective memory cell in the normal memory cell 1 with a redundant memory cell 2, and 3 is a normal judgment signal based on the redundancy judgment signal 10. A redundancy determining circuit (redundancy replacement means) for replacing a defective memory cell in the memory cell 1 with a redundant memory cell 2, a normal mode input / output circuit 4 for inputting / outputting data in a normal mode, and 7 a normal memory cell 1 , Normal memory cell data.
[0020]
Reference numeral 13 denotes a test mode additional address for expanding the address space in the test mode to reduce the number of input / output data. Reference numeral 5 denotes a test input / output circuit. A test mode additional address 13 is added to input / output data of the decoded normal memory cell 1 or redundant memory cell 2 at the address. In the test input / output circuit 5, a redundant memory cell input / output circuit (redundant memory cell input / output means) 6b is separately arranged in addition to the normal memory cell input / output circuit 6a. The redundant memory cell input / output circuit 6b inputs and outputs only the redundant memory cell data 8, which is information from the redundant memory cell 2, in the test mode. 9 is a test mode selection signal for switching the operation mode between the normal mode and the test mode, 11 is normal mode input / output data input / output to the normal mode input / output circuit 4, and 12 is input to the test input / output circuit 5. Test mode input / output data to be output, which consists of two data PDI / O (0) and PDI / O (1).
[0021]
Next, the internal configuration of the redundancy judgment circuit 3 will be described below, including the operation of the semiconductor memory device of FIG.
[0022]
First, the test mode selection signal 9 is activated. This causes a transition to the test mode. In the test input / output circuit 5, the normal memory cell 1 and the redundant memory cell 2 are accessed by the address in the normal mode and the test mode additional address, and the data is accessed by the redundancy judgment circuit 3 and the test input / output circuit 5. , Two data PDI / O (0) and PDI / O (1) are input / output as test mode input / output data 12.
[0023]
Here, the redundant memory cell data 8 from the redundant memory cell 2 is input to the redundancy determining circuit 3 and also to the redundant memory cell input / output circuit 6b in the test input / output circuit 5. FIG. 2 is a schematic diagram showing the internal configuration of the redundancy judgment circuit 3. In FIG. 7 showing the internal configuration of the conventional redundancy judgment circuit 3, the circuit configuration is complicated because it is necessary to connect the redundant memory cell 2 to the test input / output circuit 5 having the same configuration as the normal mode input / output circuit 4. However, in the redundancy judgment circuit 3 of the present embodiment, the redundant memory cell data 8 is also input to the redundant memory cell input / output circuit 6b separately provided in the test input / output circuit 5 as described above. In the redundancy judgment circuit 3, there is no need to switch the normal memory cell space to the redundant memory cell space. Therefore, it is possible to test the redundant memory cell 2 without inputting the redundant memory cell selection signal 14 to the redundancy judgment circuit 3 as in the related art. Further, since the normal memory cell 1 and the redundant memory cell 2 are tested at the same time, it is possible to detect a short circuit between the normal memory cell 1 and the redundant memory cell 2. In the normal mode, the redundant memory cell input / output circuit 6b does not operate, so that there is no influence on the normal mode.
[0024]
(Second embodiment)
Subsequently, a second embodiment of the present invention will be described. FIG. 3 shows a block diagram of the semiconductor memory device of the present embodiment.
[0025]
In the semiconductor memory device of FIG. 3, the number of input / output data (normal input / output data) I / O (0) to I / O (8) in the normal mode is 9 in total, and 2 3 +1 It is the number of I / O. Utilizing this number of I / Os, the semiconductor memory device of FIG. 1 does not require the redundant memory cell input / output circuit 6b separately provided in the first embodiment. Note that, also in the present embodiment, it is assumed that defect relief by fuse trimming or the like is not performed. Hereinafter, a specific description will be given.
[0026]
In FIG. 3, 1 is a normal memory cell, 2 is a redundant memory cell, 10 is a redundancy judgment signal for replacing a defective memory cell in the normal memory cell 1 with the redundant memory cell 2, and 3 is defective by the redundancy judgment signal 10. A redundancy determining circuit (redundancy determining means) 4 for replacing a memory cell with a redundant memory cell 2 is a normal mode input / output circuit for inputting / outputting data in the normal mode. 7 is normal memory cell data which is information from the normal memory cell 1, 8 is redundant memory cell data which is information from the redundant memory cell 2, and 9 is a test mode selection for switching the operation mode between the normal mode and the test mode. A signal 11 is input / output data in the normal mode.
[0027]
Further, in FIG. 3, reference numeral 13 denotes a test mode additional address for expanding the address space in the test mode to reduce the number of input / output data, and 5 denotes a test input / output circuit (test input / output means) In the test mode, the additional address for the test mode is received in addition to the address in the normal mode, the two addresses are decoded as test addresses, and the corresponding normal memory cell 1 or redundant memory cell 2 is accessed. The test input / output circuit 5 is divided into a wide area address space 5a and a narrow area address space 5b allocated to mutually different address spaces. In this wide area address space 5a, addresses corresponding to 2 @ 3 input / output data I / O (0) to I / O (7) are allocated, and in the narrow area address space 5b, one remaining address is assigned. An address corresponding to the input / output data I / O (8) is assigned. In the test mode, the wide area address space 5a inputs and outputs one data PDI / O (0), and the narrow area address space 5b inputs and outputs another data PDI / O (1). The two data PDI / O (0) and PDI / O (1) form the input / output data 12 in the test mode.
[0028]
Subsequently, the operation of the semiconductor memory device of FIG. 3 will be described below. First, the mode shifts to the test mode by activating the test mode selection signal 9. The test input / output circuit 5 receives and decodes the address in the normal mode and the additional address 13 for the test mode, accesses the corresponding normal memory cell 1 or the redundant memory cell 2, and outputs the test mode input / output data 12 Input and output.
[0029]
Here, the redundant memory cell data 8 from the redundant memory cell 2 is input to the redundancy determination circuit 3 and also to the narrow area address space 5b of the test input / output circuit 5, as shown in FIG. The data is input / output as data PDI / O (1) via the narrow area address space 5b. Therefore, the redundant memory cell 2 can be tested without requiring the input of the redundant memory cell selection signal 14 unlike the conventional redundancy determination circuit 3 shown in FIG. Further, since the normal memory cell 1 and the redundant memory cell 2 are tested at the same time, it is possible to detect a short circuit between the cells 1 and 2. Further, since the redundant memory cell input / output circuit 6b required in the first embodiment is not required, the circuit area can be reduced.
[0030]
(Third embodiment)
Subsequently, a third embodiment of the present invention will be described. FIG. 5 shows an internal block diagram of a redundancy judgment circuit and the like in the semiconductor memory device of the present embodiment.
[0031]
In the figure, 1 is a normal memory cell, 2 is a redundant memory cell, 10 is a redundancy judgment signal for replacing a defective memory cell in the normal memory cell 1 with a redundant memory cell 2, and 3 is a defect by the redundancy judgment signal 10. A redundancy judgment circuit for replacing a memory cell with a redundancy memory cell 2, a normal mode input / output circuit 4 for inputting / outputting data in a normal mode, and a redundancy memory cell selection signal 14 characteristic of the present embodiment. , A signal for selecting the redundant memory cell 2 and also the memory cell 1a in the normal memory cell 1 physically continuous with the redundant memory cell 2.
[0032]
Next, an operation and a characteristic configuration of the semiconductor memory device of the present embodiment will be described below. In the present embodiment, when the redundant memory cell 2 is accessed by the redundant memory cell selection signal 14 in the test mode, not only the redundant memory cell 2 but also a normal memory cell physically connected to the redundant memory cell 2 A simultaneous access circuit (simultaneous access means) 15 is arranged so that memory cell 1a in memory cell 1 is simultaneously accessed.
[0033]
Therefore, in the present embodiment, when the redundant memory cell 2 is tested by the redundant memory cell selection signal 14, since the physically continuous redundant memory cell space and the normal memory cell space are simultaneously accessed, these two cells are accessed. It is possible to easily detect a defective portion such as a short circuit therebetween.
[0034]
【The invention's effect】
As described above, according to the semiconductor memory device of the present invention, in the test mode, the redundant memory cell is accessed through the input / output means dedicated to the redundant memory cell. The space and the redundant memory cell space can be tested at the same time, the efficiency of the test can be improved, and the short circuit between the normal memory cell space and the redundant memory cell space can be detected.
[0035]
According to the first to third aspects of the present invention, the address space of the test input / output unit is divided into a wide area address space and a narrow area address space for normal memory cells, and Since the addresses of the redundant memory cells are allocated, in addition to the effects of the first and second aspects of the present invention, the input / output means dedicated to the redundant memory cells is not required, and the circuit can be simplified.
[Brief description of the drawings]
FIG. 1 is a diagram showing a block configuration of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a redundancy judgment circuit provided in the semiconductor memory device.
FIG. 3 is a diagram illustrating a block configuration of a semiconductor memory device according to a second embodiment of the present invention;
FIG. 4 is a diagram showing a configuration of a test input / output circuit provided in the semiconductor memory device.
FIG. 5 is a diagram showing a configuration of a redundancy judgment circuit provided in a semiconductor memory device according to a third embodiment of the present invention.
FIG. 6 is a diagram showing a block configuration of a conventional semiconductor memory device.
FIG. 7 is a diagram showing a configuration of a conventional redundancy judgment circuit.
FIG. 8 is a diagram showing an operation of a conventional redundancy judgment circuit when a redundant memory cell selection signal is inactive.
FIG. 9 is a diagram showing an operation of a conventional redundancy judgment circuit when a redundant memory cell selection signal is active.
[Explanation of symbols]
Reference Signs List 1 normal memory cell 1a normal memory cell physically continuous to redundant memory cell 2 redundant memory cell 3 redundancy determination circuit 4 normal mode input / output circuit 5 test input / output circuit (test input / output means)
5a Wide area address space 5b Narrow area address space 6a Normal memory cell input / output circuit 6b Redundant memory cell input / output circuit (redundant memory cell input / output means)
7 Normal memory cell data 8 Redundant memory cell data 9 Test mode selection signal 10 Redundancy determination signal 11 Normal mode input / output data 12 Test mode input / output data 13 Additional address for test mode 14 Redundant memory cell selection signal 15 Simultaneous access circuit (simultaneous access) means)

Claims (3)

In a semiconductor memory device provided with redundant replacement means for replacing defective memory cells included in normal memory cells with redundant memory cells,
A test input / output means for inputting a test address;
The test input / output means is divided into a wide area address space and a narrow area address space to which addresses are individually assigned,
In the wide area address space, test addresses of normal memory cells except for a part of the normal memory cells are assigned,
The semiconductor memory device according to claim 1, wherein a test address of said part of normal memory cells and a test address of said redundant memory cell are allocated to said narrow area address space. Numbers other than powers of 2 are used as normal input / output data.
The power-of-two test addresses of the normal input / output data are allocated to a wide area address space of the test input / output means ,
2. A test address of the remaining normal input / output data obtained by removing the power of two from the total number of the normal input / output data is allocated to a narrow area address space of the test input / output unit. 13. The semiconductor memory device according to claim 1. Data in the redundant memory cell assigned to the address of the narrow region address space of said test input means, according to claim 1, characterized in that it is transmitted to both the said test input means said redundant replacement unit 13. The semiconductor memory device according to claim 1.

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