JP3603438B2 - Amplification type solid-state imaging device and manufacturing method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an amplification type solid-state imaging device having a built-in capacitance element for sampling and holding a signal charge, and a method for manufacturing the same.
[0002]
[Prior art]
The CCD solid-state imaging device usually only has a built-in charge detection circuit composed of a source follower circuit of several stages as an output circuit.
2. Description of the Related Art In recent years, in accordance with a demand for higher resolution of a solid-state imaging device, an amplification-type solid-state imaging device having no smear and capable of realizing fine pixels has been developed. This amplification type solid-state imaging device includes a MOS transistor for amplifying an optical signal for each pixel, that is, a pixel MOS transistor, and reads out a signal stored in the pixel MOS transistor as current modulation of the MOS transistor. .
[0003]
FIG. 4 shows an example of a circuit configuration of the amplification type solid-state imaging device. In the amplification type solid-state imaging device 1, light receiving elements constituting a plurality of unit pixels, that is, pixel transistors, for example, pixel MOS transistors 2, are arranged in a matrix, and the gate of each row of the pixel MOS transistors 2 is provided by a shift register or the like. A vertical scanning signal (ie, a vertical selection pulse) φV [φV₁, ‥‥ φV_i, ΦV_{i + 1},..], The drain of which is connected to the power supply V_DD, And the source for each column is connected to the vertical signal line 5.
[0004]
A load capacitance element 7 that samples and holds a signal voltage (charge) via an operation MOS switch 6 is connected to the vertical signal line 5. The load capacitance element 7 is connected between the vertical signal line 5 and the ground potential. An operation pulse φ is applied to the gate of the operation MOS switch 6._OPSIs applied.
[0005]
A reset bias voltage V is applied to the vertical signal line 5 between the source of the pixel MOS transistor 2 and the operation MOS switch 6 via a reset MOS switch 8 which also serves to reset the load capacitance element 7 and reset the vertical signal line 5._RBIs connected to a reset bias voltage supply terminal 13 for supplying the same. A reset pulse φ is applied to the gate of the reset MOS switch 8._RSTIs supplied.
[0006]
Reference numeral 9 denotes a horizontal scanning circuit composed of a shift register and the like. The horizontal scanning circuit 9 sequentially supplies a horizontal scanning signal (that is, a horizontal scanning pulse) φH [φH to a gate of a horizontal MOS switch 11 connected to a horizontal signal line 10.₁, ‥‥ φH_n, ΦH_{n + 1}, ‥‥] are supplied.
[0007]
As the pixel MOS transistor 2, a MOS transistor having an annular gate electrode structure in which a source is surrounded by a gate electrode is used, and charges obtained by photoelectric conversion are accumulated in a silicon substrate below the gate electrode.
[0008]
FIG. 5 is a cross-sectional view showing a semiconductor structure of the unit pixel (ie, pixel MOS transistor) 2.
In this figure, reference numeral 21 denotes a first conductivity type, for example, a p-type silicon semiconductor substrate; 22, a photoelectrically converted signal charge; in this example, a p-type well region for accumulating holes 20; This is a well area. An n-type source region 24 and a drain region 25 are formed in the p-type well region 22. For example, light is applied to the p-type well region 22 between the two regions 24 and 25 via a gate insulating film so as to surround the source region. A gate electrode 26 made of a thin-film polycrystalline silicon that can be transmitted is formed. The holes 20 accumulated by photoelectric conversion in the p-type well region 22 immediately below the gate electrode 26 control a channel current (drain current) during a read operation, and the amount of change in the channel current becomes a signal output.
[0009]
In this amplification type solid-state imaging device, the charge that has been photoelectrically converted during the light receiving period is accumulated in the p-type well region below the gate electrode. In the horizontal blanking period, before the readout operation period of the pixel MOS transistor 2, that is, in the reset period, the vertical signal line 5 and the load capacitance element 7 are reset by the reset bias voltage V._RBReset to. That is, the reset pulse φ_RSTAnd operation pulse φ_OPSTo turn on the reset MOS switch 8 and the operation MOS switch 6 at the same time. As a result, the initial voltage of the vertical signal line 5 and the load capacitance element 2 before the read operation period of the pixel MOS transistor 2 becomes the reset bias voltage V_RBIs reset to
[0010]
Thereafter, the reset MOS switch 8 is turned off, and a vertical selection pulse φV is applied to a vertical selection line, for example, the vertical selection line 4 in the i-th row._iIs given. At this time, the operating pulse φ_OPSAre continuously supplied, and the operation MOS switch 6 is turned on.
At this time, the pixel MOS transistor 2 in the selected i-th row is turned on, a current flows to the vertical signal line 5 connected thereto as a modulation of the current to the source, and is temporarily supplied to the load capacitance element 7 through the operation MOS switch 6. It is stored as electric charge. That is, a signal voltage corresponding to a channel potential corresponding to the signal charge amount (hole amount) stored in the pixel MOS transistor 2 is held in the load capacitance element 7. This signal read operation is performed once in one horizontal blanking period, and one horizontal row is simultaneously read, and the charge read to each load capacitance element 7 is sampled and held.
[0011]
Next, during the horizontal effective period, the signal charges held in these load capacitance elements 7 are converted into horizontal scanning signals φH [φH₁, ‥‥ φH_n, ΦH_{n + 1}, ‥‥], the horizontal MOS switch 11 is turned on in order to flow through the horizontal signal line 10 and output to the outside as a signal voltage through an output circuit.
[0012]
As described above, in the amplification type solid-state imaging device, the signal charge is once stored in the load capacitance element 7 and then read out to the outside through the horizontal MOS switch 11. Therefore, the random noise of the output signal is determined by the capacitance of the horizontal MOS switch 11 and the capacitance of the load capacitance element 7. In general, the signal-to-noise ratio, that is, the S / N ratio is better as the capacitance of the load capacitance element 7 is larger, although it depends on the driving capability of the switching MOS transistor. For example, in order to satisfy the S / N ratio of 50 dB required for an image element, the load capacitance element 7 needs to have a capacitance of at least about 1 pF.
[0013]
[Problems to be solved by the invention]
Conventionally, in order to realize the load capacitance element 7 having such a capacity, as shown in FIG. 6, a MOS structure which is formed simultaneously with a MOS transistor constituting a peripheral circuit (hereinafter referred to as a peripheral MOS transistor) has been used. That is, n formed on one surface of the silicon semiconductor region surrounded by the field insulating film 31, for example, the p-type well region 22.⁻At the same time as the formation of the peripheral MOS transistor on the region 32, a gate electrode 34 of polycrystalline silicon is formed via a gate insulating film (eg, a gate oxide film) 33, and the gate electrode 34 and n⁻The load capacitance element 7 is formed between the regions 32.
[0014]
Therefore, for example, when a gate oxide film thickness of 20 nm used for a general transistor length of 0.8 μm is used, in order to secure a capacitance of 1 pF, if the width of the load capacitance element is 5 μm, the length is 450 μm. Required. Since the load capacitance element is connected for each vertical signal line, the area of the peripheral circuit is made very large.
[0015]
In particular, in order to incorporate the fixed pattern noise elimination, two capacitors are required. Further, since the signals of the adjacent pixels in the vertical direction are added in the field readout, another double capacitor is required. . As a result, a total of four capacitive elements are required for each horizontal pixel.
[0016]
For example, in the case of a 1 / 2-inch amplification type solid-state imaging device having 2 million pixels, the horizontal pixel pitch is 3.65 μm, so that the width is only 3 μm, and the pattern width of the capacitor is 600 μm or more. These four pieces occupy 2.4 mm or more in the vertical direction of the chip size.
[0017]
Therefore, in order to realize a solid-state imaging device having a small angle of view, even if the pixel area is reduced, the peripheral circuits are relatively large in order to realize a solid-state imaging device having a good S / N ratio and high image quality. As a result, there is a problem that the chip becomes large.
[0018]
In view of the above, the present invention provides a small-sized amplifying solid-state imaging device having a good S / N ratio and a method of manufacturing the same, which increases the capacitance of a capacitor for sampling and holding a signal charge without increasing a chip area. Is what you do.
[0019]
[Means for Solving the Problems]
An amplification type solid-state imaging device according to the present invention includes a first capacitor element portion made of the same material as a gate insulating film and a gate electrode of a first MOS transistor;amountA capacitance element formed by connecting in parallel a second capacitance element part in which a material for a gate electrode of a second MOS transistor is provided as a counter electrode on the element part via an insulating film made of a silicon nitride film is used as a signal charge. Is built in as a capacitive element for sampling and holding.
An amplification type solid-state imaging device according to the present invention includes a first capacitor element portion made of the same material as a gate insulating film and a gate electrode of a first MOS transistor, and a first capacitor element portion provided on the first capacitor element portion with an insulating film interposed therebetween. Amplification type solid-state imaging device in which a capacitance element configured by connecting in parallel a second capacitance element part provided with a material of a gate electrode of a second MOS transistor as a counter electrode is built in as a capacitance element for sampling and holding signal charges. In the element, a surface oxide film of an electrode on an upper side of the first capacitance element portion generated in a gate oxidation step of the second MOS transistor is used as an insulating film of the second capacitance element section.
[0020]
In this solid-state imaging device, since the capacitance element is formed by the first capacitance element portion and the second capacitance element portion which are stacked and connected in parallel, the capacitance of the capacitance element can be effectively increased, and accordingly, The two-dimensional area can be reduced, and the size of the solid-state imaging device can be reduced without deteriorating the S / N ratio.
[0021]
A method for manufacturing an amplification type solid-state imaging device according to the present invention is characterized in that a first MOS transistor is provided on a semiconductor region.Gate insulating film and gate electrodeSame asDepends on materialA first insulating film;First electrode material layerFormAnd a step of:Form silicon nitride filmThe process ofSilicon nitride film;First electrode material layerPatterning at the same timeForming a second insulating film and a first electrode to form a first capacitor element portion including a semiconductor region, the first insulating film, and the first electrode;After the gate oxidation of the second MOS transistor,On the second insulating filmGate electrode of second MOS transistorDepends on the materialForm the second electrodeForming a first capacitor, a second capacitor element including a second insulating film and a second electrode, and connecting the first capacitor element and the second capacitor element in parallel;A capacitor for sampling and holding a signal charge is formed.
According to this manufacturing method, a large-capacitance element for sampling and holding signal charges can be formed without changing the manufacturing process used in the amplification type solid-state imaging device by adding only one silicon nitride film forming step. it can.
[0022]
Another method for manufacturing an amplification type solid-state imaging device according to the present invention is a method for manufacturing a first MOS transistor on a semiconductor region.OfWith the first insulating filmA first insulating film made of the same material as the gate electrode;Forming a first electrode,Forming a first capacitive element portion including a semiconductor region, a first insulating film, and a first electrode;The surface oxide film of the first electrode generated when the gate of the second MOS transistor is oxidized is referred to as a second insulating film.The process ofSecond insulating filmToGate of second MOS transistorElectrode materialForming the second electrodeThen, a second capacitive element portion including the first electrode, the second insulating film, and the second electrode is formed.Process andBy connecting the first capacitance element portion and the second capacitance element portion in parallel,A capacitor for sampling and holding a signal charge is formed.According to this manufacturing method, a large-capacitance element for sampling and holding signal charges can be produced without any change in a manufacturing process in which a conventional amplification type solid-state imaging device is used.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
An amplification type solid-state imaging device according to the present invention includes a first capacitance element portion made of the same material as a gate insulating film and a gate electrode of a first MOS transistor, and a first capacitance element portion formed on the first capacitance element portion.Made of silicon nitride filmA configuration in which a capacitance element configured by connecting in parallel a second capacitance element provided with a material of a gate electrode of a second MOS transistor as an opposite electrode via an insulating film as a counter electrode is built in as a capacitance element for sampling and holding signal charges. And
[0025]
According to the present invention, in the amplification type solid-state imaging device, the first MOS transistor is a peripheral MOS transistor or a pixel MOS transistor, and the second MOS transistor is a pixel MOS transistor or a peripheral MOS transistor.
[0026]
An amplification type solid-state imaging device according to the present invention includes a first capacitor element portion made of the same material as a gate insulating film and a gate electrode of a first MOS transistor, and a first capacitor element portion provided on the first capacitor element portion with an insulating film interposed therebetween. Amplification type solid-state imaging device in which a capacitance element configured by connecting in parallel a second capacitance element part provided with a material of a gate electrode of a second MOS transistor as a counter electrode is built in as a capacitance element for sampling and holding signal charges. In the element, a surface oxide film of an electrode on an upper side of the first capacitance element portion generated in a gate oxidation step of the second MOS transistor is used as an insulating film of the second capacitance element section.
[0027]
According to the present invention, in the above-mentioned amplification type solid-state imaging device, the second MOS transistor is formed in a gate oxidation step.Upper electrode for the first capacitive elementIs used as an insulating film of the second capacitor element portion.
[0028]
A method for manufacturing an amplification type solid-state imaging device according to the present invention is characterized in that a first MOS transistor is provided on a semiconductor region.Gate insulating film and gate electrodeSame asDepends on materialFirst insulating filmAnd first electrode material layerFormAnd a step of:Form silicon nitride filmThe process ofSilicon nitride film;First electrode material layerSimultaneous patterning to form second insulating film and first electrodeForming a first capacitor element portion including a semiconductor region, a first insulating film, and a first electrode;After the gate oxidation of the second MOS transistor,On the second insulating filmGate electrode of second MOS transistorDepends on the materialForm the second electrodeForming a first capacitor, a second capacitor element including a second insulating film and a second electrode, and connecting the first capacitor element and the second capacitor element in parallel;A capacitor for sampling and holding a signal charge is formed.
[0029]
Further, according to the method of manufacturing an amplification type solid-state imaging device according to the present invention, a first MOS transistor is provided on a semiconductor region.OfFirst insulating filmAnd a first insulating film made of the same material as the gate electrode;Form the first electrodeForming a first capacitive element portion including a semiconductor region, a first insulating film, and a first electrode;Using the surface oxide film of the first electrode generated during the gate oxidation of the second MOS transistor as a second insulating film;ToGate of second MOS transistorElectrode materialForming the second electrodeThen, a second capacitive element portion including the first electrode, the second insulating film, and the second electrode is formed.Process andBy connecting the first capacitance element portion and the second capacitance element portion in parallel,A capacitor for sampling and holding a signal charge is formed.
[0030]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0031]
The amplification type solid-state imaging device of this example also has the circuit configuration shown in FIG.
That is, as shown in FIG. 4, light receiving elements constituting a plurality of unit pixels, that is, pixel transistors, for example, pixel MOS transistors 2 are arranged in a matrix, and the gate of each row of the pixel MOS transistors 2 is provided from a shift register or the like. A vertical scanning signal (ie, a vertical selection pulse) φV [φV₁, ‥‥ φV_i, ΦV_{i + 1},..], The drain of which is connected to the power supply V_DD, And the source for each column is connected to the vertical signal line 5.
[0032]
A load capacitance element 7 that samples and holds a signal voltage (charge) via an operation MOS switch 6 is connected to the vertical signal line 5. The load capacitance element 7 is connected between the vertical signal line 5 and the ground potential. An operation pulse φ is applied to the gate of the operation MOS switch 6._OPSIs applied.
[0033]
A reset bias voltage V is applied to the vertical signal line 5 between the source of the pixel MOS transistor 2 and the operation MOS switch 6 via a reset MOS switch 8 which also serves to reset the load capacitance element 7 and reset the vertical signal line 5._RBIs connected to a reset bias voltage supply terminal 13 for supplying the same. A reset pulse φ is applied to the gate of the reset MOS switch 8._RSTIs supplied.
[0034]
Then, a horizontal scanning signal (ie, horizontal scanning pulse) φH [φH is sequentially supplied from a horizontal scanning circuit 9 including a shift register or the like to a gate of a horizontal MOS switch 11 connected to a horizontal signal line 10.₁, ‥‥ φH_n, ΦH_{n + 1}, ‥‥] are supplied.
[0035]
As the pixel MOS transistor 2, a MOS transistor having an annular gate electrode structure in which a source is surrounded by a gate electrode is used, and charges obtained by photoelectric conversion are accumulated in a silicon substrate below the gate electrode. An example of the semiconductor structure of the unit pixel (that is, the pixel MOS transistor) is as shown in FIG.
[0036]
The operation of this amplification type solid-state imaging device is the same as that described above, and the description is omitted.
[0037]
In the embodiment of the present invention, in such an amplification type solid-state imaging device, a load capacitance element for sampling and holding a signal charge is replaced by a MOS structure used for a conventional peripheral MOS transistor, that is, a polycrystalline silicon layer serving as an electrode material and a semiconductor substrate. And a capacitor connected in parallel with each other using, for example, a thin film polycrystalline silicon layer which is an electrode material constituting the pixel MOS transistor.
[0038]
FIG. 1 shows a basic and simple embodiment of a capacitive element structure according to the present invention.
The capacitance element of this example, that is, the load capacitance element 701 is formed on the silicon substrate, that is, n⁻On the semiconductor region 42, for example, a gate insulating film (for example, a gate oxide film) of a peripheral MOS transistor and a gate electrode made of polycrystalline silicon are formed simultaneously with the same gate insulating film 41 and an electrode made of polycrystalline silicon (a so-called lower electrode). ) 43 is formed, and n sandwiching the gate insulating film 41 is formed.⁻A capacitor element having a MOS structure composed of a semiconductor region 42 and an electrode 43 of polycrystalline silicon, that is, a first capacitor element section 44 is formed, and a thinner insulating layer is formed on the first capacitor element section 44, that is, on the electrode 43. A thin-film polycrystalline silicon layer is formed through a film (for example, an oxide film or a SiN film) 46 at the same time as the formation of the gate electrode of the pixel MOS transistor 2 using the thin-film polycrystalline silicon, and is patterned to face the thin-film polycrystalline silicon. An electrode (a so-called upper electrode) 47 is formed, and a second capacitance element portion 48 is formed between the lower electrode 43 and the upper counter electrode 47 with the insulating film 46 interposed therebetween, and the first capacitance element portion 44 and the second capacitance The element section 48 is electrically connected in parallel. That is, n⁻The semiconductor region 42 and the counter electrode 47 are commonly connected, and the lower electrode 43 is connected to the vertical signal line 5. 49 is a field oxide film.
[0039]
Here, the insulating film 46 forming the second capacitive element portion 48 is formed by a surface oxide film formed by oxidizing polycrystalline silicon of the electrode 43 by a gate oxidation step when forming a gate insulating film of the pixel MOS transistor 2. can do.
[0040]
According to the load capacitance element 701 described above, the thinner insulating film 46 and the gate electrode of the pixel MOS transistor are simultaneously formed on the polycrystalline silicon electrode 43 of the first capacitance element portion 44 having the MOS structure formed simultaneously with the peripheral MOS transistor. By forming the counter electrode 47 of the formed thin-film polycrystalline silicon and providing the second capacitance element portion 48 and connecting both capacitance element portions 44 and 48 in parallel, the area is the same as the conventional one and only the capacitance is independently increased. be able to. As described above, by effectively increasing the capacitance of the load capacitance element 701, the two-dimensional area can be reduced accordingly, and the S / N ratio is not deteriorated, and the amplification type solid-state imaging element is reduced. Can be reduced in size.
[0041]
Usually, the surface oxide film of polycrystalline silicon contains phosphorus at a high concentration, and therefore grows 1.5 to 3 times as thick as the gate insulating film. Therefore, when the surface oxide film of the polycrystalline silicon electrode 43 is used as the insulating film 46 of the second capacitance element portion 48, the second capacitance element portion 48 does not necessarily provide a large capacitance, but the conventional production Capacity can be increased without changing the process at all.
[0042]
Next, a description will be given of another embodiment of the present invention in which the capacitance is effectively increased. In this example, a thin SiN film is used as an insulating film of the second capacitive element portion, and the structure and manufacturing method will be described with reference to FIGS.
[0043]
First, as shown in FIG. 2, a region where the load capacitance element 702 is to be formed, that is, n surrounded by the field oxide film 49.⁻A polycrystalline silicon layer 43A serving as an electrode is grown on the upper surface including the semiconductor region 22 via an insulating film 41 by a CVD (chemical vapor deposition) method.
The insulating film 41 is formed simultaneously with the formation of the gate insulating film of the peripheral MOS transistor, and the polycrystalline silicon layer 43A is also grown simultaneously with the formation of the polycrystalline silicon layer serving as the gate electrode of the peripheral MOS transistor. The polycrystalline silicon layer is formed in a state in which carrier impurities such as phosphorus (P) are doped.
[0044]
Next, on the polycrystalline silicon layer 43A, an insulating film serving as a capacitance of the load capacitance element, for example, an SiN film 51 is formed thin by, for example, a CVD method. This film thickness is determined in consideration of an insulation leak current under a potential difference related to the load capacitance element and a period during which the sample and hold must be performed. The thickness is preferably, for example, about 5 nm to 30 nm.
[0045]
Here, the SiN film 51 generally has a larger leakage current when a voltage is applied than the silicon oxide film.2 nmA degree of thermal oxide film may be formed in a diluted oxygen atmosphere or the like. The reason for using the SiN film 51 is that the SiN film has a high dielectric constant and an excellent withstand voltage, and particularly has an oxidation resistance and a hydrofluoric acid etching resistance. This will be described later.
[0046]
Next, as shown in FIG. 2B, first, the SiN film 51 is selectively etched and removed using a resist mask 52, and then the polycrystalline silicon layer 43A is continuously and selectively selected using the same resist mask 52. Remove by etching. Thus, in the region where the load capacitance element is formed, the SiN film 51 for the capacitance element and the electrode 43 (the so-called lower electrode) of the polycrystalline silicon layer 43A are formed.
Here, the etching apparatus may be divided into the SiN film 51 and the polycrystalline silicon layer 43A, or if the etching can be performed continuously, the same etching apparatus may be used to perform the etching under the etching condition of the insulating film; The step of etching can be performed continuously.
[0047]
Next, prior to the gate oxidation for forming the gate insulating film of the pixel MOS transistor, it is necessary to remove the gate oxide film for the peripheral MOS transistor by etching in a region corresponding to the pixel portion. . At this time, since the SiN film 51 constituting the load capacitance element is excellent in hydrofluoric acid etching resistance, the entire surface of the wafer including the region having the SiN film 51 contains hydrofluoric acid without any special consideration. There is an advantage that the etching treatment with a solution and the removal of the gate oxide film in the region of the pixel portion can be performed in the conventional manner. After this etching step, formation of a gate insulating film of the pixel MOS transistor, that is, gate oxidation is performed.
[0048]
In this gate oxidation step, as shown in FIG. 2C, since the SiN film 51 has oxidation resistance, the electrode 43 of the polycrystalline silicon layer is not oxidized and the insulating film does not become thick. However, the side surface of the polycrystalline silicon electrode 43 exposed on the surface is oxidized to form an oxide film 53. By performing such gate oxidation in a wet atmosphere, an oxide film is formed slightly on the SiN film 51, and there is also an advantage that when used as a load capacitance element, leakage current due to voltage can be reduced. This allows the SiN film 51 to be further thinned.
[0049]
Next, as shown in FIG. 3D, a thin-film polycrystalline silicon layer 55 is grown simultaneously with the formation of the thin-film polycrystalline silicon for the gate electrode of the pixel MOS transistor over the entire surface. The withstand voltage of the polycrystalline silicon layer with respect to the thin film polycrystalline silicon layer 55 at the edge of the electrode 43 is such that the side surface of the polycrystalline silicon layer electrode 43 is oxidized by the oxidation step of FIG. 2C, and a sufficiently thick oxide film 53 is formed. There is no problem at all. This point is also an excellent feature of the manufacturing process of this example.
[0050]
Next, as shown in FIG. 3E, a resist mask 56 is formed on the thin-film polycrystalline silicon layer 55, and in a normal step of patterning the gate electrode of the pixel MOS transistor, the thin-film polycrystalline silicon layer 55 is etched to form a counter electrode (a so-called upper electrode) 551.
[0051]
Usually, the SiN film is made of SiO₂This is disadvantageous because the etching rate of the polycrystalline silicon is slightly higher than that of the film as the etching stopper, but here, since the thin polycrystalline silicon layer 55 is etched, the thickness of the thin polycrystalline silicon layer of the pixel is 100 nm. If it is within the range, even if the SiN film 51 is about 5 nm, it can be a sufficient stopper.
[0052]
Also, even if the thin-film polycrystalline silicon layer 55 is patterned so as to surround the lower electrode 43 of the polycrystalline silicon layer, there is no problem with the breakdown voltage as described above.
Therefore, the thin-film polycrystalline silicon layer 55 may be patterned inside or outside the end of the lower electrode 43 at all. Therefore, the degree of freedom of patterning is large.
[0053]
In this way, n⁻The first capacitor element portion 57 formed by the region 22, the insulating film 41, and the lower electrode 43 made of polycrystalline silicon, the lower electrode 43, and the second capacitor element portion 58 formed by the SiN film 51 and the upper electrode 551 made of polycrystalline silicon. A laminate is obtained.
[0054]
After that, the first capacitance element portion 57 and the second capacitance element portion 58 are electrically connected in parallel, that is, n⁻The region 22 and the electrode 551 are commonly connected and grounded, and the lower electrode 43 is connected to a vertical signal line to form a target load capacitance element 702.
[0055]
According to the load capacitance element 702 of this embodiment, the capacitance can be increased without increasing the area of the load capacitance element by providing the capacitance element portions 57 and 58 in a stacked manner. By using the SiN film 51 having a high dielectric constant as the insulating film as the second capacitance element portion 58, a load capacitance element having a larger capacitance can be formed.
[0056]
As a manufacturing process, only a single step of growing the SiN film 51 is added, and the large-capacity load capacitance element 702 can be formed without changing a manufacturing process of an ordinary amplification type solid-state imaging device.
Since the SiN film 51 used for increasing the capacity can be made thicker or thinner independently, there is an advantage that the degree of freedom in designing the capacity is large.
[0057]
Also in this embodiment, since a load capacitance element having a large capacitance can be obtained, the S / N ratio of the solid-state imaging device can be improved. Further, since the area of the peripheral circuit can be reduced and the chip area can be reduced, the mounting area of the solid-state imaging device can be reduced, thereby improving the commercial value, and the number of chips per wafer increases, thereby reducing the manufacturing cost.
[0058]
In the above example, the structure of the amplification type solid-state imaging device of the capacitive load operation system, particularly the structure of the load capacitance device has been described. However, the present invention can also be applied to the configuration of the capacitance device which samples and holds the signal charges in other operation systems.
[0059]
In the above example, an example of application to an amplification type solid-state imaging device was described because it is particularly effective in forming a capacitance circuit in the amplification type solid-state imaging device. The present invention is sufficiently applicable to such a circuit.
[0060]
【The invention's effect】
According to the amplification type solid-state imaging device according to the present invention, the capacitance of the capacitor that samples and holds the signal charge can be increased without increasing the area. Therefore, the S / N ratio in the solid-state imaging device can be improved by the increase in the capacitance.
[0061]
In addition, the increased capacity allows the area of the peripheral circuit to be reduced and the chip area to be reduced, so that the mounting area of the solid-state imaging device can be reduced. Cost can be reduced.
[0062]
When a silicon nitride film is used as an insulating film constituting the second capacitor element portion as the capacitor, the capacitance can be further increased. In this case, since the SiN film is grown in an independent process without being used for the formation of the film of the other portion, the film thickness can be freely set, so that the degree of freedom in designing the capacitance value is large.
When the surface oxide film of the electrode on the upper side of the first capacitance element portion generated in the gate oxidation step of the second MOS transistor is used as the insulating film forming the second capacitance element part, the conventional manufacturing process is not changed at all. In addition, the capacitance of the capacitor that samples and holds the signal charge can be increased.
[0063]
ADVANTAGE OF THE INVENTION According to the manufacturing method of the amplification type solid-state imaging device which concerns on this invention, without changing the manufacturing process of the conventional solid-state imaging device at all, the capacitance element which increased the capacity | capacitance in the same area as the conventional one, ie, sample-holds a signal charge. A capacitor can be formed.
[0064]
Further, according to the method of manufacturing an amplification type solid-state imaging device according to the present invention, only one step of growing a silicon nitride film is added, and the other is increased in capacity with the same area as the conventional one without changing the manufacturing process. A capacitor, that is, a capacitor which samples and holds a signal charge can be formed. Therefore, an amplifying solid-state imaging device having an improved S / N ratio and a small chip area can be easily manufactured with little change in a conventional manufacturing process.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an example of a load capacitance element in an amplification type solid-state imaging device according to the present invention.
FIG. 2A is a manufacturing process diagram showing another example of the load capacitance element in the amplification type solid-state imaging device according to the present invention.
B is a manufacturing process diagram showing another example of the load capacitance element in the amplification type solid-state imaging device according to the present invention.
C It is a manufacturing process diagram showing another example of the load capacitance element in the amplification type solid-state imaging device according to the present invention.
FIG. 3D is a manufacturing process diagram showing another example of the load capacitance element in the amplification type solid-state imaging device according to the present invention.
E is a manufacturing process diagram showing another example of the load capacitance element in the amplification type solid-state imaging device according to the present invention.
F It is a manufacturing process drawing showing another example of the load capacitance element in the amplification type solid-state imaging device according to the present invention.
FIG. 4 is a circuit configuration diagram of an amplification type solid-state imaging device.
FIG. 5 is a sectional view showing a semiconductor structure of a pixel MOS transistor.
FIG. 6 is a configuration diagram of a load capacitance element in a conventional amplification type solid-state imaging device.
[Explanation of symbols]
7,701,702 Load capacitance element
41 Insulating film
42 n⁻
43 Electrode made of polycrystalline silicon
44, 57 First capacitance element section
46 Insulating film
47 Electrode made of polycrystalline silicon
48, 58 Second capacitance element section
51 SiN film
551 Polycrystalline silicon electrode

Claims (5)

A first capacitor element portion made of the same material as the gate insulating film and the gate electrode of the first MOS transistor;
Capacitor composed of a second capacitor element formed by providing the material of the gate electrode of the second MOS transistor as a counter electrode via an insulating film made of a silicon nitride film on the first capacitance element portion on connected in parallel An amplification-type solid-state imaging device, wherein the device is built in as a capacitance device that samples and holds a signal charge. The first MOS transistor is a peripheral MOS transistor or a pixel MOS transistor;
2. The amplification type solid-state imaging device according to claim 1, wherein the second MOS transistor is a pixel MOS transistor or a peripheral MOS transistor. A first capacitor element portion made of the same material as the gate insulating film and the gate electrode of the first MOS transistor, and a material of the gate electrode of the second MOS transistor facing the first capacitor element portion via the insulating film; In an amplification type solid-state imaging device, a capacitance element configured by connecting a second capacitance element portion provided as an electrode in parallel is built in as a capacitance element for sampling and holding a signal charge.
The amplification type you characterized by comprising using a surface oxide film of the upper side electrode of the first capacitive element that occurs in the gate oxidation process as the insulating film of the second capacitive element of the second MOS transistor Solid-state imaging device. Forming a first insulating film and a first electrode material layer of the same material as the gate insulating film and the gate electrode of the first MOS transistor on the semiconductor region;
Forming a silicon nitride film on the first electrode material layer;
Simultaneously patterning the silicon nitride film and the first electrode material layer to form a second insulating film and a first electrode, and forming a first capacitor element portion including the semiconductor region, the first insulating film, and the first electrode The process of
After the gate of the second MOS transistor is oxidized, a second electrode made of a material of a gate electrode of the second MOS transistor is formed on the second insulating film to form the first electrode, the second insulating film, and the second electrode. Forming a second capacitive element portion composed of two electrodes;
A method for manufacturing an amplification type solid-state imaging device, comprising: forming a capacitor for sampling and holding signal charges by connecting the first capacitor and the second capacitor in parallel. A first insulating film and a first electrode made of the same material as the first insulating film and the gate electrode of the first MOS transistor are formed on the semiconductor region, and the first insulating film and the first electrode are formed from the semiconductor region, the first insulating film, and the first electrode. Forming a first capacitive element portion comprising:
Using the surface oxide film of the first electrode generated during the gate oxidation of the second MOS transistor as a second insulating film;
A second electrode is formed on the second insulating film by using a material of a gate electrode of the second MOS transistor, and a second capacitance element portion including the first electrode, the second insulating film, and the second electrode is formed. The process of
A method for manufacturing an amplification-type solid-state imaging device, comprising: forming a capacitance element that samples and holds a signal charge by connecting the first capacitance element part and the second capacitance element part in parallel.

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