JP3604101B2 - Flash memory controller - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a flash memory control device of an electronic device including a flash memory having a built-in program such as a facsimile machine, a copying machine, a personal computer, and a word processor, and particularly to an operation mode in which a program built in the flash memory cannot be read due to a malfunction or the like. The present invention relates to a flash memory control device that can automatically escape from the above mode when a transition has occurred.
[0002]
[Prior art]
2. Description of the Related Art In various types of electronic devices, flash memories are becoming widespread as non-volatile memories that retain their stored contents even when power is turned off. Data and programs are stored in the flash memory. In the latter case, the CPU sequentially reads out the programs from the flash memory and operates according to the programs.
[0003]
Generally, a flash memory has various operation modes. For example, the operation modes include a write mode for writing data (including a program) to the flash memory, a read (read) mode for reading data, and a command mode for executing various built-in functions. The operation mode of the flash memory generally changes to a read mode when the power is turned on or when the flash memory is reset, and thereafter shifts to another operation mode by a command (instruction) issued from a CPU or the like.
[0004]
However, if the program is embedded in the flash memory, and if the CPU issues a command to make a transition from the read mode to another operation mode, the CPU will not be able to read the program from the flash memory thereafter, and will not be able to operate. I will. Therefore, a program for returning the operation mode of the flash memory to the read mode under a certain condition is provided in a ROM or the like, or the program of the flash memory is copied to the RAM or the like, so that the operation mode of the flash memory is changed from the read mode to another mode. When making a transition, the program in the flash memory is jumped to the program in the ROM or RAM, and then the operation mode of the flash memory is set to the read mode in accordance with the program in the ROM or RAM, and the program returns to the program in the flash memory.
[0005]
However, the above countermeasures are effective when the flash memory shifts to another operation mode based on an instruction issued from the CPU or the like, but when the CPU operates according to the program in the flash memory, the malfunction, when writing to the flash memory is performed in collision voluntarily, whereby the operation mode of the flash memory ends up transition from the read mode to another mode, such a case a call to the subsequent program not Enabled, thus rendering the CPU inoperable. Conventionally, when the inoperable state as described above occurs, the power is turned off and then turned on again, and the flash memory is restored by returning to the read mode by pressing the reset key, etc. I was letting it.
[0006]
[Problems to be solved by the invention]
As described above, in the related art, when the operation mode shifts to an operation mode in which the program built in the flash memory cannot be read due to a malfunction or the like, the user must reset each one, and the operability is poor. There is a problem. An object of the present invention is to solve the above-described problems of the related art, and to automatically return to an operable state when a transition is made to an operation mode in which a program built in the flash memory cannot be read due to a malfunction or the like. It is an object of the present invention to provide a flash memory control device that can be used.
[0007]
[Means for Solving the Problems]
A flash memory control apparatus for an electronic apparatus having a flash memory having a built-in program, and a flash memory access detection circuit for detecting that the flash memory is accessed, detects that the flash memory is in the write state The access to the flash memory is detected by the write state detection circuit and the flash memory access detection circuit, and the fact that the flash memory is in the write state is detected by the write state detection circuit. wherein the mask signal masks state is released if normal writing is a reset signal generating circuit for generating a reset signal when showing the masked and such that the flash memory is reset by the reset signal And Sshumemori control device.
[0008]
[Action]
Than the structure described above, when writing to the flash memory is performed by such malfunction, Ru is immediately reset the flash memory.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of a flash memory control device according to a first embodiment of the present invention. As shown in the drawing, the flash memory control device of this embodiment includes a flash memory 1 having a built-in program, a flash memory access detection circuit 2 for detecting that the flash memory 1 is being accessed (addressed), and a flash memory 1 for writing. The flash memory 1 includes a write state detection circuit 3 for detecting a state, a flash memory 1 and a reset signal generation circuit (AND gate) 4 for generating a reset signal c for resetting the CPU 5.
[0010]
FIG. 2 is a timing chart of main signals in the above embodiment. Hereinafter, the operation of the first embodiment will be described with reference to FIGS. When the power is turned on or a reset key (not shown) is pressed, an initial reset signal b (Low level signal) is generated, and the flip-flops 6 and 7 and the D-type flip-flop 8 are generated by the signal. , 9, 10, and 11 are set (Q output is at a high level). Thereafter, the CPU 5 accesses the flash memory 1 (addressing by the address bus d), reads a program in the flash memory 1 via the data bus e, and operates according to the program.
[0011]
In such a state, a write operation to the flash memory 1 occurs due to a malfunction, and as a result, as described in the section of the related art, the operation mode of the flash memory 1 is set to a mode other than the read mode (write mode). −). When such a state occurs, the flash memory access detection circuit 2 detects that the flash memory 1 is being accessed. That is, the fact that writing to the flash memory 1 is performed means that an address belonging to the address space of the flash memory 1 is output to the address bus d by the CPU 5. Is decoded, it can be detected that the access (addressing) to the flash memory 1 has been performed. Thus, the high-level signal f is output from the flash memory detection circuit 2.
[0012]
On the other hand, when outputting an address to the address bus d, the CPU 5 outputs a state signal n indicating what the address output is for. Therefore, the write state detection circuit 3 decodes the state signal n, and outputs a high-level signal g when the state signal indicates the write state.
[0013]
The reset signal generation circuit 4 outputs a low-level reset signal c when the input signals f, g, and h are all high (see FIG. 2). The signal h is normally a mask signal of a high level, and the mask is released by a program and becomes a low level only when normal writing to the flash memory 1 is performed. That is, at the time of writing to the flash memory 1 due to a malfunction, the mask signal remains at the high level because the mask signal remains in the mask state.
[0014]
When the flip-flops 6 and 7 are reset by the reset signal c, the signals k and m go low, thereby resetting the flash memory 1 and the CPU 5. The D-type flip-flops 8, 9, 10, and 11 constitute a delay circuit. The Q output of the flip-flop 7 enters the D-input of the D-type flip-flop 8, and the input signal is a clock signal a (FIG. 2). ) Sequentially appear at the outputs of the subsequent D-type flip-flops 9, 10, 11 (see FIG. 2). Thus, the signal i and the signal j are generated, the flip-flop 6 is set by the signal i, and the flip-flop 7 is set by the signal j (see FIG. 2). That is, the reset period of the flash memory 1 and the CPU 5 ends.
[0015]
When the flash memory 1 is reset, the flash memory 1 returns to the read mode, and the CPU 5 is initialized by the reset to be in an operable state. It is also possible to adopt a configuration in which only the flash memory 1 is reset to the read mode without resetting the CPU 5, and the operation of the CPU 5 is restarted. However, the situation in which the CPU 5 can normally resume the operation in such a configuration is limited to a specific case. In the above operation, the reset period (reset release timing) of the CPU 5 is extended by a predetermined time from the reset period (reset release timing) of the flash memory 1. However, the CPU 5 ends the reset and restarts the operation. This is to ensure that the flash memory 1 has completed the reset process.
[0016]
【The invention's effect】
As described above, according to the present invention, writing to the flash memory is performed by such malfunction, whereby the CPU can not read the program, since immediately the flash memory is reset, which automatically operable Ru can return to the state.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a flash memory control device according to a first embodiment of the present invention.
FIG. 2 is a timing chart of the flash memory control device according to the first embodiment of the present invention.
[Explanation of symbols]
1: Flash memory 2: Flash memory access detection circuit 3: Write state detection circuit 4: Reset signal generation circuit 5: CPU
6, 7: flip-flops 8 to 11: D-type flip-flops

Claims (1)

A flash memory control device for an electronic device including a flash memory having a built-in program, wherein the flash memory access detection circuit detects that the flash memory is being accessed, and detects that the flash memory is in a write state. An access to the flash memory is detected by the write state detection circuit and the flash memory access detection circuit, and the flash memory is detected to be in the write state by the write state detection circuit. A reset signal generating circuit for generating a reset signal when the mask signal indicates that the mask state is released if the write operation is performed properly, and the flash memory is reset by the reset signal. To Sshumemori control device.

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