JP3620590B2 - Driving method of semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for driving a semiconductor memory device having a ferroelectric capacitor.
[0002]
[Prior art]
As a first conventional example of a semiconductor memory device having a ferroelectric capacitor, a field effect transistor (hereinafter referred to as FET) 1 and a ferroelectric capacitor 2 are provided as shown in FIG. It is known that the bit line BL is connected to the region 1a, the upper electrode of the ferroelectric capacitor 2 is connected to the source region 1b of the FET1, and the word line WL is connected to the gate electrode 1c of the FET1.
[0003]
The semiconductor memory device according to the first conventional example is a destructive read system in which recorded data is erased when data is read. For this reason, since a rewrite operation is required after the data is read, an operation (polarization inversion operation) for changing the polarization direction of the ferroelectric film is required for each data read operation.
[0004]
By the way, since a phenomenon called polarization fatigue deterioration occurs in the ferroelectric film, there is a problem that the polarization development characteristic of the ferroelectric film is remarkably deteriorated when the polarization inversion operation is repeated.
[0005]
Therefore, a semiconductor memory device according to a second conventional example as shown in FIG. 7 has been proposed. That is, the second conventional example is a non-destructive readout method in which the lower electrode 1b of the ferroelectric capacitor 2 is connected to the gate electrode 1c of the FET 1, and the ferroelectric capacitor 2 is used for controlling the gate potential of the FET 1. In FIG. 7, reference numeral 3 denotes a substrate.
[0006]
When writing data in the semiconductor memory device according to the second conventional example, a write voltage is applied between the upper electrode 2a of the ferroelectric capacitor 2 serving as a control electrode and the substrate 3.
[0007]
For example, when data is written by applying a positive voltage (control voltage) with respect to the substrate 3 to the upper electrode 2 a, downward polarization occurs in the ferroelectric film 2 c of the ferroelectric capacitor 2. Thereafter, even if the upper electrode 2a is grounded, the positive charge remains in the gate electrode 1c of the FET 1, so that the potential of the gate electrode 1c becomes positive.
[0008]
If the potential of the gate electrode 1c exceeds the threshold voltage of the FET 1, the FET 1 is in an on state. Therefore, if a potential difference is applied between the drain region 1a and the source region 1b, the drain region 1a and the source region 1b Current flows between the two. Such a logical state of the ferroelectric memory is defined as “1”, for example.
[0009]
On the other hand, when a voltage that is negative with respect to the substrate 3 is applied to the upper electrode 2 a of the ferroelectric capacitor 2, upward polarization occurs in the ferroelectric film 2 c of the ferroelectric capacitor 2. After that, even if the upper electrode 2a is grounded, since the negative charge remains in the gate electrode 1c of the FET 1, the potential of the gate electrode 1c becomes negative. In this case, since the potential of the gate electrode 1c is always smaller than the threshold voltage of the FET 1, the FET 1 is in an off state. Therefore, even if a potential difference is applied between the drain region 1a and the source region 1b, No current flows between the source region 1b. Such a logical state of the ferroelectric memory is defined as “0”, for example.
[0010]
Even if the power supply to the ferroelectric capacitor 2 is cut off, that is, even if a voltage is not applied to the upper electrode 2a of the ferroelectric capacitor 2, the above-described respective logical states are preserved, so that the nonvolatile memory is stored. A device is realized. That is, when the power supply is turned off for a certain period and then supplied again to apply a voltage between the drain region 1a and the source region 1b, when the logic state is "1", the drain region 1a and the source region 1b Since the current flows between them, the data “1” can be read out. On the other hand, when the logic state is “0”, the current does not flow between the drain region 1a and the source region 1b. Can do.
[0011]
[Problems to be solved by the invention]
In order to correctly retain data even during the power-off period (the characteristic of retaining data in this way is called retention), even during the power-off period, when the data is “1”, the gate electrode 1c of the FET 1 Is always maintained higher than the threshold voltage of the FET 1, and when the data is “0”, the potential of the gate electrode 1 c of the FET 1 must always be maintained at a negative voltage.
[0012]
Incidentally, during the power-off period, the upper electrode 2a and the substrate 3 of the ferroelectric capacitor 2 are at the ground potential, so that the potential of the gate electrode 1c is isolated. Therefore, ideally, as shown in FIG. 8, the first of the hysteresis loop 4 at the time of writing data to the ferroelectric capacitor 2 and the gate capacitance load line 7 of the FET 1 when the bias voltage is 0V. Is the potential of the gate electrode 1c for the data "1", and the second intersection c of the hysteresis loop 4 and the gate capacitance load line 8 is the potential of the gate electrode 1c for the data "0". In FIG. 8, the vertical axis indicates the charge Q appearing on the upper electrode 2a (or the gate electrode 1c), and the horizontal axis indicates the voltage V.
[0013]
However, in reality, the ferroelectric capacitor 2 is not an ideal insulator but has a resistance component, so that the potential of the gate electrode 1c drops through this resistance component. This potential drop is exponential and has a time constant obtained by multiplying the parallel combined capacitance of the gate capacitance of the FET 1 and the capacitance of the ferroelectric capacitor 2 and the resistance component of the ferroelectric capacitor 2. This time constant is at most 10 ⁴ About seconds. Therefore, the potential of the gate electrode 1c is halved in a few hours.
[0014]
As shown in FIG. 8, since the potential of the gate electrode 1c is about 1V at the first intersection c, when this potential is halved, the potential of the gate electrode 1c becomes about 0.5V and the threshold value of the FET 1 is reached. Since the voltage is lower than the voltage (generally about 0.7 V), the FET 1 that should be in the on state is turned off in a short time.
[0015]
As described above, the ferroelectric memory using the ferroelectric capacitor for controlling the gate potential of the FET has an advantage that the rewriting operation is not necessary after the data is read. Has a problem. That is, a potential is generated at the gate electrode of the FET after data is written, and the ability to hold the gate potential determines the retention characteristics. However, until the ferroelectric capacitor is discharged by the resistance component of the ferroelectric capacitor. Since the time constant is short, the data holding ability is short, that is, the retention characteristic is not good.
[0016]
Therefore, we considered a semiconductor memory device as shown in FIG. Hereinafter, the semiconductor memory device shown in FIG. 9 is referred to as a semiconductor memory device as a premise of the present invention.
[0017]
In the memory cell block of the first column constituting the semiconductor memory device that is the premise of the present invention, a plurality of, for example, four ferroelectric capacitors CF11, CF21, CF31, and CF41 are connected in series in the bit line direction. At the same time, each ferroelectric capacitor CF11, CF21, CF31, CF41 is connected in parallel with a selection field effect transistor (hereinafter simply referred to as a selection transistor) Q11, Q21, Q31, Q41. A memory cell is constituted by the capacitor and each selection transistor. A plurality of ferroelectric capacitors CF11, CF21, CF31, and CF41 are selected at the lower end side of the series circuit of the first column formed by connecting a plurality of ferroelectric capacitors CF11, CF21, CF31, and CF41 in series. A first read field effect transistor (hereinafter simply referred to as a read transistor) Q51 for reading data by detecting the polarization deviation of the ferroelectric film of the ferroelectric capacitor is connected.
[0018]
In the second memory cell block, a plurality of ferroelectric capacitors CF12, CF22, CF32, and CF42 are connected in series in the bit line direction as in the first memory cell block, and each ferroelectric capacitor is connected. Selection transistors Q12, Q22, Q32, Q42 are connected in parallel to the body capacitors CF12, CF22, CF32, CF42, and a plurality of ferroelectric capacitors CF12, CF22, CF32, CF42 are connected in series. Connected to the lower end side of the series circuit of the column is a second read transistor Q52 for reading data by detecting the polarization deviation of the ferroelectric film of the selected ferroelectric capacitor.
[0019]
The gate electrodes of the selection transistors Q11 and Q12 constituting the memory cells in the first row are connected in common to the first word line WL1, and the gate electrodes of the selection transistors Q21 and Q22 constituting the memory cells in the second row are the second. The gate electrodes of the selection transistors Q31 and Q32 that are commonly connected to the second word line WL2 and that constitute the memory cell in the third row are commonly connected to the third word line WL3 and that constitute the memory cell in the fourth row. The gate electrodes of the transistors Q41 and Q42 are commonly connected to the fourth word line WL4.
[0020]
The upper end of the first column series circuit, that is, the upper electrode of the ferroelectric capacitor CF11 in the first row is connected to the first control line (first set line) BS1, and the first column series circuit. , That is, the lower electrode of the ferroelectric capacitor CF41 in the fourth row is connected to the gate electrode of the first read transistor Q51, and the drain region of the first read transistor Q51 is connected to the first bit line BL1. ing.
[0021]
The upper end of the second column series circuit, that is, the upper electrode of the ferroelectric capacitor CF12 in the first row is connected to the second control line (second set line) BS2, and the second column series circuit. , That is, the lower electrode of the fourth row ferroelectric capacitor CF42 is connected to the gate electrode of the first read transistor Q52, and the drain region of the second read transistor Q52 is connected to the second bit line BL2. ing.
[0022]
The source region of the first read transistor Q51 and the source region of the second read transistor Q52 are commonly connected to a plate line (reset line) CP.
[0023]
The write operation in the semiconductor memory device which is the premise of the present invention is as follows. Here, a case where data is written to the ferroelectric capacitor CF21 constituting the memory cell in the second row of the first column will be described.
[0024]
First, a high voltage is applied to the word lines WL1, WL3, WL4 to turn on the selection transistors Q11, Q31, Q41, while a ground voltage is applied to the word line WL2 to turn off the selection transistor Q21. In this way, the ferroelectric capacitor CF21 is selected, and the capacitance of the ferroelectric capacitor CF21 and the gate capacitance of the first read transistor Q51 are connected in series, and one end of the series capacitance circuit is connected. It becomes the well region of the first read transistor Q51 and the other end of the series capacitance circuit becomes the first control line BS1.
[0025]
Next, when the well region of the first read transistor Q51 is grounded and a write voltage is applied to the first control line BS1, the direction of polarization of the ferroelectric capacitor CF21 changes according to the polarity of the write voltage. . Thereafter, when a high voltage is applied to the word line WL2 to turn on the selection transistor Q21, the upper electrode and the lower electrode of the ferroelectric capacitor CF21 are short-circuited, so that the ferroelectric capacitor CF21 is reset.
[0026]
The operation of reading data from the ferroelectric capacitor CF21 constituting the memory cell in the second column of the first row is as follows.
[0027]
First, as in the write operation, a high voltage is applied to the word lines WL1, WL3, WL4 to turn on the selection transistors Q11, Q21, Q41, while a ground voltage is applied to the word line WL2 to select the selection transistor Q31. Turn off. In this way, the ferroelectric capacitor CF21 is selected, and the capacitance of the ferroelectric capacitor CF21 and the gate capacitance of the first read transistor Q51 are connected in series, and one end of the series capacitance circuit is connected. The first read transistor Q51 becomes the well region and the other end becomes the first control line BS1.
[0028]
Next, when the well region of the first read transistor Q51 is grounded and a read voltage is applied to the first control line BS1, the read voltage is changed between the capacitance value of the ferroelectric capacitor CF21 and the first read transistor Q51. A voltage divided according to the gate capacitance value of the first read transistor Q51 is applied to the gate electrode of the first read transistor Q51, and between the source region and the drain region of the first read transistor Q51 according to the potential of the gate electrode. Current flows between the plate line CP and the first bit line BL1.
[0029]
In the semiconductor memory device which is the premise of the present invention, the polarization value of the ferroelectric film differs depending on the data written in the ferroelectric capacitor, so the polarization value of the ferroelectric film when a read voltage is applied The changes are also different. Since the ratio of the change in polarization value to the change in voltage is a capacitance value, the capacitance value of the ferroelectric capacitor differs depending on the polarization value of the ferroelectric film corresponding to the written data. That is, the capacitance value of the selected ferroelectric capacitor CF21 has a different value depending on the polarization value of the ferroelectric film of the ferroelectric capacitor CF21.
[0030]
Incidentally, since the gate voltage of the first read transistor Q51 is determined by the capacitance division of the capacitance value of the ferroelectric capacitor CF21 and the gate capacitance value of the first read transistor Q51, the ferroelectric film of the ferroelectric capacitor CF21. The gate capacitance value of the first read transistor Q51 changes according to the polarization value.
[0031]
For this reason, since the value of the current flowing between the source region and the drain region of the first read transistor Q51 changes according to the data written in the ferroelectric capacitor CF21, the change in the current value is detected. As a result, the data written in the ferroelectric capacitor CF21 can be read out.
[0032]
As described above, in the semiconductor memory device that is the premise of the present invention, a voltage is applied to the ferroelectric capacitor during the data holding period in order to reset the ferroelectric capacitor after data is written. Because there is no, it has excellent retention characteristics. That is, since the potential difference of the ferroelectric capacitor is not held, but the polarization state of the ferroelectric film is held, the retention characteristic is excellent.
[0033]
However, in the semiconductor memory device which is the premise of the present invention, the parasitic capacitance value existing between the ferroelectric capacitor and the read transistor differs for each address. For example, the parasitic capacitance value between the fourth row ferroelectric capacitor CF41 and the first read transistor Q51 is represented by q. ₁ And the parasitic capacitance value for each of the select transistors Q11, Q21, Q31, Q41 is q ₂ Then, the parasitic capacitance value when reading the data written in the ferroelectric capacitor CF41 in the fourth column is q ₁ On the other hand, the parasitic capacitance value when reading the data written in the ferroelectric capacitor CF11 in the first column is q ₁ + 3 × q ₂ It becomes.
[0034]
As described above, since the parasitic capacitance value existing between the ferroelectric capacitor and the read transistor is different for each address, the gate voltage of the read transistor during the read operation is different for each address. There is a problem of becoming unstable.
[0035]
In view of the above, an object of the present invention is to improve the retention characteristics of a semiconductor memory device and stabilize the operation of a read transistor.
[0036]
[Means for Solving the Problems]
In order to achieve the above object, a driving method of a semiconductor memory device according to the present invention includes a ferroelectric capacitor for storing data by polarization deviation of a ferroelectric film, and a series connection with the ferroelectric capacitor. A memory cell block having a plurality of memory cells connected in parallel to each other and a first common node of two common nodes constituting the memory cell block, and reading Semiconductor having a set line to which a voltage is applied and a capacitive load connected to the second common node of the two common nodes and detecting polarization deviation of the ferroelectric film of the ferroelectric capacitor A method for driving a storage device, and a cell connected in series to a data read ferroelectric capacitor from which data is to be read out of a plurality of ferroelectric capacitors. While the selection transistor is turned on, the cell selection transistor connected in series to the ferroelectric capacitor that does not read data among the plurality of ferroelectric capacitors is turned off, and one of the data reading ferroelectric capacitors is turned off. A first step of connecting the electrode to the set line via the first common node and connecting the other electrode of the data read ferroelectric capacitor to the capacitive load via the second common node; And a third step of removing the read voltage applied to the set line, and the read voltage applied in the second step is read in the third step. When the voltage is removed, the polarization deviation of the ferroelectric film of the data read ferroelectric capacitor is set so as to return to the deviation before reading the data. It is.
[0037]
According to the method for driving a semiconductor memory device of the present invention, the read voltage applied in the second step has a large polarization deviation of the ferroelectric film when the read voltage is removed in the third step. Since the size is set so as to return to the deviation before reading the value data, the read data is not destroyed when the data stored in the ferroelectric capacitor is read. There is no need to do. This eliminates the need to change the polarization direction of the ferroelectric film (polarization inversion operation) every time data is read out, and it is difficult for polarization fatigue deterioration to occur in the ferroelectric film of the ferroelectric capacitor. The number of times the storage device can be read is greatly improved.
[0038]
In addition, when reading data by moving charge from the data read ferroelectric capacitor to the capacitive load, the unselected ferroelectric capacitors are separated from the capacitive load by the off-state cell selection transistor, Since the unselected ferroelectric capacitor does not act as a parasitic capacitance, the voltage applied to the capacitive load does not vary when data is read.
[0039]
The method for driving a semiconductor memory device according to the present invention further includes a fourth step of making the potential difference between one electrode and the other electrode of the data read ferroelectric capacitor zero after the third step. Preferably it is.
[0040]
As described above, when the potential difference between the one electrode and the other electrode of the ferroelectric capacitor is made zero after the third step, the potential decrease due to the resistance component of the ferroelectric capacitor is suppressed. Therefore, the retention characteristics are improved.
[0041]
In the method for driving a semiconductor memory device according to the present invention, the read voltage applied in the second step is between one electrode and the other electrode of the ferroelectric capacitor when the read voltage is applied. It is preferable that the potential difference to be generated is set so as to be less than the coercive voltage of the ferroelectric capacitor.
[0042]
In this way, when the read voltage applied in the second step is removed, the polarization deviation of the ferroelectric film of the data read ferroelectric capacitor can be reliably returned to the deviation before the data read. it can.
[0043]
In the method of driving a semiconductor memory device according to the present invention, it is preferable that the ferroelectric capacitor is disposed on the first common node side and the cell selection transistor is disposed on the second common node side.
[0044]
In this case, the parasitic capacitance connected to the second common node can be reduced as compared with the case where the cell selection transistor is interposed between the first common node and the ferroelectric capacitor. Thus, a more stable read operation becomes possible.
[0045]
In the method for driving a semiconductor memory device according to the present invention, the capacitive load is preferably a field effect transistor having a gate electrode connected to the second common node.
[0046]
In this way, the voltage applied in the second step can be divided based on the capacitance ratio between the capacitance value of the ferroelectric capacitor and the gate capacitance value of the field effect transistor, so that it is applied to the ferroelectric capacitor. It is easy to set the voltage to be such that when the read voltage is removed, the polarization deviation of the ferroelectric film returns to the deviation before reading data, and the field effect transistor By detecting the current flowing between the drain region and the source region, the polarization deviation of the ferroelectric film can be reliably detected.
[0047]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
The semiconductor memory device and the driving method thereof according to the first embodiment of the present invention will be described below with reference to FIG.
[0048]
FIG. 1 shows an equivalent circuit of first and second memory cell blocks constituting the semiconductor memory device according to the first embodiment.
[0049]
As shown in FIG. 1, in the first memory cell block, a plurality of ferroelectric capacitors CF11, CF12, CF13, and CF14 that store data by deviation of polarization of the ferroelectric film, and the plurality of ferroelectric capacitors. A plurality of memory cells comprising a plurality of cell selection field effect transistors (hereinafter simply referred to as cell selection transistors) Q11, Q12, Q13, Q14 connected in series to each of body capacitors CF11, CF12, CF13, CF14 Are connected in parallel with each other.
[0050]
The first common node N11 of the first memory cell block is a first memory cell block selection field effect transistor transistor (hereinafter simply referred to as a first block selection transistor) that selects the first memory cell block. It is connected via Q10 to the first set line SET1 to which the read voltage is applied. The gate electrode of the first block selection transistor Q10 is connected to the block selection line BS. The second common node N12 is connected to the first reset line RST1 via a first write field effect transistor (hereinafter simply referred to as a first write transistor) Q15, and as a capacitive load. Of the first readout field effect transistor (hereinafter simply referred to as the first readout transistor) Q16. The gate electrode of the first write transistor Q15 is connected to the first write transistor control line RE1, the drain region of the first read transistor Q16 is connected to the bit line BL, and the source region of the first read transistor Q16. Are connected to the first reset line RST1.
[0051]
Further, word lines WL11, WL12, WL13, and WL14 are connected to the gate electrodes of the cell selection transistors Q11, Q12, Q13, and Q14, respectively.
[0052]
Also in the second memory cell block, a plurality of ferroelectric capacitors CF21, CF22, CF23, and CF24 that store data by the polarization deviation of the ferroelectric film, and the plurality of ferroelectric capacitors CF21, CF22 are stored. , CF23, and CF24, a plurality of memory cells including a plurality of cell selection transistors Q21, Q22, Q23, and Q24 connected in series are connected in parallel to each other.
[0053]
The first common node N21 of the second memory cell block is a second memory cell block selection field effect transistor (hereinafter simply referred to as a second block selection transistor) Q20 that selects the second memory cell block. And is connected to a second set line SET2 to which a read voltage is applied. The gate electrode of the second block selection transistor Q20 is connected to the block selection line BS. The second common node N22 is connected to the second reset line RST2 via a second write field effect transistor transistor (hereinafter simply referred to as a second write transistor) Q25, and has a capacitive load. Is connected to the gate electrode of a second read field effect transistor (hereinafter simply referred to as a second read transistor) Q26. The gate electrode of the second write transistor Q25 is connected to the second write transistor control line RE2, the drain region of the second read transistor Q26 is connected to the bit line BL, and the source region of the second read transistor Q26. Are connected to the second reset line RST2.
[0054]
In addition, word lines WL21, WL22, WL23, and WL24 are connected to the gate electrodes of the cell selection transistors Q21, Q22, Q23, and Q24, respectively.
[0055]
As a feature of the first embodiment, the ferroelectric capacitors CF11, CF12, CF13, CF14 constituting the first memory cell block are arranged on the first common node N11 side and the cell selection transistors Q11, Q12, Q13, Q14 is disposed on the second common node N12 side, and the ferroelectric capacitors CF21, CF22, CF23, and CF24 constituting the second memory cell block are disposed on the first common node N21 side and cell selection is performed. Transistors Q21, Q22, Q23, and Q24 are arranged on the second common node N22 side.
[0056]
The capacitance values of the plurality of ferroelectric capacitors CF11, CF12, CF13, CF14, CF21, CF22, CF23, and CF24 constituting the first memory cell block and the second memory cell block are equal to each other and the plurality of cells. The selection transistors Q11, Q12, Q13, Q14, Q21, Q22, Q23, and Q24 have the same size.
[0057]
Although not shown in FIG. 1, the bit line BL is connected to the sense amplifier SA to which the reference voltage VREF is input, and the voltage change appearing on the bit line BL is compared with the reference voltage VREF by the sense amplifier SA. As a result, the data stored in the selected ferroelectric capacitor can be read out.
[0058]
(Data write operation)
The data write operation in the semiconductor memory device according to the first embodiment will be described below. Here, a case where data is written to the ferroelectric capacitor CF12 constituting the memory cell block in the second column of the first memory cell block will be described.
[0059]
First, a high signal is applied to the block selection line BS, the first write transistor control line RE1, and the word line WL12 to turn on the first block selection transistor Q10, the first write transistor Q15, and the cell selection transistor Q12. On the other hand, a low signal is applied to the second write transistor control line RE2 and the word lines WL11, WL13, WL14, WL21, WL22, WL23, WL24, and the second write transistor Q25, cell selection transistors Q11, Q13, Q14. , Q21, Q22, Q23, Q24 are turned off.
[0060]
Thus, the memory cell block in the second column of the first memory cell block is selected.
[0061]
Next, when writing data “1”, a high signal is applied to the first set line SET1 and a low signal is applied to the first reset line RST1, and when data “0” is written, A low signal is applied to the first set line SET1, and a high signal is applied to the first reset line RST1.
[0062]
Thus, the set voltage is applied to the upper electrode of the ferroelectric capacitor CF12 constituting the memory cell block in the second column of the first memory cell block, and the reset voltage is applied to the lower electrode of the ferroelectric capacitor CF12. Therefore, when data “1” is written, the polarization of the ferroelectric film of the ferroelectric capacitor CF2 is downward, while when data “0” is written, the ferroelectric capacitor CF2 The polarization of the ferroelectric film is upward.
[0063]
Next, when the data write operation is completed, the first set line SET1 and the first reset line RST1 are set to the same potential, and then the block selection line BS, the first write transistor control line RE1, and the word line WL12 are set. A low signal is applied to turn off the first block selection transistor Q10, the first write transistor Q15, and the cell selection transistor Q12.
[0064]
In this case, since the potential difference applied between the upper electrode and the lower electrode of the ferroelectric capacitor CF12 becomes zero, even if the power is turned off in this state, the ferroelectric substance of the ferroelectric capacitor CF12 Since the state of polarization of the film is maintained, the data written in the ferroelectric capacitor CF12 is saved. As a result, the semiconductor memory device exhibits the function of a nonvolatile memory.
[0065]
(Data read operation)
Hereinafter, an operation of reading data from the ferroelectric capacitor CF12 constituting the memory cell block in the second column of the first memory cell block will be described.
[0066]
First, a high signal is applied to the block selection line BS and the word line WL12 to turn on the first block selection transistor Q10 and the cell selection transistor Q12, while the first write transistor control line RE1 and the word line WL11, A low signal is applied to WL13, WL14, WL21, WL22, WL23, and WL24 to turn off the first write transistor Q15 and the cell selection transistors Q11, Q13, Q14, Q21, Q22, Q23, and Q24. Further, a high signal is applied to the second write transistor control line RE2 to turn on the second write transistor Q25.
[0067]
Thus, the first set line SET1 and the upper electrode of the ferroelectric capacitor CF12 are connected, and the lower electrode of the ferroelectric capacitor CF12 and the gate electrode of the first read transistor Q16 are connected. . The other ferroelectric capacitors CF11, CF13, CF14 of the first memory cell block are disconnected from the first read transistor Q16, and CF21, CF22, CF23, CF24 of the second memory cell block are the second read transistors. Separated from Q26.
[0068]
In this state, when a read voltage (for example, 1.5 V) is applied to the first set line SET1, the read voltage is a capacitance ratio between the capacitance value of the ferroelectric capacitor CF12 and the gate capacitance value of the first read transistor Q16. The voltage divided by is applied to the gate electrode of the first read transistor Q16.
[0069]
Since the direction of polarization of the ferroelectric film of the ferroelectric capacitor CF12 differs between the case where the data “1” is stored in the ferroelectric capacitor CF12 and the case where the data “0” is stored, the hysteresis line Therefore, the magnitude of the voltage applied to the gate electrode of the first read transistor Q16 is different. Therefore, the gate potential of the first read transistor Q16 differs depending on the stored data. Hereinafter, this will be described with reference to FIG.
[0070]
When a read voltage of 1.5 V is applied to the first set line SET1, the point where polarization is maintained is replaced with the origin, and when the gate capacitance is a load line, this load line is the voltage axis (horizontal axis) Is equivalent to crossing at 1.5V. As shown in FIG. 2, this is equivalent to providing the first gate capacity load line 8 for data “1”, and the second gate capacity load line 9 for data “0”. Equal to giving.
[0071]
When a voltage is applied to the first set line SET1, a voltage is also applied to the ferroelectric capacitor CF12. Therefore, when the potential of the first set line SET1 is 1.5 V, the polarization changes along the first curve A for the data “1”, and the first curve A and the first gate capacitance are changed. While balancing at the intersection point g with the load line 8, for data “0”, the polarization changes along the second curve B and the intersection point h between the second curve B and the second gate capacitance load line 9. Balance.
[0072]
The intersection point i, intersection point j, and intersection point k determine the distribution of potentials in each polarization state. For data “1”, about 0.7 V between the intersection point i and the intersection point j is the first readout. In addition to being distributed as the gate potential of the transistor Q16, about 0.9 V between the intersection point i and the intersection point k is distributed as the gate potential of the first read transistor Q16 for data “0”.
[0073]
Therefore, if the threshold voltage of the first read transistor Q16 is set to 0.8 V, which is an intermediate value between 0.7 V and 0.9 V, the first read transistor is read when reading data “1”. When Q16 is turned off and data “0” is read, the first read transistor Q16 is turned on.
[0074]
Therefore, when a potential difference is applied between the bit line BL and the first reset line RST1 shown in FIG. 1, no current flows through the first read transistor Q16 when data “1” is stored. Since current flows through the first read transistor Q16 when data “0” is stored, the stored data becomes “1” by detecting the current flowing through the first read transistor Q16 by the sense amplifier SA. Or “0”.
[0075]
By the way, in this read operation, the application of the read voltage to the first set line SET1 acts in the direction of increasing the polarization with respect to the data “1”, but the polarization with respect to the data “0”. Acts in the reverse direction. Therefore, when the voltage applied to the ferroelectric capacitor CF12 exceeds the coercive voltage, the polarization is reversed. In the first embodiment, when the data is “0”, the ferroelectric capacitor CF12 Since the applied voltage is 0.6 V, which is smaller than the point m that becomes the coercive voltage, the polarization does not invert, so there is no possibility that stored data changes.
[0076]
Here, by adjusting the capacitance value of the ferroelectric capacitor CF12 and the gate capacitance value of the first read transistor Q16, it is applied between the first set line SET1 and the substrate of the first read transistor Q16. And the voltage applied between the upper electrode and the lower electrode of the ferroelectric capacitor CF12 and the voltage applied between the gate electrode and the substrate in the first read transistor Q16, The voltage applied to the ferroelectric capacitor CF12 is preferably set to a value that does not exceed the coercive voltage of the ferroelectric capacitor CF12, that is, a value that does not reverse the polarization.
[0077]
In the first embodiment, the voltage applied to the ferroelectric capacitor CF12 during the read operation is set to a value that does not exceed the coercive voltage of the ferroelectric capacitor CF12. However, the present invention is not limited to this. When the read voltage applied to the ferroelectric capacitor CF12 is removed, the polarization deviation of the ferroelectric film of the ferroelectric capacitor CF12 returns to the deviation before reading data. That's fine.
[0078]
Thus, according to the first embodiment, since the polarization of the ferroelectric film of the ferroelectric capacitor CF12 is not reversed when the read operation is performed, the polarization of the ferroelectric film is changed every time the data read operation is performed. An operation to change the direction (polarization inversion operation) is not necessary. For this reason, since the polarization fatigue deterioration hardly occurs in the ferroelectric film of the ferroelectric capacitor CF12, the retention characteristic of the semiconductor memory device is greatly improved.
[0079]
When the data read operation is completed, a low signal is applied to the first set line SET1 and the first reset line RST1 to make the potential difference between the upper electrode and the lower electrode of the ferroelectric capacitor CF12 zero.
[0080]
Next, a high signal is applied to the first write transistor control line RE1 to turn on the first write transistor Q15. Thereafter, a low signal is applied to the block selection line BS and the word line WL2 to turn off the first block selection transistor Q10 and the cell selection transistor Q12.
[0081]
During the read operation, the gate potential of the first read transistor Q16, which is a floating node, fluctuates due to the leakage current of the ferroelectric capacitor CF12 and the cell selection transistor Q12. This operation resets the floating node. .
[0082]
According to the first embodiment, since the capacitance values of the ferroelectric capacitors CF11, CF12, CF13, and CF14 are equal to each other, and the sizes of the cell selection transistors Q11, Q12, Q13, and Q14 are equal to each other, each ferroelectric capacitor CF11. , CF12, CF13, CF14 and the first read transistor Q16 have the same parasitic capacitance value, so that the gate potential of the first read transistor Q16 depends on the address of the ferroelectric capacitor to be read. The problem of variation does not occur.
[0083]
That is, in the first memory cell block, the cell selection transistors Q11, Q12, Q13, Q14 are connected between the ferroelectric capacitors CF11, CF12, CF13, CF14 and the first read transistor Q16. When data is read by moving charges from the ferroelectric capacitor CF12 of the selected memory cell to the gate electrode of the first read transistor Q16, the ferroelectric capacitors CF11, CF13, and CF14 of the unselected memory cells are The cell selection transistors Q11, Q13, and Q14 in the off state are disconnected from the first read transistor Q16. For this reason, since the ferroelectric capacitors CF11, CF13, and CF14 that constitute an unselected memory cell and have large capacitance values do not function as parasitic capacitances, the operating voltage of the first read transistor Q16 does not vary.
[0084]
During the read operation, the gate electrode of the second read transistor Q26 is connected to the second reset line RST2 via the second write transistor Q25, and the second reset line RST2 is grounded. Thus, the second read transistor Q26 can be surely turned off. Thereby, the data read operation from the first memory cell block can be stably performed.
[0085]
(Second Embodiment)
A semiconductor memory device and a driving method thereof according to the second embodiment of the present invention will be described below with reference to FIG.
[0086]
FIG. 3 shows an equivalent circuit of the first memory cell block constituting the semiconductor memory device according to the second embodiment. In the second memory cell block, an equivalent circuit similar to that of the first memory cell block is provided, but the illustration is omitted.
[0087]
As shown in FIG. 3, a plurality of ferroelectric capacitors CF11, CF12, CF13, CF14 for storing data according to the polarization deviation of the ferroelectric film, and the plurality of ferroelectric capacitors CF11, CF12, CF13, CF14. A plurality of memory cells composed of a plurality of cell selection transistors Q11, Q12, Q13, and Q14 connected in series to each of these are connected in parallel to each other.
[0088]
The first common node N11 is connected to a first set line SET1 to which a read voltage is applied via a first block selection transistor transistor Q10, and the gate electrode of the first block selection transistor Q10 is a block. It is connected to the selection line BS. The second common node N12 is connected to the first reset line RST1 through the first write transistor Q15, and is connected to the gate electrode of the first read transistor Q16 as a capacitive load. The gate electrode of the first write transistor Q15 is connected to the first write transistor control line RE1, the drain region of the first read transistor Q16 is connected to the bit line BL, and the source region of the first read transistor Q16. Are connected to the first reset line RST1.
[0089]
Further, word lines WL11, WL12, WL13, and WL14 are connected to the gate electrodes of the cell selection transistors Q11, Q12, Q13, and Q14, respectively.
[0090]
As a feature of the second embodiment, the cell selection transistors Q11, Q12, Q13, and Q14 are arranged on the first common node N11 side, and the ferroelectric capacitors CF11, CF12, CF13, and CF14 are the first common node. It is arranged on the node N12 side.
[0091]
Also in the second embodiment, the capacitance values of the plurality of ferroelectric capacitors CF11, CF12, CF13, and CF14 are equal to each other, and the sizes of the plurality of cell selection transistors Q11, Q12, Q13, and Q14 are equal to each other.
[0092]
Since the driving method of the semiconductor memory device according to the second embodiment is the same as that of the first embodiment, the description thereof is omitted.
[0093]
According to the driving method of the semiconductor memory device according to the second embodiment, the polarization of the ferroelectric film of the ferroelectric capacitor CF12 is not reversed when the read operation is performed, as in the first embodiment. Since the polarization fatigue deterioration hardly occurs in the ferroelectric film of the body capacitor CF12, the retention characteristic of the semiconductor memory device is greatly improved.
[0094]
Here, a comparison between the first embodiment and the second embodiment will be described. In the first embodiment, the ferroelectric capacitors CF11, CF12, CF13, and CF14 are disposed on the first common node N11 side, and the cell selection transistors Q11, Q12, Q13, and Q14 are the second common node. Since it is arranged on the N12 side, cell select transistors Q11, Q12, Q13, Q14 are provided between the first common node N11 and the ferroelectric capacitors CF11, CF12, CF13, CF14 as in the second embodiment. The time required for driving can be shortened as compared with the case where the is interposed. That is, in the first embodiment, the capacitance between the gate and the source of the cell selection transistors Q11, Q13, Q14 connected in series to the unselected ferroelectric capacitors CF11, CF13, CF14 acts as a parasitic capacitance. However, since the parasitic capacitance is small, there is no particular problem, so that high speed operation is possible. On the other hand, in the second embodiment, since the large capacitances of the unselected ferroelectric capacitors CF11, CF13, and CF14 function as parasitic capacitances, there is a problem that it takes a long time to drive. .
[0095]
(Third embodiment)
Hereinafter, a semiconductor memory device and a driving method thereof according to the third embodiment of the present invention will be described with reference to FIG.
[0096]
FIG. 4 shows an equivalent circuit of the first memory cell block constituting the semiconductor memory device according to the third embodiment. In the second memory cell block, an equivalent circuit similar to that of the first memory cell block is provided, but the illustration is omitted.
[0097]
As shown in FIG. 4, in the first memory cell block, a plurality of ferroelectric capacitors CF11, CF12, CF13, and CF14 that store data by polarization deviation of the ferroelectric film, and a plurality of ferroelectric materials A plurality of first cell selection transistors Q11A, Q12A, Q13A, Q14A connected to the upper electrodes of the capacitors CF11, CF12, CF13, and CF14, and a plurality of ferroelectric capacitors CF11, CF12, CF13, and CF14 are connected to the lower electrodes. A plurality of memory cells composed of the plurality of second cell selection transistors Q11B, Q12B, Q13B, and Q14B are connected in parallel to each other.
[0098]
The first common node N11 is connected via a first block selection transistor transistor Q10 to a first set line SET1 to which a read voltage is applied, and the gate electrode of the first block selection transistor Q10 is a block. It is connected to the selection line BS. The second common node N12 is connected to the first reset line RST1 via the first write transistor Q15, and is connected to the gate electrode of the first read transistor Q16 as a capacitive load. The gate electrode of the first write transistor Q15 is connected to the first write transistor control line RE1, the drain region of the first read transistor Q16 is connected to the bit line BL, and the source region of the first read transistor Q16. Are connected to the first reset line RST1.
[0099]
In addition, the first word lines WL11A, WL12A, WL13A, and WL14A are connected to the gate electrodes of the first cell selection transistors Q11A, Q12A, Q13A, and Q14A, respectively, and the second cell selection transistors Q11B, First word lines WL11B, WL12B, WL13B, and WL14B are connected to the gate electrodes of Q12B, Q13B, and Q14B, respectively.
[0100]
As a feature of the third embodiment, first cell selection transistors Q11A, Q12A, Q13A, and Q14A are respectively interposed between the ferroelectric capacitors CF11, CF12, CF13, and CF14 and the first common node N11. In addition, second cell selection transistors Q11B, Q12B, Q13B, and Q14B are respectively interposed between the ferroelectric capacitors CF11, CF12, CF13, and CF14 and the second common node N12.
[0101]
In the third embodiment, the capacitance values of the plurality of ferroelectric capacitors CF11, CF12, CF13, and CF14 are equal to each other, and the sizes of the plurality of first cell selection transistors Q11A, Q12A, Q13A, and Q14A are equal to each other. The second cell selection transistors Q11B, Q12B, Q13B, and Q14B have the same size.
[0102]
When a data write operation or read operation is performed on the memory cell block of the semiconductor memory device according to the third embodiment, the first memory cell connected in series with the ferroelectric capacitor CF12 of the selected memory cell. The cell selection transistor Q12A and the second cell selection transistor Q12B are turned on, and the upper electrode of the selected ferroelectric capacitor CF12 is connected to the first set line SET1 via the first selection transistor Q12A. At the same time, the lower electrode of the selected ferroelectric capacitor CF12 is connected to the first reset line RST1 via the second cell selection transistor Q12B. Further, the first cell selection transistors Q11A, Q13A, Q14A and the second cell selection transistors Q11B, Q13B, Q14B connected in series with the ferroelectric capacitors CF11, CF13, CF14 of the unselected memory cells are turned off. Put it in a state.
[0103]
According to the first or second embodiment, a slight voltage is also applied between the upper electrode and the lower electrode of the unselected ferroelectric capacitors CF11, CF13, CF14, but the third embodiment. According to the above, since the unselected ferroelectric capacitors CF11, CF13, CF14 are surely disconnected from the first set line SET1 and the first reset line RST1, the unselected ferroelectric capacitors CF11, CF13, CF14 are separated. No voltage is applied between the upper and lower electrodes.
[0104]
(Fourth embodiment)
Hereinafter, a semiconductor memory device and a driving method thereof according to the fourth embodiment of the present invention will be described with reference to FIG.
[0105]
FIG. 5 shows an equivalent circuit of the first memory cell block constituting the semiconductor memory device according to the fourth embodiment. In the second memory cell block, an equivalent circuit similar to that of the first memory cell block is provided, but the illustration is omitted.
[0106]
As shown in FIG. 5, in the first memory cell block, a plurality of ferroelectric capacitors CF11, CF12, CF13, and CF14 that store data by polarization deviation of the ferroelectric film, and the plurality of ferroelectric capacitors. A plurality of memory cells including a plurality of cell selection transistors Q11, Q12, Q13, and Q14 connected in series to each of the body capacitors CF11, CF12, CF13, and CF14 are connected in parallel to each other.
[0107]
The first common node N11 is connected to a first set line SET1 to which a read voltage is applied via a first block selection transistor transistor Q10, and the gate electrode of the first block selection transistor Q10 is a block. It is connected to the selection line BS. The second common node N12 is connected to the first reset line RST1 through the first write transistor Q15, and is connected to the gate electrode of the first read transistor Q16 as a capacitive load. The gate electrode of the first write transistor Q15 is connected to the first write transistor control line RE1, the drain region of the first read transistor Q16 is connected to the bit line BL, and the source region of the first read transistor Q16. Are connected to the first reset line RST1.
[0108]
Further, word lines WL11, WL12, WL13, and WL14 are connected to the gate electrodes of the cell selection transistors Q11, Q12, Q13, and Q14, respectively.
[0109]
Also in the fourth embodiment, the capacitance values of the plurality of ferroelectric capacitors CF11, CF12, CF13, and CF14 are equal to each other, and the sizes of the plurality of cell selection transistors Q11, Q12, Q13, and Q14 are equal to each other.
[0110]
As a feature of the fourth embodiment, a reset transistor Q17 is connected between the first common node N11 and the second common node N12, and the gate electrode of the reset transistor Q17 is connected to the reset control line SE. ing.
[0111]
In the fourth embodiment, after the data write operation and read operation, a high signal is applied to the reset control line SE to turn on the reset transistor Q17.
[0112]
Therefore, the potential difference generated between the upper electrode and the lower electrode of the ferroelectric capacitor that has completed the data writing operation and the data reading operation can be reliably reduced to zero in a short time.
[0113]
In the first to fourth embodiments, the first read transistor Q16 is used as the capacitive load, and the read voltage is set to the capacitance value of the ferroelectric capacitor and the gate capacitance value of the first read transistor Q16. The divided voltage is applied to the gate electrode of the first read transistor Q16, and the difference in current flowing between the drain region and the source region of the first read transistor Q16 is determined according to the potential of the gate electrode. By detecting, the data stored in the ferroelectric capacitor is read out, but another capacitive load may be used instead of the first read transistor Q16. For example, a voltage value when a wiring is used instead of the first read transistor Q16 and a voltage obtained by dividing the read voltage based on the capacitance value of the ferroelectric capacitor and the wiring capacitance value of the wiring is applied to the wiring. May be detected by a sense amplifier.
[0114]
【The invention's effect】
According to the method for driving a semiconductor memory device of the present invention, the read voltage is such that when the read voltage is removed, the polarization deviation of the ferroelectric film returns to the deviation before reading the multivalued data. Since the size is set, when the data stored in the ferroelectric capacitor is read, the read data is not destroyed, so there is no need to perform a data rewrite operation. For this reason, since the polarization fatigue deterioration hardly occurs in the ferroelectric film of the ferroelectric capacitor, the retention characteristic of the semiconductor memory device is greatly improved.
[0115]
In addition, when reading data by transferring charge from the data read ferroelectric capacitor to the capacitive load, it is separated from the capacitive load by the cell selection transistor that is not selected in the ferroelectric capacitor off state. Since the ferroelectric capacitors that are not used do not act as parasitic capacitances, the voltage applied to the capacitive load at the time of data reading does not vary.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of first and second memory cell blocks constituting a semiconductor memory device according to a first embodiment.
FIG. 2 is a diagram illustrating the behavior of charge and voltage during a read operation of the semiconductor memory device according to the first embodiment.
FIG. 3 is an equivalent circuit diagram of a first memory cell block constituting a semiconductor memory device according to a second embodiment.
FIG. 4 is an equivalent circuit diagram of a first memory cell block constituting a semiconductor memory device according to a third embodiment.
FIG. 5 is an equivalent circuit diagram of a first memory cell block constituting a semiconductor memory device according to a fourth embodiment.
FIG. 6 is an equivalent circuit diagram of a memory cell constituting the semiconductor memory device according to the first conventional example.
FIG. 7 is an equivalent circuit diagram of a memory cell constituting a semiconductor memory device according to a second conventional example.
FIG. 8 is a diagram for explaining the behavior of charge and voltage during a read operation of a semiconductor memory device according to a second conventional example.
FIG. 9 is an equivalent circuit diagram of a semiconductor memory device as a premise of the present invention.
[Explanation of symbols]
CF11, CF12, CF13, CF14 Ferroelectric capacitor of the first memory cell block
CF21, CF22, CF23, CF24 Ferroelectric capacitor of second memory cell block
Q11, Q12, Q13, Q14 Cell selection transistor of the first memory cell block
Q21, Q22, Q23, Q24 Cell selection transistor of second memory cell block
Q11A, Q12A, Q13A, Q14A First cell selection transistor of the first memory cell block
Q11B, Q12B, Q13B, Q14B Second cell selection transistor of the first memory cell block
Q10 First block selection transistor
Q20 Second block selection transistor
Q15 First write transistor
Q25 Second write transistor
Q16 First read transistor
Q26 Second read transistor
Q17 Reset transistor
WL11, WL12, WL13, WL14 Word line of the first memory cell block
WL21, WL22, WL23, WL24 Word line of second memory cell block
WL11A, WL12A, WL13A, WL14A First word line of the first memory cell block
WL11B, WL12B, WL13B, WL14B Second word line of the first memory cell block
N11 First common node of first memory cell block
N12 Second common node of first memory cell block
N21 First common node of second memory cell block
N22 Second common node of second memory cell block
BS block selection line
BL bit line
SET1 First set line
SET2 Second set line
RST1 First reset line
RST2 Second reset line
RE1 First write transistor control line
RE2 Second write transistor control line
SE reset control line

Claims (4)

A memory cell block in which a plurality of memory cells having cell selection transistors connected in series with a ferroelectric capacitor for storing data by deviation of polarization of a ferroelectric film are connected in parallel, and the memory cell block A method for driving a semiconductor memory device, comprising: a common node connected to the capacitor; and a capacitive load connected to the common node and detecting polarization deviation of a ferroelectric film of the ferroelectric capacitor,
One data read
A first step of connecting one electrode of a ferroelectric capacitor of a memory cell selected by the cell selection transistor to the capacitive load via the common node;
After the first step , a read voltage is applied to a set line connected to the other electrode of the ferroelectric capacitor, and the read voltage includes a capacitance value of the ferroelectric capacitor and a capacitance value of the capacitive load. A second step of detecting a voltage applied to the capacitive load divided based on the ratio to detect a polarization deviation of the ferroelectric film and reading the data ;
The read voltage applied in the second step is such that the voltage applied between the one electrode and the other electrode of the ferroelectric capacitor is less than or equal to the coercive voltage of the ferroelectric capacitor. Well,
A third step of removing the read voltage after the second step;
The polarization deviation after the third step is the same as the polarization deviation before the second step,
After the third step, there is provided a fourth step of zeroing a potential difference between the upper electrode and the lower electrode of the ferroelectric capacitor generated in the third step. A method for driving a semiconductor memory device. Method for driving a semiconductor memory device according to claim 1 before Symbol cell selection transistor, characterized in that arranged before Symbol Common node side. The capacitive load driving method of the semiconductor memory device according to claim 1, wherein the gate electrode is connected to the field effect transistor before Symbol Common node. In the field effect transistor, a voltage obtained by dividing the read voltage based on a ratio between a capacitance value of the ferroelectric capacitor and a gate capacitance value of the field effect transistor is applied to a gate electrode of the field effect transistor. 4. The deviation of polarization of the ferroelectric film is detected by detecting a current flowing between a drain region and a source region of the field effect transistor. A method for driving a semiconductor memory device.

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