JP3620702B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a method of forming a capacitor in a trench hole in a semiconductor substrate and a capacitor structure.
[0002]
[Prior art]
Conventionally, in a semiconductor device, a capacitor using a deep trench hole used in a DRAM or the like has been formed by forming a hole that has been reduced to the limit of lithography (lithography), and by deeply digging this hole, a capacitor having a high capacity has been formed. . FIG. 13 shows a semiconductor substrate on which a conventional capacitor is formed.
The semiconductor substrate is formed with a transistor or the like constituting the semiconductor device. In this figure, the transistor portion is not shown, and only the capacitor portion is shown (FIG. 13B). The semiconductor substrate 100 is made of, for example, a silicon semiconductor. A first insulating film and a second insulating film are stacked on the main surface of the semiconductor substrate 100. The first insulating film is made of a silicon nitride film (SiN) 101, and the second insulating film is made of a TEOS film 102. The TEOS film is an insulating film made of silicon oxide obtained by a chemical vapor deposition method using tetraethoxysilane gas. A trench hole 103 is formed on the main surface of the semiconductor substrate 100, and a dielectric film 104 is formed on the side surface thereof. A semiconductor layer 105 such as polysilicon is formed on the TEOS film 102 and inside the trench hole. Here, a capacitor is formed in which the dielectric film 104 is a dielectric, and the semiconductor substrate 100 and the semiconductor layer 105 are first and second electrodes. For example, a DRAM memory element is formed by combining this capacitor with a MOS transistor formed on a semiconductor substrate.
[0003]
Next, a method for forming this capacitor will be described.
First, a 5 nm-thickness silicon oxide film (SiO 2) is used as a base material for the mask material on the semiconductor substrate 100. ₂ ) (Not shown) is formed, a 220 nm thick silicon nitride film 101 is formed thereon, and a 700 nm thick TEOS film 102 is laminated thereon. And these laminated bodies are used as a mask material. A photoresist 106 is applied on the TEOS film 102 with respect to the base material, and a trench hole pattern is formed on the photoresist 106 by well-known lithography (FIG. 12A). Next, the TEOS film 102, the silicon nitride film 101, and the silicon oxide film are etched using the photoresist 106 as an etching mask. Thereafter, the photoresist 106 is peeled off and used as an etching mask for the silicon semiconductor substrate 100 (FIG. 12B). Therefore, anisotropic etching such as RIE (Reactive Ion Etching) performed in the subsequent semiconductor substrate etching is performed by performing etching under etching conditions that can take a selectivity with respect to TEOS using the TEOS film 102 as a mask. Deep trench holes can be formed (FIG. 13A). By growing a thin film of silicon nitride or silicon oxide as the dielectric film 104 in the trench thus formed, and further depositing a polysilicon film 105 as a conductive material in the trench hole 103, A capacitor is formed (FIG. 13B).
[0004]
[Problems to be solved by the invention]
However, when the trench hole formed in the semiconductor substrate in this way is used as a capacitor, the capacitance capacity is determined by the surface area of the portion corresponding to the inner wall surface of the trench. Therefore, in order to secure a large capacity of the capacitor, it is necessary to increase the depth of the trench hole or increase the width of the trench hole. On the other hand, with the miniaturization of semiconductor elements, there has been a limit to ensure a large trench width. For this reason, it is inevitable to deepen the trench hole in order to ensure the capacitance capacity.
Further, if the trench hole is to be etched deeply, there is a limit to increasing the thickness of the TEOS film, which is a mask material. Therefore, the TEOS film having a limited thickness is not etched as much as possible, and the trench hole of the semiconductor substrate is used. Therefore, it is necessary to etch the semiconductor substrate under such etching conditions that the etching rate of silicon with respect to the etching rate of the TEOS film can be made extremely high. However, it is not easy to find a condition for obtaining a desired etching shape while maintaining a high selection ratio of silicon to the TEOS film, and the etching depth is inevitably limited.
The present invention has been made under such circumstances, and provides a method for manufacturing a semiconductor device in which the capacitance of a capacitor formed in a trench hole is increased using a conventional etching technique.
[0005]
[Means for Solving the Problems]
The present invention includes a pillar formed of a conductive layer formed on a bottom surface of a trench hole of a semiconductor substrate and formed from the bottom surface toward an opening end, an insulating film formed on a trench hole side wall and a pillar surface, and at least the trench. And a capacitor having a semiconductor substrate and pillar as a first electrode, an insulating film as a dielectric, and a conductive film as a second electrode. Since it is possible to secure a large side wall area in the trench hole using a pillar, it is easy to form a large-capacity capacitor.
In addition, after forming an insulating film collar along the inner wall of the trench hole, polysilicon is deposited inside the collar, and then the collar is removed by selective etching, thereby forming a pillar in the trench hole. It is said. According to this method, the pillars can be formed in a self-aligning manner. Therefore, a pillar can be easily formed without performing an extra lithography process.
[0007]
The method of manufacturing a semiconductor device according to the present invention includes a step of forming a first trench hole having a predetermined opening diameter on a main surface of a semiconductor substrate, a step of forming an insulating film on a side wall of the first trench hole, Filling a conductive layer into a first trench hole in which an insulating film is formed on the main surface of the semiconductor substrate and on the side wall; and removing the conductive layer on the main surface of the semiconductor substrate by etching to remove the conductive layer from the first trench hole. The step of leaving only inside one trench hole and the insulating film formed on the side wall of the first trench hole are removed by etching to form the bottom surface of the first trench hole from the bottom surface toward the opening end. Forming a first pillar composed of the conductive layer, oxidizing the first pillar and a sidewall of the first trench hole facing the first pillar, and the first trench hole. Etching the bottom of Forming a second trench hole continuous with the first trench hole under the first trench hole and forming the second trench hole by oxidation on the side wall of the first trench hole under the first pillar. The first feature is that a step of forming a second pillar continuous with the first pillar by performing anisotropic etching using the oxide film as a mask is provided.
[0008]
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the step of forming a first trench hole having a predetermined opening diameter on a main surface of a semiconductor substrate, and the step of forming an insulating film on a sidewall of the first trench hole. A step of filling a conductive layer in the first trench hole in which an insulating film is formed on the main surface of the semiconductor substrate and on the side wall; and etching the conductive layer on the main surface of the semiconductor substrate to remove the conductive layer. The step of leaving only the inside of the first trench hole and the insulating film formed on the side wall of the first trench hole are removed by etching so that the bottom surface of the first trench hole extends from the bottom surface toward the opening end. Forming a first pillar composed of the conductive layer formed, oxidizing the surface of the first pillar and the side wall of the first trench hole facing the first pillar, and the first The bottom of the trench hole A second trench hole is formed under the first trench hole to be continuous with the first trench hole, and the second pillar is continuous with the first pillar under the first pillar. Forming the second pillar, and anisotropically etching the first and second pillars using an oxide film formed by oxidation on the surface of the first pillar as a mask. A second feature is that it includes a step of forming a second trench hole in the first and second pillars.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment will be described with reference to FIGS.
1 to 3 are sectional views of a semiconductor substrate for explaining a capacitor forming process. A semiconductor element such as a transistor constituting a semiconductor device or a circuit element such as a capacitor is formed on a semiconductor substrate. In this figure, the transistor part is omitted and the capacitor part is shown (FIG. 1A). ). The semiconductor substrate 10 is made of, for example, a silicon semiconductor. The main surface of the semiconductor substrate 10 is a silicon oxide film (SiO ₂ ) The first insulating film and the second insulating film are stacked via 8. The first insulating film is made of a silicon nitride film (SiN) 1, and the second insulating film is made of a TEOS film 2. A trench hole 3 is formed in the main surface of the semiconductor substrate 10. A polysilicon pillar 6 is formed in the trench hole 3 from the bottom surface toward the opening end. A dielectric film 4 is formed on the bottom and side surfaces of the trench hole 3 and the surface of the pillar 6. A conductive layer 5 such as polysilicon is formed on the TEOS film 2 and in the trench hole. Here, a capacitor is formed in which the dielectric film 4 is a dielectric, the semiconductor substrate 10 and the pillar 6 are first electrodes, and the conductive layer 5 is a second electrode. For example, a DRAM memory element is formed by combining this capacitor with a MOS transistor on a semiconductor substrate.
[0010]
Next, the capacitor forming method of this embodiment will be described.
First, a 5 nm-thickness silicon oxide film (SiO 2) is used as a base material for the mask material on the semiconductor substrate 10. ₂ ) 8 is formed, a silicon nitride film 1 having a thickness of 200 nm is formed thereon, and a TEOS film 2 having a thickness of 700 nm is laminated thereon. And these laminated bodies are used as a mask material. A photoresist (not shown) is applied to the base material on the TEOS film 2, and a trench hole pattern is formed in the photoresist by well-known lithography. Next, the TEOS film 2, the silicon nitride film 1, and the silicon oxide film 8 are etched using this photoresist as an etching mask. Thereafter, the photoresist is peeled off and used as an etching mask for the silicon semiconductor substrate 10. Therefore, anisotropic etching such as RIE performed in the subsequent semiconductor substrate etching is performed by using the TEOS film 2 as a mask and performing etching under etching conditions having a selection ratio with respect to TEOS. A trench hole 3 is formed (FIG. 1B). For anisotropic etching for forming the trench hole 3, a magnetron RIE apparatus is used, and HBr, O as etching gases. ₂ , NF ₃ And processing at a pressure of 100 mTorr. The trench hole 3 has an elliptical shape in which the hole cross section has a minor axis = 0.2 μm and a major axis = 0.34 μm. FIG. 3B is a plan view of the semiconductor substrate. The trench hole 3 has an elliptical cross-sectional shape, and the pillar 6 has an elliptical cross-sectional shape corresponding to this. The distance between the pillar 6 and the side wall of the trench hole 3 is about 0.07 μm.
[0011]
A BSG (Boron Silicate Glass) film 7 is deposited to a thickness of about 20 nm in the trench hole 3 thus formed (FIG. 1C). Thereafter, the entire BSG film 7 is etched back by anisotropic etching such as RIE (Reactive Ion Etching) to expose the silicon surface of the semiconductor substrate 10 on the bottom surface of the trench hole 3 and the color of the BSG film 7 on the side wall of the trench hole 3. 7 '(hereinafter referred to as a collar BSG film) is formed (FIG. 2A). Next, a polysilicon layer 5 having a film thickness of about 300 nm is deposited by a low pressure CVD (Chemical Vapor Deposition) method and buried in the trench hole 3 (FIG. 2B), and then lower than the surface of the semiconductor substrate 10. The polysilicon layer 5 is etched back to the position to form the pillar 6 (FIG. 2C). For the etch back of the polysilicon layer 5, a down-flow type dry etching apparatus is used, and the surface of the polysilicon layer is controlled to a height that is 50 nm lower than the silicon interface of the semiconductor substrate. Thereafter, the color BSG film 7 'is etched with high selectivity to TEOS, silicon nitride, silicon oxide, and silicon. The color BSG film can be etched using only the BSG while maintaining a high selectivity with respect to TEOS by using an etching method using vapor phase HF. By this etching, conductive pillars 6 are formed in the trench holes 3 (FIG. 3A).
[0012]
Next, a silicon nitride film which is a capacitor insulating film (dielectric) 4 is formed on the surface of the polysilicon pillar 6 and the sidewall of the trench hole 3, and a polysilicon film 9 serving as a counter electrode of the capacitor is deposited. A capacitor is formed. This capacitor has a configuration in which the semiconductor substrate 10 and the pillar 6 are used as a first electrode, the polysilicon film 9 as a counter electrode is used as a second electrode, and the capacitor insulating film 4 is used as a dielectric. In addition, the surface area about 1.7 times that of the conventional trench structure (FIG. 13B) can be obtained, and the capacitance of the formed capacitor is about 1.7 times proportional to the surface area. Capacitance capacity is obtained.
[0013]
Next, a second embodiment will be described with reference to FIGS.
4 to 6 are sectional views of the semiconductor substrate for explaining the capacitor forming process. A semiconductor element such as a transistor or a circuit element such as a capacitor constituting a semiconductor device is formed on the semiconductor substrate. In this figure, the transistor part is omitted and the capacitor part is shown (FIG. 6B). ). The semiconductor substrate 20 is made of, for example, a silicon semiconductor. On the main surface of the semiconductor substrate 20, a silicon oxide film (SiO ₂ ) (Not shown), the first insulating film and the second insulating film are stacked. The first insulating film is made of a silicon nitride film (SiN) 21, and the second insulating film is made of a TEOS film 22. An upper trench hole 23 and a lower trench hole 24 are formed in the main surface of the semiconductor substrate 20. Inside the trench holes 23, 24, polysilicon pillars are formed from the bottom surface of the trench hole 24 toward the opening end of the trench hole 23. A conductive pillar 26 formed from the semiconductor substrate 20 is disposed in the trench hole 24, and an insulating pillar 26 ′ made of a silicon oxide film and connected to the pillar 26 is disposed in the trench hole 23. A silicon oxide film 28 is formed on the side wall of the trench hole 23.
[0014]
A capacitor (not shown) is formed in this trench structure. That is, after removing the insulating pillar 26 ′, a capacitor insulating film (dielectric) of a silicon oxide film is formed on the bottom and side surfaces of the trench hole 24 and the surface of the pillar 26, and polysilicon is formed inside the trench holes 23 and 24. A capacitor is formed by forming a conductive layer or the like. The capacitor is configured such that the capacitor insulating film is a dielectric, the semiconductor substrate 20 and the pillar 26 are first electrodes, and the conductive layer is a second electrode. For example, a DRAM memory element is formed by combining this capacitor with a MOS transistor formed on a semiconductor substrate.
[0015]
Next, the capacitor forming method of this embodiment will be described.
First, a 5 nm-thickness silicon oxide film (SiO 2) is used as a base material for the mask material on the semiconductor substrate 20. ₂ (Not shown), a silicon nitride film 21 having a thickness of 200 nm is formed thereon, and a TEOS film 22 having a thickness of 700 nm is laminated thereon. And these laminated bodies are used as a mask material. A photoresist (not shown) is applied to the base material on the TEOS film 22, and a trench hole pattern is formed in the photoresist by well-known lithography. Next, the TEOS film 22, the silicon nitride film 21, and the silicon oxide film are etched using this photoresist as an etching mask. Thereafter, the photoresist is peeled off and used as an etching mask for the silicon semiconductor substrate 20. Therefore, anisotropic etching such as RIE performed in the subsequent semiconductor substrate etching is performed using the TEOS film 22 as a mask and etching is performed under an etching condition with a selection ratio with respect to TEOS. A trench hole 23 is formed (FIG. 4A). For anisotropic etching for forming the trench hole 23, a magnetron RIE apparatus is used, and HBr, O as etching gases. ₂ , NF ₃ And processing at a pressure of 100 mTorr.
[0016]
The trench hole has an elliptical cross section with a minor axis = 0.2 μm and a major axis = 0.34 μm. A BSG film 27 is deposited to a thickness of about 20 nm in the trench hole 23 thus formed (FIG. 4B). Thereafter, the entire surface of the BSG film 27 is etched back by anisotropic etching such as RIE to expose the silicon surface of the semiconductor substrate 20 on the bottom surface of the trench hole 23 and the color of the BSG film 7 on the side wall of the trench hole 23 (hereinafter referred to as color BSG). 7 'is formed (refer to FIG. 4 (c)). Next, a polysilicon layer 25 having a thickness of about 300 nm is deposited by low-pressure CVD, and this is buried in the trench hole 23 (FIG. 5A), and then the polysilicon layer is lowered to a position lower than the surface of the semiconductor substrate 20. 25 is etched back to form pillars 25 '(FIG. 5B). A down-flow type dry etching apparatus is used to etch back the polysilicon layer 25, and the surface of the etched back polysilicon layer is controlled to a height that is 50 nm lower than the silicon interface of the semiconductor substrate 20. Thereafter, the color BSG film 27 'is etched with high selectivity to TEOS, silicon nitride, silicon oxide, and silicon. The color BSG film can be etched using only the BSG while maintaining a high selectivity with respect to TEOS by using an etching method using vapor phase HF.
[0017]
By this etching, an elliptical conductive pillar 25 ′ having a height of 1.8 μm and a minor axis of 0.06 μm is formed in the trench hole 23 (FIG. 5C).
Next, the entire polysilicon pillar 25 ′ is oxidized by a thermal oxidation process to form an insulating pillar 26 ′ and a silicon oxide film 28 on the bottom and side walls of the trench hole 23 (FIG. 6). (A)). Thereafter, first, the conditions under which the silicon oxide film is etched (SiO 2 ₂ = Equivalent to 40 nm etching), and then trench holes are etched under conditions that allow highly selective etching of silicon on the semiconductor substrate with respect to TEOS and silicon oxide films. SiO ₂ = For etching equivalent to 40 nm, a magnetron RIE apparatus is used, and HBr, NF ₃ Etching is performed using gas at a pressure of 100 mTorr for 2 minutes. As conditions for etching silicon with high selectivity to TEOS and silicon oxide films, a magnetron RIE apparatus is used, and etching gases such as HBr, O ₂ , NF ₃ Etching was performed at a pressure of 100 mTorr for 6 minutes.
[0018]
As a result, a trench hole 24 having a depth of 8 μm from the silicon interface of the semiconductor substrate (the depth of the trench hole 24 is 6 μm) and a pillar 26 are formed in the trench hole 24.
In the trench holes 23 and 24 thus formed, a silicon nitride film having a film thickness of 8 nm, which is a capacitor insulating film (dielectric), is formed on the pillar trench, and then the trench holes 23 and 24 are formed. By embedding a polysilicon film, a capacitor having a surface area about 1.5 times that of the conventional trench structure can be obtained.
[0019]
Next, a third embodiment will be described with reference to FIGS.
This embodiment is characterized in that only the surface is oxidized while the upper pillar of the second embodiment is entirely oxidized.
7 and 8 are cross-sectional views of the semiconductor substrate for explaining the capacitor forming step. A semiconductor element such as a transistor and a circuit element such as a capacitor which form a semiconductor device are formed on the semiconductor substrate. In this figure, the transistor portion is omitted and the capacitor portion is shown (FIG. 8B). )). The semiconductor substrate 30 is made of, for example, a silicon semiconductor. On the main surface of the semiconductor substrate 30, a silicon oxide film (SiO ₂ ) (Not shown), the first insulating film and the second insulating film are stacked. The first insulating film is composed of a silicon nitride film (SiN) 31, and the second insulating film is composed of a TEOS film 32. An upper trench hole 33 and a lower trench hole 34 are formed on the main surface of the semiconductor substrate 30. In the trench holes 33 and 34, polysilicon pillars are formed from the bottom surface of the trench hole 34 toward the opening end of the trench hole 33. A conductive pillar 36 formed from the semiconductor substrate 30 is disposed in the trench hole 34, and an insulating pillar 37 made of a silicon oxide film and connected to the pillar 36 is disposed in the trench hole 33. A silicon oxide film 38 is formed on the sidewall of the trench hole 33. A trench hole 39 is formed in the pillars 36 and 37.
[0020]
A capacitor (not shown) is formed in this trench structure. That is, after the insulating pillar 37 is removed, a capacitor insulating film (dielectric) made of a silicon oxide film is formed on the bottom and side surfaces of the trench holes 34 and 39 and on the surface of the pillar 36. A capacitor is formed by forming a conductive layer such as silicon. This capacitor is configured so that the capacitor insulating film is a dielectric, the semiconductor substrate 30 and the pillar 36 are first electrodes, and the conductive layer embedded in the trench holes 33 and 34 is a second electrode. For example, a DRAM memory element is formed by combining this capacitor with a MOS transistor formed on a semiconductor substrate.
[0021]
Next, the capacitor forming method of this embodiment will be described.
Since the process up to the step of forming the pillar 33 shown in FIG. 7A is the same as that of the second embodiment, the description up to that point (see FIGS. 4 and 5C) is omitted. That is, in the process up to FIG. 7A, the elliptical pillar 35 having a height of 1.8 μm and a minor axis of 0.15 μm is formed in the trench hole 33 having a depth of 2 μm. The trench hole 33 has an elliptical shape in which the hole cross section has a minor axis = 0.2 μm and a major axis = 0.34 μm.
Next, the sidewall and bottom surface of the trench hole 33 and the surface of the pillar 35 are oxidized by a thermal oxidation process, and the silicon oxide film 38 having a thickness of 20 nm on the sidewall and bottom surface of the trench hole 33 and the surface of the pillar 35 having a thickness of 20 nm. A silicon oxide film 37 is formed (FIG. 7B). Thereafter, the conditions under which the silicon oxide film is first etched (SiO 2 ₂ = Equivalent to 25 nm etching) (FIG. 8A), and then the trench hole 35 is etched under the condition that the silicon of the semiconductor substrate can be etched with high selectivity with respect to TEOS and the silicon oxide film. As a result, a trench hole 34 having a depth of 8 μm from the silicon interface of the semiconductor substrate 30 is formed, and a trench hole 39 is also formed inside the pillars 36 and 37 (see FIG. 8B).
After a 6-nm-thick silicon nitride film, which is a capacitor insulating film (dielectric), is formed on the inner surfaces of the trench holes 33 and 34 and the inner walls of the pillar 36 and 37 surface trench holes 39 thus formed. By embedding a polysilicon film in the trench holes 23 and 24, it is possible to obtain a capacitor having a surface area about 2.1 times that in the case where the conventional trench structure is used.
[0022]
Next, a fourth embodiment will be described with reference to FIGS.
In the first to third embodiments, the trench structure capacitor formed in the semiconductor substrate has been described. For example, a semiconductor device using the capacitor includes a DRAM. The DRAM uses a one-transistor type cell as shown in FIG. 9 in which the number of components per memory cell is small for high bit integration, and only a MOS capacitor for storing charge and a MOS transistor for transferring the charge are used. It is composed of
[0023]
FIG. 9 is a circuit diagram of a DRAM memory, FIG. 10 is a sectional view of a semiconductor substrate on which a DRAM memory element is formed, and FIG. 11 is a schematic plan view of the semiconductor substrate partially showing a memory element pattern. A transistor (Tr) and a capacitor (C) for one memory cell are formed on a semiconductor substrate 40, for example, a p-type silicon semiconductor substrate. A trench hole 47 is formed in the main surface of the semiconductor substrate 40. In the trench hole 47, a polysilicon pillar 41 is formed from the bottom surface toward the opening end. A dielectric film 42 of a silicon nitride film is formed on the bottom and side surfaces of the trench hole 47 and the surface of the pillar 41. An n-type impurity diffusion region 44 is formed in the semiconductor substrate in the vicinity of the side wall and the bottom surface excluding the upper portion of the trench hole. In order to prevent a short circuit with the substrate except for a part of the opening end of the upper side wall of the trench hole 47, a silicon oxide film (SiO ₂ ) 45 is formed. Polysilicon films 43, 43 'and 43 "are formed inside the trench hole 47. In such a trench structure, the pillar 41 and the n-type impurity diffusion region 44 serve as the first electrode, and the dielectric film A capacitor (C) having the dielectric 42 and the polysilicon films 43, 43 'and 43 "as the second electrode is formed.
[0024]
On the other hand, a MOS transistor (Tr) is formed on the main surface of the semiconductor substrate 40. That is, the n-type impurity diffusion regions 46, 46 that are source / drain regions are formed close to the trench hole 47. Further, a gate 49 made of a polysilicon film or the like is formed between the source / drain regions 46 and 46 via a gate oxide film 48. One of the source / drain regions is electrically connected to the second electrode of the capacitor (C) (the first electrode is grounded). Such MOS transistors and capacitors constitute the memory cell shown in FIG.
As shown in FIG. 11, one memory cell 50 is repeatedly formed vertically and horizontally on a semiconductor substrate 40 to constitute a cell array. The n-type impurity diffusion region 44 of the memory cell 50 is joined to the n-type impurity diffusion region 44 ′ of the adjacent memory cell.
The capacitor of this embodiment has a larger surface area than the conventional one because the pillar is formed. Therefore, the capacitance is 1.7 times larger than the conventional one.
DRAMs must always maintain a certain capacitance value above a certain value regardless of the memory cell miniaturization in order to ensure refresh operation frequency, allowance for sensing operation, and reduce soft error rate due to alpha rays. There is. Since the capacitor of this embodiment has a larger capacity than the conventional one, it is optimal for use in a DRAM.
[0025]
In the above embodiment, the magnetron RIE apparatus is used as anisotropic etching for forming trench holes in the semiconductor substrate. However, an inductively coupled RIE apparatus, an ECR-RIE apparatus, a simple parallel plate RIE apparatus, or the like is used. Various etching apparatuses can be used, and the present invention is not limited to the magnetron RIE apparatus.
In the above embodiment, polysilicon is used as the pillar. However, various conductive materials such as semiconductor materials such as amorphous silicon, silicon carbide (SiC), silicide, carbon, and the like can be used depending on the purpose. it can.
In the above embodiment, the combination of BSG is used as the collar material for the trench hole sidewalls and TEOS is used as the hard mask material for the trench holes. However, other suitable combinations of materials may be used. For example, instead of BSG, BPSG (Boron-Doped Phospho-Silicate Glass), PSG (Phospho-Silicate Glass), SOG (Spin On Glass) can be used as a material that can obtain a selection ratio with respect to TEOS in vapor phase HF treatment. ) Etc. can also be used.
Further, for example, as a hard mask material, a material such as a thermal oxide film or a SiN film can be used instead of TEOS.
[0026]
In the above embodiment, TEOS / SiN / SiO is used as a hard mask material for trench formation. ₂ However, various materials, film configurations, film thicknesses, and the like can be arbitrarily selected according to the purpose. For example, a TEOS single-layer film or a single-layer film of a thermal oxide film can be used.
In the above embodiment, TEOS is used as a hard mask material for trench etching. However, it is possible to obtain a selection ratio with respect to BSG such as a thermal oxide film. ₂ System materials can also be used, and other materials such as SiN films can also be used.
Further, conditions such as the diameter of the pillar, the amount of oxidation when oxidizing the pillar, and the depth of the trench hole in the above embodiment can be arbitrarily selected according to the purpose.
In the above embodiment, a vertical trench hole is formed. However, a trench hole that is narrow in the deep part, a trench hole that has a large diameter in the deep part, a trench hole whose thickness is changed in the middle, and the like. Any shape can be selected.
Moreover, in the said Example, although the pillar formation process was used as a technique for capacitor formation, it is applicable also for the objectives other than capacitor formation.
[0027]
【The invention's effect】
With the above configuration, the present invention can increase the surface area of the capacitor by using the pillar structure as a trench capacitor, so that a large capacitance capacity can be secured without increasing the outer diameter of the capacitor. Further, it is possible to form a smaller-diameter pillar in the trench hole in a self-aligned manner, and it is possible to easily form a structure that is lower than the limit of the lithography process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment and a manufacturing process thereof.
FIG. 2 is a sectional view of a manufacturing process of the semiconductor device according to the first embodiment.
3A and 3B are a manufacturing process cross-sectional view and a plan view of the semiconductor device of the first embodiment.
FIG. 4 is a cross-sectional view of a manufacturing process of a semiconductor device according to a second embodiment.
FIG. 5 is a sectional view of a manufacturing process of the semiconductor device according to the second embodiment.
FIG. 6 is a cross-sectional view of a manufacturing process of the semiconductor device of the second embodiment.
7 is a cross-sectional view of a manufacturing process of a semiconductor device according to a third embodiment; FIG.
FIG. 8 is a cross-sectional view of a manufacturing process of a semiconductor device according to a third embodiment.
FIG. 9 is a circuit diagram of a DRAM memory cell according to a fourth embodiment.
FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment.
FIG. 11 is a plan view of a semiconductor device according to a fourth embodiment.
FIG. 12 is a cross-sectional view of a manufacturing process of a conventional device.
FIG. 13 is a cross-sectional view of a manufacturing process of a conventional device.
[Explanation of symbols]
1, 21, 31, 101... Silicon nitride film,
2, 22, 32, 102 ... TEOS film,
3, 23, 24, 33, 34, 39, 47, 103 ... trench holes,
4, 42, 104 ... capacitor insulating film,
5, 25, 105 ... polysilicon layer,
6, 25 ', 26', 35, 36, 41 ... pillar,
7, 27 ... BSG film, 7 ', 27' ... Color BSG film,
8, 28, 38, 45 ... silicon oxide film,
9, 43, 43 ', 43 ", 105 ... polysilicon film,
10, 20, 30, 40, 100 ... semiconductor substrate,
37 ... Silicon oxide film (pillar),
44, 44 '... n-type impurity diffusion region,
46: Source / drain region (n-type impurity diffusion region),
48 ... gate oxide film, 49 ... gate, 50 ... memory cell.

Claims (2)

Forming a first trench hole having a predetermined opening diameter on the main surface of the semiconductor substrate; forming an insulating film on the side wall of the first trench hole; insulating on the main surface of the semiconductor substrate and the side wall; Filling a conductive layer inside the first trench hole in which the film is formed, etching removing the conductive layer on the main surface of the semiconductor substrate, and leaving the conductive layer only inside the first trench hole; The first insulating film formed on the side wall of the first trench hole is removed by etching, and the bottom surface of the first trench hole is formed from the conductive layer formed from the bottom surface toward the opening end. Forming the first pillar, oxidizing the first pillar and the side wall of the first trench hole facing the first pillar, etching the bottom surface of the first trench hole, and Under the trench hole A second trench hole formed continuously with the first trench hole is formed, and anisotropic etching is performed under the first pillar using an oxide film formed by oxidation on the side wall of the first trench hole as a mask. And a step of forming a second pillar that is continuous with the first pillar by performing the steps described above. Forming a first trench hole having a predetermined opening diameter on the main surface of the semiconductor substrate; forming an insulating film on the side wall of the first trench hole; insulating on the main surface of the semiconductor substrate and the side wall; Filling a conductive layer inside the first trench hole in which the film is formed, etching removing the conductive layer on the main surface of the semiconductor substrate, and leaving the conductive layer only inside the first trench hole; The first insulating film formed on the side wall of the first trench hole is removed by etching, and the bottom surface of the first trench hole is formed from the conductive layer formed from the bottom surface toward the opening end. Forming the first pillar, oxidizing the first pillar surface and the side wall of the first trench hole facing the first pillar, and etching the bottom surface of the first trench hole to form the first pillar. Under the trench hole Forming a second trench hole continuous with the first trench hole and forming a second pillar continuous with the first pillar under the first pillar; The first and second pillars are anisotropically etched using the oxide film formed by oxidation on the surface of the first pillar as a mask, so that the second pillar is formed in the first and second pillars. A method of manufacturing a semiconductor device, comprising a step of forming a trench hole.

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