JP3622705B2 - Manufacturing method of semiconductor device for display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal image display device having a color image display function, and more particularly to an active liquid crystal image display device.
[0002]
[Prior art]
With recent advances in microfabrication technology, liquid crystal material technology, high-density packaging technology, etc., a large number of television images and various image display devices are provided on a commercial basis with a 5 to 50 cm diagonal liquid crystal panel.
[0003]
These liquid crystal image display devices (liquid crystal panels) generally have a matrix organization of 200 to 1200 scanning lines and 200 to 1600 signal lines. Screening and high definition are progressing simultaneously.
[0004]
FIG. 7 shows a state of mounting on a liquid crystal panel, and a semiconductor integrated circuit for supplying a drive signal to an electrode terminal group 6 of a scanning line formed on one transparent insulating substrate, for example, a glass substrate 2, constituting the liquid crystal panel 1. A COG (Chip-On-Glass) system in which the chip 3 is connected using a conductive adhesive, or a copper foil terminal (not shown) made of, for example, a polyimide resin thin film and plated with gold or solder. An electrical signal is supplied to the image display unit by a mounting means such as a TCP (Tape-Carrier-Package) method in which the TCP film 4 is fixed to the electrode terminal group 5 of the signal line by pressing with an appropriate adhesive containing a conductive medium. The Here, for convenience, two mounting methods are shown at the same time, but in actuality, either method is appropriately selected.
[0005]
Reference numerals 7 and 8 denote wiring paths that connect between the image display unit located almost at the center of the liquid crystal panel 1 and the electrode terminals 5 and 6 of the signal lines and the scanning lines. There is no need to be composed of materials. Reference numeral 9 denotes a counter glass substrate or color filter which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the counter surface.
[0006]
FIG. 8 shows an equivalent circuit diagram of an active liquid crystal panel in which an insulated gate transistor 10 is arranged for each picture element as a switching element, 11 (8 in FIG. 3) is a scanning line, and 12 (7 in FIG. 7) is a signal line. , 13 are liquid crystal cells, and the liquid crystal cell 13 is electrically treated as a capacitive element. Elements drawn with solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and a counter electrode 14 common to all liquid crystal cells 13 drawn with dotted lines is formed on the other glass substrate 9. ing. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is attached to the gradation of the display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Is added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a storage capacitor line which is a common bus of the storage capacitor 15.
[0007]
FIG. 9 is a cross-sectional view of the main part of the image display portion of the liquid crystal panel. The two glass substrates 2 and 9 constituting the liquid crystal panel 1 are made of resin fibers, beads, or columnar spacer materials (not shown). A closed space formed with a predetermined distance of about μm and the gap (gap) sealed with a sealing material made of organic resin and a sealing material (both not shown) at the peripheral edge of the glass substrate 9. The closed space is filled with liquid crystal 17.
[0008]
In the case of realizing color display, an organic thin film layer having a thickness of about 1 to 2 μm and containing either or both of a dye and a pigment called a colored layer 18 is deposited on the closed space side of the glass substrate 9 to provide a color display function. In this case, the glass substrate 9 is also called a color filter (color filter abbreviation is CF). Depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either the upper surface of the color filter 9, the lower surface of the glass substrate 2, or both surfaces, and the liquid crystal panel 1 functions as an electro-optical element. Currently, most liquid crystal panels on the market use a TN (twisted nematic) type liquid crystal material, and two polarizing plates 19 are usually required. Although not shown, in the transmissive liquid crystal panel, a back light source is disposed as a light source, and white light is irradiated from below.
[0009]
The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed on the two glass substrates 2 and 9 in contact with the liquid crystal 17 is an alignment film for aligning liquid crystal molecules in a predetermined direction. 21 is a drain wiring (electrode) that connects the drain of the insulated gate transistor 10 and the transparent conductive pixel electrode 22, and is often formed simultaneously with the source line (signal line) 12. The semiconductor layer 23 is located between the source line 12 and the drain wiring 21 and will be described in detail later. The Cr thin film layer 24 having a thickness of about 0.1 μm formed at the boundary between the adjacent colored layers 18 on the color filter 9 prevents external light from entering the semiconductor layer 23, the scanning line 11, and the signal line 12. This is a technique for fixing light as a so-called black matrix (Black-Matrix abbreviation is BM).
[0010]
Along with the increase in productivity due to the increase in the size of the glass substrate, the production cost is reduced, and the parts and materials to be used are also reduced as the production volume increases. I'm following. The largest market at present is notebook PCs and desktop monitors, but with the rapid growth of mobile phones, small and medium-sized liquid crystal panels are also required for the display parts of mobile terminal devices that are expected to grow at the same time. In addition to these information terminal devices, digital home appliances and conventional car navigation applications, small and medium-sized markets are also expected to grow significantly.
[0011]
It is a general principle that the yield decreases as the screen size of a liquid crystal panel increases or the definition becomes higher, but a full-scale television using a liquid crystal panel with a diagonal of 50 cm or more due to a reduction in production cost. Product development has already been partly commercialized, and movements aimed at replacing CRT have also become active.
[0012]
Since it is a cumulative response type display device, the liquid crystal panel whose response time was difficult to be less than 16 mS is also developed for liquid crystal materials, new modes such as OCB (Optically self-compensated bend) liquid crystal, and further With the new development of the FS (field sequential) type liquid crystal panel that switches and displays the backside light source for each of R, G, and B in a time-sharing manner, the response time is less than a few milliseconds, and it is finally a CRT alternative liquid crystal The development of panels has gained momentum.
[0013]
Conventionally, most of the insulated gate transistors as switching elements are liquid crystal display devices using amorphous silicon as a semiconductor layer, and there are few liquid crystal display devices using high-temperature polysilicon or low-temperature polysilicon as a semiconductor layer. However, with the increase in display capacity, the mobility of electrons is small in amorphous silicon, so that it is difficult to maintain image quality in a liquid crystal display device of UXGA (1200 scanning lines, 1600 signal lines × 3) or more. The proportion of liquid crystal display devices that use is increasing rapidly. Further, in the FS (field sequential) type liquid crystal display device, the writing speed to each pixel is naturally required to be three times as high as the conventional one, and the need for low-temperature polysilicon is increasing from this viewpoint.
[0014]
Here, FIG. 10 shows a general unit pixel of a semiconductor device for a display device adopting an insulated gate transistor having a low-temperature polysilicon semiconductor layer, and FIG. 11 is a sectional view of a manufacturing process on AA ′ of FIG. The manufacturing method will be described.
[0015]
In the production of an active substrate using low-temperature polysilicon as a semiconductor layer, although not shown in the drawing, the thickness of the insulating substrate 2 having excellent transparency, heat resistance and chemical resistance is 0.5 to 1.1. A glass substrate of mm, for example, silicon oxide (SiO 2 having a thickness of about 0.3 μm as an alkali blocking layer on one main surface of a product name 1737 manufactured by Corning,₂) Or silicon nitride (SiNx) or a stack thereof. After that, an amorphous silicon layer having a film thickness of about 0.05 μm is deposited using a PCVD (Plasma Sea BD) apparatus, heated to 300 ° C. or more to reduce hydrogen content, and then an excimer laser To crystallize the amorphous silicon layer. Of course, there is almost no hydrogen content, for example, amorphous silicon, microcrystalline silicon or even polycrystalline or mixed crystals are formed by other means such as sputtering using silicon as a target, and then irradiated with an excimer laser. Also good. The process of accelerating the crystallization of silicon and growing crystal grains is the excimer laser irradiation process. Then, the so-called low temperature polysilicon crystallized as shown in FIG. 11A is selectively etched by a fine processing technique to leave the island shape 100 on the glass substrate 2.
[0016]
Next, SiO having a film thickness of about 0.1 μm that becomes the gate insulating layer 30 at a substrate heating temperature of about 400 to 500 ° C. (because it is called a low temperature) using a film forming apparatus such as CVD or TEOS-PCVD.₂As shown in FIG. 11B, the first metal layer serving as the gate electrode 11 is coated with a high heat resistance, for example, a MoW alloy having a film thickness of about 0.1 μm on the entire surface. Correspondingly, the low-temperature polysilicon 100 is exposed by selectively removing the gate metal layer MoW and the gate insulating layer SiO2.
[0017]
Subsequently, although not shown, phosphorus or boron as an impurity is implanted into the low-temperature polysilicon 100 by ion implantation or ion irradiation using the gate electrode 11 as a mask to form the source / drain 101, 102 of the insulated gate transistor.
[0018]
In an N-type insulated gate transistor obtained by injecting phosphorus as an impurity, a phenomenon in which electrons serving as carriers are deteriorated by a high electric field (hot carrier effect) is likely to occur. Therefore, the semiconductor layer (channel) below the gate electrode 11 and It is necessary to form a region with little or no impurities between the source / drain 101 and 102, and these techniques are also referred to as an LDD (Lightly-Doped-Drain) structure or an offset structure. For this purpose, for example, a small amount of phosphorus (at least 10% or less of the amount of source / drain implantation) is ion-implanted or ion-irradiated on the entire surface of the active substrate 2 in the state shown in FIG. A process of controlling the implantation of impurities using an appropriate mask material is necessary, such as removing about 1 to 3 μm on both sides, covering with a photosensitive resin, and injecting a predetermined concentration of phosphorus into the low-temperature polysilicon 100. Detailed description is omitted.
[0019]
After the formation of the source / drain 101, 102, as shown in FIG. 11C, the silicon oxide SiO having a film thickness of, for example, about 0.3 μm is formed as the interlayer insulating layer 50.₂Are deposited by the above-described manufacturing method, and a pair of openings 103 and 104 are formed on the source / drain 101 and 102 by a fine processing technique. At the same time, an opening 61 is formed on the scanning line 11 in a region outside the image display unit to expose a part of the scanning line 11.
[0020]
Subsequently, as shown in FIG. 11D, after a heat-resistant metal thin film such as Ti, Ta, or Cr having a film thickness of about 0.3 m is deposited as a source / drain wiring material using a film forming apparatus such as sputtering. Then, the source (signal line) / drain wirings 12 and 21 are formed on the interlayer insulating layer 50 including the pair of openings 103 and 104 by a fine processing technique. At this time, the electrode terminal 6 made of the refractory metal thin film may be formed simultaneously with the exposed scanning line 11 in the opening 61 outside the image display portion. Similarly, a part of the signal line 12 may be used as the electrode terminal 5 outside the image display unit. When low resistance is required for the source / drain wiring material, a three-layer structure such as Ti / AL / Ti, Mo / AL / Mo, etc. is applied in combination with AL, which is a low resistance metal, and two types of heat resistance The metal thin film has two functions: the function of preventing the AL from directly entering the source / drain and preventing ohmic contact, and the function of preventing the electrochemical corrosion caused by the contact between the AL and ITO. Is demonstrating.
[0021]
Thereafter, passivation of the active substrate 2 is necessary. As shown in FIG. 11E, the openings 62 are formed on the drain wiring 21, the scanning line electrode terminal 6, and the signal line electrode terminal 5, respectively. , 63, and 64, a silicon nitride layer (SiNx) having a film thickness of about 0.3 μm is formed using a PCVD apparatus. The passivation insulating layer 200 is made of a highly transparent and heat-resistant photosensitive acrylic resin, for example, a product name Optmer PC302 made of Japan Synthetic Rubber, and is formed to a thickness of 1 μm or more to flatten the surface of the insulating substrate 2. It is also possible.
[0022]
Furthermore, as shown in FIG. 11F, after depositing ITO (Indium-Tin-Oxide), which is a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm, using a film forming apparatus such as sputtering. Then, the pixel electrode 22 including the drain wiring 21 in the opening 62 is selectively formed on the passivation insulating layer 200 by microfabrication technology to complete the active substrate. Regarding the configuration of the electrode terminals, the exposed scanning line electrode terminals 6 and signal line terminal electrodes 5 in the openings 63 and 64 formed in the passivation insulating layer 200 may be selected, or these electrodes may be selected. The transparent conductive electrode terminals 6 ′ and 5 ′ formed on the transparent conductive electrode terminals 6 ′ and 5 ′ may be selected. It is common to connect.
[0023]
Regarding the configuration of the storage capacitor 15, FIG. 10 illustrates an example in which the pixel electrode 22 and the scanning line 11 are configured via a passivation insulating layer 200 formed on the scanning line 11. The configuration of 15 is not limited to this, and the storage capacitor line 16 and the pixel electrode 22 formed simultaneously with the scanning line 11 may be configured via the passivation insulating layer 200. However, when a thick transparent planarizing resin layer is used for the passivation insulating layer 200, it is difficult to increase the storage capacity value, so the configuration of the storage capacity requires some consideration, and other configurations are possible. Detailed explanation is omitted.
[0024]
[Problems to be solved by the invention]
As described above, the fabrication of a semiconductor device for display device (active substrate) having an insulated gate transistor using low-temperature polysilicon as a semiconductor layer requires six to seven photolithography steps, and amorphous silicon. Compared with a semiconductor device for a display device having an insulated gate transistor having a semiconductor layer as a semiconductor layer, the process cost cannot be said to be low. From such a point of view, a liquid crystal display device having an insulated gate transistor with a low-temperature polysilicon semiconductor layer has a medium-to-small screen size with a diagonal line of 25 cm or less and a high added value with built-in scanning line and signal line driving circuits. The product is only commercialized. The present invention has been made in view of the present situation, and an object of the present invention is to reduce the number of manufacturing processes in order to realize a reduction in the price of a liquid crystal panel and cope with an increase in demand.
[0034]
[Means for Solving the Problems]
Claims of the invention1The method for manufacturing a semiconductor device for a display device includes a step of forming a polycrystalline silicon layer on one main surface of an insulating substrate, a gate insulating layer, a first metal layer, and a lift-off layer on the polycrystalline silicon layer. And a step of selectively removing the lift-off layer, the first metal layer, the gate insulating layer, and the polycrystalline silicon layer using the photosensitive resin pattern corresponding to the scanning line as a mask, and the photosensitive resin pattern The lift-off layer, the first metal layer, and the gate insulating layer are etched using the photosensitive resin pattern with the film reduced as a mask. A step of partially exposing the crystalline silicon layer; a step of forming an insulating layer on a side surface of the first metal layer; and irradiation with impurities.
Alternatively, a step of forming a source / drain by implantation, a step of depositing one or more second metal layers on the insulating substrate, and a step of removing the lift-off layer and the second on the lift-off layer A step of selectively removing a metal layer, a step of forming a source / drain wiring including the source / drain on the insulating substrate and comprising a second metal layer, and a first on the drain wiring. Forming a passivation insulating layer having a pair of second openings on the opening and the source wiring; connecting the pixel electrode including the first opening to the divided source wiring; And a step of forming a connection layer including two openings on the passivation insulating layer.
[0035]
This configuration promotes rationalization of the active substrate manufacturing process and reduces the number of photolithography steps.The
[0036]
Claims of the invention2A method for manufacturing a semiconductor device for a display device of claim1The method for manufacturing a semiconductor device for a display device described above further includes a step of forming an organic insulating layer on at least the connection layer in the image display portion.
[0037]
With this configuration, an insulating layer is formed on the connection layer while minimizing the increase in manufacturing steps., tableThe reliability and yield of the display device are improved.
[0038]
Claims of the invention3The manufacturing method of the semiconductor device for a display device described in claim1The manufacturing method of a semiconductor device for a display device described above includes a step of forming a low-resistance metal layer and an organic insulating layer on at least a connection layer.
[0039]
With this configuration, the resistance of the signal line can be reduced, and a display device with high compatibility with a large screen and high definition can be obtained. Claims of the invention4The method for manufacturing a semiconductor device for a display device described above is characterized in that an insulating layer is formed by anodizing the first metal layer. Claims of the invention5The manufacturing method of the semiconductor device for display devices described above is characterized in that an insulating layer which is an organic insulating layer is formed by electrodeposition.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
The first and second embodiments of the present invention are shown in FIGS. 1 and 2, the third and fourth embodiments are shown in FIGS. 3 and 4, and the fifth and sixth embodiments are shown in FIGS. This will be described based on the drawings described.
[0041]
FIG. 1 shows a plan view of a display device semiconductor device (active substrate) according to the first and second embodiments of the present invention, and FIG. 2 shows an AA ′ line and a partial BB ′ line in FIG. Sectional drawing of this manufacturing process is shown. In addition, about the site | part of the same function as a conventional example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
[0042]
In the manufacturing method of the active substrate according to the embodiment of the present invention, first, an alkali blocking layer is deposited on one main surface of the glass substrate 2 which is an insulating transparent substrate as in the conventional example. After that, an amorphous silicon layer having a film thickness of about 0.05 μm is deposited using a film-forming apparatus such as a PCVD apparatus and heated to reduce the hydrogen content, and then the amorphous silicon is irradiated with an excimer laser. Crystallize the layer.
[0043]
Next, on the crystallized silicon layer, using a film forming apparatus such as CVD or TEOS-PCVD, SiO 2 having a thickness of about 0.1 μm and the gate electrode, which becomes the gate insulating layer 30 at a substrate heating temperature of about 400 to 500 ° C. For example, Ta or AL alloy having a film thickness of about 0.2 μm, an alloy of Ta and a high melting point metal such as Cr, W, or Mo, or Ta A molybdenum (Mo) layer having a film thickness of about 0.2 μm is deposited as a lift-off layer by depositing, for example, an Al alloy containing about several percent of Ta among silicides of high melting point metals such as Cr, W, and Mo. 40 is attached.
[0044]
Thereafter, as shown in FIG. 2A, a photosensitive resin pattern 41 corresponding to the scanning line 11 which also serves as the gate electrode of the insulated gate transistor is formed on the molybdenum (Mo) layer 40 with a film thickness of about 2.5 μm, for example. Then, using the photosensitive resin pattern 41 as a mask, the molybdenum (Mo) layer 40, the first metal layer, the gate insulating layer, and the crystallized low-temperature polysilicon are sequentially etched to expose the glass substrate 2.
[0045]
Subsequently, after the film thickness of the photosensitive resin pattern 41 is reduced by, for example, about 1 μm to 41 ′ by treatment in oxygen gas plasma or the like, the photosensitive resin pattern 41 ′ is formed as shown in FIG. As a mask, the molybdenum (Mo) layer, the first metal layer, and the gate insulating layer are sequentially etched again to partially expose the low-temperature polysilicon 100 (about 1 μm on one side) as 40 ′, 11, 30 ′.
[0046]
(First embodiment)
Subsequently, although not shown, an anodic oxidation layer 33 having a thickness of, for example, about 0.5 μm is selectively formed on the side surface of the gate electrode 11 by anodic oxidation treatment in the chemical conversion solution as shown in FIG. To do. As described above, if the gate electrode material is a Ta alloy, an AL alloy, or a refractory metal silicide, the anodic oxide layer has Ta.₂O₅, Al₂O₃, SiO₂An insulating layer containing as a main component can be obtained. In order to carry out anodization, all the gate electrodes (scanning lines) 11 need to be connected in parallel or in series, and a connection part in which these wirings are bundled on a part of the peripheral part of the glass substrate 2 is provided. The photosensitive resin pattern 41 'on the connecting portion is formed and pierced by a connecting means having a sharp cutting edge such as a clip, and anodization is performed in the chemical conversion solution while applying a direct (+) potential. Is omitted.
[0047]
(Second Embodiment)
Alternatively, if a solution containing about 0.01% of a polyamic acid salt is used as an electrodeposition solution and electrodeposition is performed by applying a + (plus) potential to the scanning line 11, an organic film having a thickness of about 0.5 μm is formed on the side surface of the gate electrode. It is also possible to selectively form a polyimide layer 33 ′ which is an insulating layer. In this case, the necessity of the gate electrode 11 being an anodizable metal is eliminated.
[0048]
All the scanning lines 11 need to be connected in parallel or in series because the insulating layer selectively formed on the side surface of the gate electrode is formed electrochemically. Needless to say, if the series-parallel arrangement of the lines 11 is not released, not only the electrical inspection of the active substrate 2 but also the actual operation as a liquid crystal display device is hindered. As a means for releasing the connection, a method of irradiating a high energy light such as a laser can be cited. On the other hand, diversion to countermeasures as a part of countermeasures against static electricity is also an important technique, but detailed explanation is omitted.
[0049]
After the insulating layer 33 (33 ′) is selectively formed on the side surface of the gate electrode 11, the photosensitive resin pattern 41 ′ is removed, and although not shown, ions are formed using the gate electrode 11 and the insulating layer 33 (33 ′) as a mask. Phosphorus or boron as an impurity is implanted into the low-temperature polysilicon 100 by implantation or ion irradiation to form the source / drain 101, 102 of the insulated gate transistor. As a result of the insulating layer of about 0.5 μm on one side adjacent to the gate electrode 11 acting as an ion implantation mask, it is possible to form regions having a smaller ion implantation amount than the source / drain 101 and 102 on both sides of the channel. Yes.
[0050]
Thereafter, as shown in FIG. 2 (d), as a source / drain wiring material, for example, a heat-resistant metal thin film 34 such as Ti, Ta, Cr having a film thickness of about 0.2 μm is deposited using a film forming apparatus such as sputtering. After that, when the insulating substrate 2 is left in a hydrogen peroxide solution containing a small amount of diluted nitric acid or ammonia, the molybdenum layer 40 'disappears and the refractory metal thin film 34 on the molybdenum layer 40' is selectively lifted off (peeled off). The gate electrode 11 having the insulating layer 33 (33 ′) on the side surface is exposed.
[0051]
Further, as shown in FIG. 2E, source (signal line) / drain wirings 12 and 21 are formed on the insulating substrate 2 including the source / drains 101 and 102 by a microfabrication technique. Since the refractory metal thin film 34 disappears, the signal line 12 ′ is divided and formed on the scanning line 11 as shown in FIG.
[0052]
After this, it is necessary to form a passivation of the insulated gate transistor. As shown in FIG. 2F, for example, SiO2 having a film thickness of about 0.3 .mu.m is deposited as the passivation insulating layer 200 by the above-described manufacturing method. A pair of openings 65 are formed on both ends of the signal line 12 ′ separated from the openings 62 on the drain wiring 21 by a technique. At the same time, an opening 63 is formed on the scanning line 11 in a region outside the image display portion, and a part of the scanning line 11 is formed, and an opening 64 is formed on the signal line 12 and a part of the signal line 12 is formed. Exposed.
[0053]
Further, as shown in FIG. 2G, ITO, which is a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm, is deposited using a film forming apparatus such as sputtering, and is then applied onto the passivation insulating layer 200. The signal line 12 ′ is divided by the microfabrication technique, including the pixel electrode 22 including the drain wiring 21 in the opening 62 and the signal line (source wiring) 12 ′ crossing the scanning line 11 and including the signal line (source wiring) 12 ′ in the opening 65. Are selectively formed. At the same time, transparent conductive electrode terminals 6 ′ and 5 ′ are formed including openings 63 and 64, and these electrode terminals are connected by a transparent conductive short-circuit line 80 to take measures against static electricity. The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and the embodiment of the present invention is completed.
[0054]
Regarding the configuration of the storage capacitor 15, FIG. 1 illustrates an example in which the pixel electrode 22 and the scanning line 11 are configured via a passivation insulating layer 200 formed on the scanning line 11. The configuration of the capacitor 15 is not limited to this, and other configurations are possible, but a detailed description thereof is omitted.
[0055]
(Third and fourth embodiments)
In the first and second embodiments, both the connection layer 81 that interconnects the pixel electrode 22 and the divided signal line 12 ′ are exposed on the uppermost layer of the active substrate 2. For this reason, there is a concern that conductive foreign matter may enter the liquid crystal cell, causing a short circuit between the counter electrode 14 on the counter substrate (color filter) 9 and the connection layer 81, thereby causing a cross-shaped line defect. In addition, flicker is likely to occur in a display image with a slight DC component whose value increases during high-temperature operation. Therefore, a countermeasure for forming an appropriate insulating layer on the connection layer 81 is effective.
[0056]
In order to minimize the increase in the manufacturing process, in the third and fourth embodiments, the organic insulating layer 71 is formed on the connection layer 81 in the dark by electrodeposition. As shown in FIG. 4, the manufacturing steps up to the formation of the connection layer 81 are the same as those in the first and second embodiments. As described above, a solution containing about 0.01% of a polyamic acid salt is used as an electrodeposition solution from among materials that can be electrodeposited as an organic insulating layer that can ensure the insulating properties necessary for the device. A positive potential is applied, and electrodeposition is performed in a dark place. As shown in FIG. 4H, the electrodeposition voltage is about several volts and a polyimide layer 71 having a thickness of about 0.3 μm is formed on the connection layer 81. To do. The reason why electrodeposition is performed in the dark is to suppress the organic insulating layer from being formed on the pixel electrode 22 by the light leakage current of the insulated gate transistor. If a small amount of organic insulating layer is formed thereon, it can be easily removed by treating the active substrate 2 with oxygen plasma.
[0057]
The polyimide resin is a resin having high heat resistance like the acrylic resin, and after the polyimide layer 71 is formed, it is preferably subjected to heat treatment at 200 to 400 ° C. for several minutes to several tens of minutes to obtain the insulation characteristics and resistance of the polyimide layer 71. Although it is preferable to improve the chemical properties, the required insulation characteristics are governed by the heat resistance of the insulated gate transistor and the composition of the liquid crystal material, so the heating conditions must be determined experimentally. The heating conditions are also applicable when the polyimide layer 33 ′ is formed on the side insulating layer of the gate electrode 11 described above.
[0058]
The design items to be noted in electrodeposition are that all the short-circuit lines 80 need to be electrically connected, and the short-circuit lines 80 are arranged around a single unit of the display device substrate so as to form a grid on the cutting line or the cutting line. And a connection pattern is preferably provided on the outer peripheral portion of the display device substrate. It should be noted that this electrical connection is not limited to an electrical inspection of the active substrate 2 but a liquid crystal display unless the connection is released and the electrode terminal 6 of the scanning line and the electrode terminal 5 of the signal line are opened at some subsequent manufacturing step. Needless to say, the actual operation of the device is hindered. Examples of means for releasing the connection include irradiation with laser light which is high energy light, or cutting or cleaving of the active substrate 2 in a multi-faced glass substrate.
[0059]
The electrode terminals 5 ′ and 6 ′ need to be exposed in order to mount the driving semiconductor integrated circuit chip, and thereafter, the organic insulating layer 71 formed on the electrode terminals 5 ′ and 6 ′ is removed. However, since selective removal using, for example, a photosensitive resin pattern as a mask increases the number of manufacturing steps, one solution is disclosed in Japanese Patent Application Laid-Open No. Hei 2-275925. As described above, after the active substrate 2 obtained as described above is bonded to the color filter 9 which is the counter substrate to form a liquid crystal panel, the electrode terminals 5 in the region outside the image display unit using the color filter 9 as a mask. Organic insulation on ', 6'Layer 7It is recommended to selectively remove 1 with oxygen plasma. Of course, it is possible to substitute the UV-O3 (ozone generation by ultraviolet irradiation) technology which is a recent technology. A liquid crystal display device is obtained by mounting a driving semiconductor integrated circuit chip on the exposed electrode terminals 5 'and 6'.
[0060]
In other words, the organic insulating layer 71 may be formed only in the image display portion, and in order to prevent the organic insulating layer from being formed on the electrode terminals 5 ′ and 6 ′ outside the image display portion, the prior patent As disclosed in Japanese Patent Application No. 2000-107577, there is also a manufacturing method in which the organic insulating layer 71 is selectively formed only on the connection layer 81 in the image display section using the in-substrate selective electrochemical processing apparatus. This is convenient for obtaining a large-screen liquid crystal display device. The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and the embodiment of the present invention is completed.
[0061]
As in the first and second embodiments, the difference between the third and fourth embodiments is that the anodic oxide layer 33 or the organic insulating layer 33 ′ is selected as the insulating layer selectively formed on the side surface of the gate electrode 11. It is a difference of what to do.
[0062]
(Fifth and sixth embodiments)
In the first to fourth embodiments, the connection layer 81 is the same transparent conductive layer as the picture element electrode 22, and generally speaking, the resistance value is about one digit higher than that of the metal layers constituting the scanning line 11 and the signal line 12. Get higher. Therefore, when the number of connection layers 81 is large or elongated, that is, in a large screen / high definition display device, the resistance value of the signal line increases and the fidelity of the display image decreases.
[0063]
In the fifth and sixth embodiments, plating is adopted as a technique for selectively forming a low resistance metal layer on the connection layer 81 from such a viewpoint, and specifically, gold, silver or copper is used on the connection layer 82. Is formed. After the formation of the transparent conductive connection layer 82 as shown in FIG. 6G in the same manufacturing process as in the first and second embodiments, the low resistance metal plate is connected to the anode, although not shown. When the layer 82 (short-circuit line 80) is a cathode and a DC voltage of several to several tens of volts is applied in a plating solution in the dark, the above-described low-resistance metal is formed on the connection layer 82 as shown in FIG. The thin film layer 72 is formed. The film thickness may be determined by the screen size and definition of the liquid crystal display device and the required response speed (time constant) of the signal line waveform including the signal line 12 ′ and the connection layer 82, for example, 0.5 μm. To be elected. A design matter to be noted in the plating is that all the connection layers 82 are electrically connected in parallel or in series as in the formation of the organic insulating layer in the first embodiment. In addition, since the resistance value of the connection layer can be lowered as shown in FIG. 5, the connection layer 82 does not interconnect the divided signal lines 12 ′ unlike FIG. 1 and FIG. It is wise to make it function as a signal line. That is, the divided signal line 12 ′ functions as a redundant wiring for the disconnection of the connection layer 82 that is a signal line.
[0064]
Subsequently, as in the third and fourth embodiments, a solution containing about 0.01% of a polyamic acid salt is used as an electrodeposition liquid, and a + (plus) potential is applied to the connection layer 82 provided with the thin film layer 72 of a low resistance metal. As shown in FIG. 6 (i), the polyimide layer 71, which is an organic insulating layer, is selectively formed in a thickness of about 0.3 μm on the low-resistance metal thin film layer 72 in the dark. Form.
[0065]
The reason for performing plating and electrodeposition in the dark is to suppress the formation of the low-resistance metal layer and the organic insulating layer on the pixel electrode 22 due to the light leakage current of the insulated gate transistor. If a small amount of a low-resistance metal layer and an organic insulating layer are formed on the pixel electrode 22 with a slight leakage current of the type transistor, the surface of the active substrate 2 is thinly removed by reverse sputtering of Ar (argon). There is no problem and there is no need to use chemicals to remove the low-resistance metal layer.
[0066]
Thereafter, as in the third and fourth embodiments, the above active substrate is bonded to a color filter which is a counter substrate to form a liquid crystal panel, and then the low resistance of the region outside the image display unit using the color filter as a mask. The polyimide resin on the thin film layer 71 made of metal is selectively removed by oxygen plasma or the like, and a semiconductor integrated circuit chip for driving is mounted to complete the fifth and sixth embodiments of the present invention.
[0067]
Alternatively, the low-resistance metal layer and the organic insulating layer may be formed up to the vicinity of the electrode terminals 5 ′ and 6 ′ outside the image display portion, and the low-resistance metal layer and the organic insulation are formed using an in-substrate selective electrochemical processing apparatus. It would be reasonable to selectively form layers within the active substrate plane.
[0068]
The difference between the fifth and sixth embodiments is that, like the first and second embodiments, the anodic oxide layer 33 or the organic insulating layer 33 ′ is selected as the insulating layer selectively formed on the side surface of the gate electrode 11. It is a difference of what to do.
[0069]
In the fifth and sixth embodiments, since the low resistance metal layer is provided on the connection layer 82, the resistance value of the connection layer 82 can be sufficiently lowered by increasing the thickness of the low resistance metal layer. As shown in FIG. 5, the advantage in device design that the connection layer is extended and the adjacent connection layers are overlapped to form the signal line 82 becomes extremely large. This is because the signal line 12 'divided in the present invention is formed by lift-off, so that it is difficult to increase the film thickness from the beginning. Further, since the divided signal line 12 ′ is connected in parallel to the signal line 82 via the pair of openings 65, it acts as a redundant configuration against the disconnection of the signal line 82, in other words, it is hard to be disconnected and has a sufficient resistance value. Liquid crystal display device that can sufficiently satisfy the demand for large screen and high definition.
As is apparent from the description of the embodiment, the requirements of the present invention are such that when the insulated gate transistor is manufactured, the lift-off layer, the gate electrode, and the gate insulating layer are etched together and self-aligned with the side surface of the gate electrode. Forming an insulating layer on the gate electrode, performing ion implantation (irradiation) using the insulating layer on the side surface of the gate electrode as a mask for the LDD structure, and forming source / drain electrodes on the source / drain in a self-aligned manner by lift-off The display device semiconductor device in which the material and film thickness of the pixel electrode, the gate insulating layer, etc. are different with respect to the configuration and members other than these, and the semiconductor device for display device in which a color filter is formed It is obvious that the difference in the configuration of the liquid crystal panel or the manufacturing method thereof also belongs to the category of the present invention. For example, the pixel electrode and the pixel electrode are located on the same substrate. Application also present invention in the liquid crystal panel of IPS (In-Plain-Switching) method of controlling giving lateral electric field to the liquid crystal between the opposed electrode formed at a distance of it is easy. In addition, the utility of the present invention is also applicable to a reflective liquid crystal image display device in which the pixel electrode is made of a metal layer, and also to a transflective liquid crystal image display device having a transparent electrode and a metal reflective electrode on the pixel electrode. It is clear that the semiconductor layer of the insulated gate transistor is not limited to polycrystalline silicon, and may be amorphous silicon, microcrystalline silicon, a mixed crystal thereof, or other semiconductor materials. is there.
[0071]
【The invention's effect】
According to the method for manufacturing a semiconductor device for a display device according to the present invention,Since the source / drain wiring is formed on the source / drain in a self-aligned manner and the semiconductor layer is not exposed, the conventional interlayer insulation layer becomes unnecessary and the number of photo etching processes can be reduced compared to the conventional example. As a result, excellent effects such as a reduction in manufacturing cost were obtained.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device for a display device according to first and second embodiments of the present invention.
FIG. 2 is a cross-sectional view of a manufacturing process of a semiconductor device for a display device according to first and second embodiments of the present invention.
FIG. 3 is a plan view of a semiconductor device for a display device according to third and fourth embodiments of the present invention.
FIG. 4 is a cross-sectional view of a manufacturing process of a semiconductor device for a display device according to third and fourth embodiments of the present invention.
FIG. 5 is a plan view of a display device semiconductor device according to fifth and sixth embodiments of the present invention;
FIG. 6 is a cross-sectional view of a manufacturing process of a semiconductor device for a display device according to fifth and sixth embodiments of the present invention.
FIG. 7 is a perspective view showing a mounting state of the liquid crystal panel.
FIG. 8 is an equivalent circuit diagram of a liquid crystal panel.
FIG. 9 is a cross-sectional view of a conventional liquid crystal panel
FIG. 10 is a plan view of a conventional active substrate.
FIG. 11 is a cross-sectional view of a manufacturing process of a conventional active substrate
[Explanation of symbols]
1 LCD panel
2 Active substrate (insulating substrate, glass substrate)
3 Semiconductor integrated circuit chip
4 TCP film
5,6 electrode terminals
9 Color filter (opposing glass substrate)
10 Insulated gate transistor
11 Scanning line (gate wiring, gate electrode)
12 Signal lines (source wiring, source electrode)
16 Storage capacitor line
17 LCD
21 Drain wiring (electrode)
22 (Transparent conductive) picture element electrode
30 Gate insulation layer
33 Insulating layer (on side of gate electrode)
34 Heat-resistant metal layer
41 Photosensitive resin pattern (forming scan lines)
50 Interlayer insulation layer
61 Opening (on scan line)
62 Opening (on drain wiring)
63 Opening (on terminal electrode of scan line)
64 Opening (on terminal electrode of signal line)
65 Opening (on split signal line)
71 Organic insulation layer
72 Low resistance metal layer
80 Short-circuit wire (for anti-static measures)
81,82 connection layer
100 (Island-like) Low-temperature polysilicon
101,102 Source / Drain
200 Passivation insulation layer

Claims (5)

Forming a polycrystalline silicon layer on one main surface of the insulating substrate; and depositing a gate insulating layer, a first metal layer, and a lift-off layer on the polycrystalline silicon layer; Selectively removing the lift-off layer, the first metal layer, the gate insulating layer, and the polycrystalline silicon layer using the photosensitive resin pattern as a mask; and partially reducing the lift-off layer by reducing the thickness of the photosensitive resin pattern. And exposing the polycrystalline silicon layer by etching the lift-off layer, the first metal layer, and the gate insulating layer using the reduced photosensitive resin pattern as a mask, and A step of forming an insulating layer on a side surface of the first metal layer; a step of forming a source / drain by irradiating or injecting impurities; and a step of forming one or more second metal layers on the insulating substrate. Worker Removing the lift-off layer and selectively removing the second metal layer on the lift-off layer; and a source comprising the second metal layer including the source / drain on the insulating substrate. A step of forming a drain wiring; a step of forming a passivation insulating layer having a first opening on the drain wiring and a pair of second openings on the source wiring; and the first opening. A method of manufacturing a semiconductor device for a display device, comprising: forming a pixel electrode including the pixel electrode; and a connection layer including the second opening connected to the divided source wiring and formed on the passivation insulating layer. Method for manufacturing a display device for a semiconductor device according to claim 1, further comprising a step of forming an organic insulating layer on the connection layer in at least the image display unit. Method for manufacturing a display device for a semiconductor device according to claim 1, further comprising a step of forming at least connected low-resistance metal layer on the layer and an organic insulating layer. By the first metal layer to anodic oxidation, a method of manufacturing a display device for a semiconductor device according to claim 1 to form an insulating layer. The manufacturing method of the semiconductor device for display apparatuses in any one of Claims 1-3 which form the insulating layer which is an organic insulating layer by electrodeposition.

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