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JP3623638B2 - Optical semiconductor device and manufacturing method thereof - Google Patents
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JP3623638B2 - Optical semiconductor device and manufacturing method thereof - Google Patents

Optical semiconductor device and manufacturing method thereof Download PDF

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JP3623638B2
JP3623638B2 JP24370597A JP24370597A JP3623638B2 JP 3623638 B2 JP3623638 B2 JP 3623638B2 JP 24370597 A JP24370597 A JP 24370597A JP 24370597 A JP24370597 A JP 24370597A JP 3623638 B2 JP3623638 B2 JP 3623638B2
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Prior art keywords
ridge
shape
type
ohmic
wiring
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JP24370597A
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JPH1187759A (en
Inventor
芳明 佐野
昌克 笠置
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Description

【0001】
【発明の属する技術分野】
本発明は、光半導体素子に係り、特に、導波路型の受光ダイオードの構造及びその製造方法に関するものである。
【0002】
【従来の技術】
光通信システムにおいて、ギガヘルツの高周波光信号を電気信号に変換する受光素子として、導波路型の受光ダイオードが用いられる。受光ダイオードの良好な高周波特性を得るためには、半導体部分を微細に加工するだけでなく、電極と半導体の接触抵抗や、配線の浮遊容量などをできるだけ低減させる必要がある。
【0003】
ここで、従来のエアーブリッジ配線構造のInP系の導波路型受光ダイオードの製造方法を図4の製造工程断面図に従って説明する。図4の左列は正面断面図、右列は側面断面図である。
【0004】
まず、図4(a)に示すように、半絶縁性InP基板1上にMBE(Molecular Beam Epitaxy)法やMOCVD(Metal Organic Chemical Vapor Deposition)法などの結晶成長法によって、n型InPオーミック層2、n型InGaAsPクラッド層3、ノンドープのInGaAs光吸収層4、p型InGaAsPクラッド層5、p型InPオーミック層6を順次堆積後、ホトリソ法によってマスクパターン7を形成する。
【0005】
次に、図4(b)に示すように、マスクパターン7によってp型InPオーミック層6、p型InGaAsPクラッド層5、ノンドープのInGaAs光吸収層4、n型InGaAsPクラッド層3を順次エッチングし、リッジ型の導波路形状9を得る。同様に、ホトリソ法とエッチングにより、n型InPオーミック層2をパターニングし、n型オーミック領域10を形成した後、素子表面全体に絶縁膜11を堆積する。
【0006】
次いで、図4(c)に示すように、ホトリソ法とマスク合わせによって、n型オーミック領域10上にレジスト開口を形成し、絶縁膜のエッチング、オーミック性の金属の蒸着と、リフトオフによりn電極12を形成する。同様に、導波路形状9の頂面内のp型InPオーミック層6上にp電極13を形成する。
【0007】
次に、図4(d)に示すように、ホトリソ法によって、エアーブリッジで配線用下地レジスト14を形成する。
【0008】
次に、図4(e)に示すように、ホトリソと配線金属の蒸着により、n電極の配線15を形成する。
【0009】
次いで、図4(f)に示すように、配線用下地レジスト14を溶解除去して、エアーブリッジ配線16を形成する。
【0010】
最後に、図4(f)中に示す位置で半導体を劈開し、導波路型素子を得る。入射光は、矢印の方向からInGaAs光吸収層4に吸収され、電気信号に変換される。
【0011】
【発明が解決しようとする課題】
受光素子を高周波動作させるためには、素子に連結される直列抵抗、インダクタンスや寄生容量を極力低減することが重要である。しかしながら、高周波用の導波路型受光素子のリッジ型の導波路形状9の寸法は幅が4〜6μm、長さが10〜20μm、高さが2〜3μmと非常に微小に設計されている。
【0012】
図4(c)において、p電極13をリッジ型の導波路形状9の頂上面内に確実に形成するためには、ホトリソ工程のマスク合わせ精度の限界から、p電極13の幅をリッジ型の導波路形状9の頂面の幅よりも、通常2〜3μm小さくすることが必要である。このため、頂上面幅を4μmとするとp電極13の幅は1μm程度となり、オーミック接触面積が小さくなってコンタクト抵抗が増大するという欠点があった。
【0013】
また、同様に、図4(d)〜(f)における配線工程においても、前記と同じ理由により、リッジ型の導波路形状9の配線幅が1μm程度と細くなるために、インダクタンスや配線抵抗が大きくなってしまうという欠点があった。
【0014】
本発明は、上記問題点を除去し、素子に連結される直列抵抗、インダクタンスや寄生容量を極力低減し、高周波特性に優れた光半導体素子及びその製造方法を提供することを目的とする。
【0015】
【課題を解決するための手段】
本発明は、上記目的を達成するために、
〔1〕リッジ形状を有する光半導体素子において、リッジ上面側のオーミック性電極がこのリッジ上面側と完全に接触するとともに前記オーミック性電極の電極幅が前記リッジ上面の幅よりも大きい形状を有するとともに、このリッジ上面側のオーミック性電極が同時にリッジ外部のパッド部にまでエアーブリッジ状に引き出される形状を有するようにしたものである。
【0016】
〕リッジ形状を有する光半導体素子の製造方法において、リッジ型の導波路形状を得る工程と、このリッジ型の導波路形状を覆うようにレジストを形成する工程と、半導体基板全体をアッシングして前記レジストを膜べりさせ、前記リッジ型の導波路形状の頂面上が露出したレジストパターンを得る工程と、開口幅が前記リッジ型の導波路形状より大きい新たなレジストパターンを形成する工程と、前記リッジ型の導波路形状の頂面とオーミック接触する配線金属によってオーミック性電極及び前記リッジ上面側のオーミック性電極が同時にリッジ外部のパッド部にまでエアーブリッジ状に引き出される形状を有する配線を形成する工程とを施すようにしたものである。
【0017】
【発明の実施の形態】
以下、本発明の実施の形態について詳細に説明する。
【0018】
図1は本発明の実施例を示す半導体受光素子の正面断面図、図2はその半導体受光素子の側面断面図、図3は本発明の実施例を示す半導体受光素子の製造工程断面図である。なお、図3の左列は正面断面図、右列は側面断面図である。
【0019】
この実施例の半導体受光素子は、図1及び図2に示すように、半絶縁性InP基板21上に、n型InPオーミック層22、n型InGaAsPクラッド層23、ノンドープのInGaAs光吸収層24、p型InGaAsPクラッド層25、p型InPオーミック層26からなるリッジ型の導波路形状を有し、このリッジ型の導波路形状の両側には、オーミック性電極32が形成され、n型InPオーミック層22に接続されている。
【0020】
更に、リッジ型の導波路形状の上部には、p型InPオーミック層26の幅よりも広い幅のオーミック性電極35が形成されている。また、このオーミック性電極35は、図2に示すように、半絶縁性InP基板21上のパッド部37に、オーミック性電極35と一体に接続される配線36により接続されている。なお、38は入射光39が入射される劈開面である。
【0021】
以下、この実施例の半導体受光素子の製造方法を図3を用いて説明する。
【0022】
(1)従来工程と同様に、まず、図3(a)に示すように、半絶縁性InP基板21上に結晶成長法によって、n型InPオーミック層22、n型InGaAsPクラッド層23、ノンドープのInGaAs光吸収層24、p型InGaAsPクラッド層25、p型InPオーミック層26を順次堆積後、ホトリソ法によって、マスクパターン27を形成する。
【0023】
(2)次に、図3(b)に示すように、マスクパターン27によってp型InPオーミック層26、p型InGaAsPクラッド層25、ノンドープのInGaAs光吸収層24、n型InGaAsPクラッド層23を順次エッチングし、リッジ型の導波路形状29を得る。同様に、ホトリソ法とエッチングによりn型InPオーミック層22をパターニングし、n型オーミック領域30を形成した後、素子正面全体に絶縁膜31を堆積する。
【0024】
(3)次に、図3(c)に示すように、n型オーミック領域30に対するオーミック性電極32を形成後、リッジ型の導波路形状29を包含するようにレジストパターン33を形成する。ここで、レジストパターン33は通常のレジスト材料やポリイミドなどの樹脂を用いても効用は同じである。また、液状の樹脂材料を凹凸上に塗布する場合、その粘性のために凸部上では薄く被着するため、リッジ型の導波路形状29の頂面上では特に薄くなる。
【0025】
(4)次に、図3(d)に示すように、半導体基板全体をアッシング(酸素プラズマによる樹脂の灰化)してレジスト33を膜べりさせ、リッジ型の導波路形状29の頂面上が露出したレジストパターン33′を得る。次いで、開口幅がリッジ型の導波路形状29より大きい新たなレジストパターン34を形成する。
【0026】
(5)次に、図3(e)に示すように、p型InPオーミック層26とオーミック接触する配線金属(例えば、Ti/Pt/Au構造)の蒸着/リフトオフによって、オーミック性電極35とそれに接続される配線36を形成する。この工程では、配線ホトリソ後、絶縁膜31をエッチングしてから配線金属の蒸着を行っても良い。ここで、オーミック性電極35の電極幅は、図3(e)の正面断面図から分かるように、リッジ型の導波路形状29を包含するように幅広く形成され、また、図3(e)の側面断面図から分かるように、リッジ型の導波路形状29の頂面から半絶縁性InP基板21上のパッド部37と接続されるように形成される。
【0027】
最後に、図3(f)に示すように、レジストパターン33′を除去してから劈開を行って、導波路型の受光素子を得る。ここで、レジストパターン33をポリイミド等の樹脂材料とし、最終的に除去しないままでも良く、さらにこのときパッド部37をポリイミド上に形成しても良い。
【0028】
上記したように、本実施例によれば、図3(c)に示すように、ホトリソの精密なマスク合わせを用いることなく、リッジ型の導波路形状29の頂部全体と配線金属がオーミック接触できるため、再現性良くコンタクト抵抗を大きく低減することができる。また、配線用レジストパターン34をレジストパターン33′の上に形成しているため、リッジ型の導波路形状29の頂部のオーミック性電極35の電極幅を、リッジ型の導波路形状29の頂部の幅よりも大きくすることができ、配線36のコンダクタンスを小さくできるという利点がある。
【0029】
更に、リッジ型の導波路形状29の頂部のオーミック電極35はオーバーハング上に形成できるため、リッジ型の導波路形状29の側面に接触することもなく、つまり、上部配線と半導体素子との間の寄生容量を増大させる恐れがない。また、本実施例における配線はオーミック性電極35と一体に形成されているため、工程の簡略化を図ることができる。
【0030】
このように、本実施例によれば、寄生容量を増大させることなく、直列抵抗や配線のインダクタンスが小さいという、高周波特性に優れた半導体受光素子を簡便に再現性良く製造できる利点がある。
【0031】
なお、本発明は、以下のような利用形態を有する。
【0032】
上記実施例においては、光が結晶側面より入射する導波路型の受光素子について説明したが、本発明は、導波路型の光半導体素子に関し、簡便で再現性良く、上面側のオーミック性電極を低コンタクト抵抗、低インダクタンスで形成し、また、同時にパッド部に配線を引き出すことができるように構成している。つまり、本発明は、受光素子ばかりでなく、高周波で動作する導波路型のレーザーダイオードや光変調器等の光半導体素子にも適用できることは言うまでもない。
【0033】
なお、本発明は上記実施例に限定されるものではなく、本発明の趣旨に基づいて種々の変形が可能であり、これらを本発明の範囲から排除するものではない。
【0034】
【発明の効果】
以上、詳細に説明したように、本発明によれば、以下のような効果を奏することができる。
【0035】
(1)請求項1記載の発明によれば、素子に連結される直列抵抗、インダクタンスや寄生容量を極力低減し、高周波特性に優れた光半導体素子を提供するとともに、同時にパッド部に配線を引き出すことができる。
【0036】
(2)請求項記載の発明によれば、寄生容量を増大させることなく、直列抵抗や配線のインダクタンスが小さい、高周波特性に優れた半導体受光素子を簡便に再現性良く製造できる。
【図面の簡単な説明】
【図1】本発明の実施例を示す半導体受光素子の正面断面図である。
【図2】本発明の実施例を示す半導体受光素子の側面断面図である。
【図3】本発明の実施例を示す半導体受光素子の製造工程断面図である。
【図4】従来の半導体受光素子の製造工程断面図である。
【符号の説明】
21 半絶縁性InP基板
22 n型InPオーミック層
23 n型InGaAsPクラッド層
24 ノンドープのInGaAs光吸収層
25 p型InGaAsPクラッド層
26 p型InPオーミック層
27 マスクパターン
29 リッジ型の導波路形状
30 n型オーミック領域
31 絶縁膜
32,35 オーミック性電極
33,33′,34 レジストパターン
36 配線
37 パッド部
38 劈開面
39 入射光
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an optical semiconductor device, and more particularly to a structure of a waveguide type light receiving diode and a manufacturing method thereof.
[0002]
[Prior art]
In an optical communication system, a waveguide type light receiving diode is used as a light receiving element for converting a high frequency optical signal of gigahertz into an electric signal. In order to obtain good high-frequency characteristics of the light-receiving diode, it is necessary not only to finely process the semiconductor portion, but also to reduce the contact resistance between the electrode and the semiconductor, the stray capacitance of the wiring, and the like as much as possible.
[0003]
Here, a manufacturing method of a conventional InP-based waveguide type light-receiving diode having an air bridge wiring structure will be described with reference to a manufacturing process sectional view of FIG. 4 is a front sectional view, and the right column is a side sectional view.
[0004]
First, as shown in FIG. 4A, an n-type InP ohmic layer 2 is formed on a semi-insulating InP substrate 1 by a crystal growth method such as an MBE (Molecular Beam Epitaxy) method or a MOCVD (Metal Organic Chemical Vapor Deposition) method. The n-type InGaAsP cladding layer 3, the non-doped InGaAs light absorption layer 4, the p-type InGaAsP cladding layer 5, and the p-type InP ohmic layer 6 are sequentially deposited, and then a mask pattern 7 is formed by photolithography.
[0005]
Next, as shown in FIG. 4B, the p-type InP ohmic layer 6, the p-type InGaAsP cladding layer 5, the non-doped InGaAs light absorbing layer 4, and the n-type InGaAsP cladding layer 3 are sequentially etched by the mask pattern 7. A ridge-type waveguide shape 9 is obtained. Similarly, after patterning the n-type InP ohmic layer 2 by photolithography and etching to form the n-type ohmic region 10, an insulating film 11 is deposited on the entire device surface.
[0006]
Next, as shown in FIG. 4C, a resist opening is formed on the n-type ohmic region 10 by photolithography and mask alignment, and an n-electrode 12 is formed by etching of the insulating film, vapor deposition of ohmic metal, and lift-off. Form. Similarly, a p-electrode 13 is formed on the p-type InP ohmic layer 6 in the top surface of the waveguide shape 9.
[0007]
Next, as shown in FIG. 4D, a wiring base resist 14 is formed by an air bridge by a photolithography method.
[0008]
Next, as shown in FIG. 4E, an n-electrode wiring 15 is formed by vapor deposition of photolithography and wiring metal.
[0009]
Next, as shown in FIG. 4 (f), the wiring base resist 14 is dissolved and removed to form the air bridge wiring 16.
[0010]
Finally, the semiconductor is cleaved at the position shown in FIG. 4F to obtain a waveguide element. Incident light is absorbed by the InGaAs light absorption layer 4 from the direction of the arrow and converted into an electrical signal.
[0011]
[Problems to be solved by the invention]
In order to operate the light receiving element at a high frequency, it is important to reduce as much as possible the series resistance, inductance, and parasitic capacitance connected to the element. However, the dimensions of the ridge-type waveguide shape 9 of the high-frequency waveguide-type light-receiving element are designed to be very small with a width of 4 to 6 μm, a length of 10 to 20 μm, and a height of 2 to 3 μm.
[0012]
In FIG. 4C, in order to reliably form the p-electrode 13 in the top surface of the ridge-type waveguide shape 9, the width of the p-electrode 13 is set to a ridge-type from the limit of mask alignment accuracy in the photolithography process. The width of the top surface of the waveguide shape 9 is usually required to be 2 to 3 μm smaller. For this reason, when the top surface width is 4 μm, the width of the p-electrode 13 becomes about 1 μm, and there is a drawback that the ohmic contact area is reduced and the contact resistance is increased.
[0013]
Similarly, also in the wiring steps in FIGS. 4D to 4F, for the same reason as described above, the wiring width of the ridge-type waveguide shape 9 becomes as thin as about 1 μm, so that inductance and wiring resistance are reduced. There was a drawback of becoming larger.
[0014]
An object of the present invention is to eliminate the above-mentioned problems and to provide an optical semiconductor element excellent in high frequency characteristics and a method for manufacturing the same, by reducing series resistance, inductance, and parasitic capacitance connected to the element as much as possible.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides
In the optical semiconductor device having (1) ridge, and having a shape larger than the width of the electrode width is the ridge top surface of the ohmic electrode with ohmic electrodes of the ridge upper face side is full contact with the upper surface of the ridge-side The ohmic electrode on the upper surface side of the ridge has a shape that is drawn out to the pad portion outside the ridge at the same time in the form of an air bridge .
[0016]
[ 2 ] In a method of manufacturing an optical semiconductor device having a ridge shape, a step of obtaining a ridge-type waveguide shape, a step of forming a resist so as to cover the ridge-type waveguide shape, and ashing the entire semiconductor substrate And a step of obtaining a resist pattern in which the top surface of the ridge-type waveguide shape is exposed, and a step of forming a new resist pattern having an opening width larger than the ridge-type waveguide shape. A wiring having a shape in which an ohmic electrode and an ohmic electrode on the ridge upper surface side are simultaneously drawn out in an air bridge shape to a pad portion outside the ridge by a wiring metal that is in ohmic contact with the top surface of the ridge-type waveguide shape. And a forming step.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail.
[0018]
FIG. 1 is a front sectional view of a semiconductor light receiving element showing an embodiment of the present invention, FIG. 2 is a side sectional view of the semiconductor light receiving element, and FIG. 3 is a manufacturing process sectional view of the semiconductor light receiving element showing an embodiment of the present invention. . 3 is a front sectional view, and the right column is a side sectional view.
[0019]
As shown in FIGS. 1 and 2, the semiconductor light receiving device of this embodiment has an n-type InP ohmic layer 22, an n-type InGaAsP cladding layer 23, a non-doped InGaAs light absorbing layer 24, on a semi-insulating InP substrate 21. It has a ridge-type waveguide shape composed of a p-type InGaAsP cladding layer 25 and a p-type InP ohmic layer 26, and ohmic electrodes 32 are formed on both sides of the ridge-type waveguide shape, and an n-type InP ohmic layer 22 is connected.
[0020]
Furthermore, an ohmic electrode 35 having a width wider than that of the p-type InP ohmic layer 26 is formed on the top of the ridge-type waveguide shape. Further, as shown in FIG. 2, the ohmic electrode 35 is connected to a pad portion 37 on the semi-insulating InP substrate 21 by a wiring 36 that is integrally connected to the ohmic electrode 35. Reference numeral 38 denotes a cleavage plane on which the incident light 39 is incident.
[0021]
A method for manufacturing the semiconductor light receiving element of this embodiment will be described below with reference to FIG.
[0022]
(1) As in the conventional process, first, as shown in FIG. 3A, an n-type InP ohmic layer 22, an n-type InGaAsP cladding layer 23, a non-doped layer are formed on a semi-insulating InP substrate 21 by crystal growth. After sequentially depositing the InGaAs light absorbing layer 24, the p-type InGaAsP cladding layer 25, and the p-type InP ohmic layer 26, a mask pattern 27 is formed by photolithography.
[0023]
(2) Next, as shown in FIG. 3B, the p-type InP ohmic layer 26, the p-type InGaAsP cladding layer 25, the non-doped InGaAs light absorption layer 24, and the n-type InGaAsP cladding layer 23 are sequentially formed by the mask pattern 27. Etching is performed to obtain a ridge-type waveguide shape 29. Similarly, after patterning the n-type InP ohmic layer 22 by photolithography and etching to form the n-type ohmic region 30, an insulating film 31 is deposited on the entire device front surface.
[0024]
(3) Next, as shown in FIG. 3C, after forming the ohmic electrode 32 for the n-type ohmic region 30, a resist pattern 33 is formed so as to include the ridge-type waveguide shape 29. Here, the resist pattern 33 has the same effect even when a normal resist material or a resin such as polyimide is used. Further, when a liquid resin material is applied on the unevenness, the liquid resin material is thinly deposited on the convex portion due to its viscosity, so that it is particularly thin on the top surface of the ridge-type waveguide shape 29.
[0025]
(4) Next, as shown in FIG. 3D, the entire semiconductor substrate is ashed (resin ashing by oxygen plasma) to remove the resist 33, and the top surface of the ridge-type waveguide shape 29 is formed. A resist pattern 33 'is exposed. Next, a new resist pattern 34 having an opening width larger than the ridge-type waveguide shape 29 is formed.
[0026]
(5) Next, as shown in FIG. 3 (e), the ohmic electrode 35 and the ohmic electrode 35 are formed by vapor deposition / lift-off of a wiring metal (for example, Ti / Pt / Au structure) in ohmic contact with the p-type InP ohmic layer 26. A wiring 36 to be connected is formed. In this step, the wiring metal may be deposited after the insulating film 31 is etched after the wiring photolithography. Here, as can be seen from the front sectional view of FIG. 3 (e), the electrode width of the ohmic electrode 35 is widely formed so as to include the ridge-type waveguide shape 29, and the ohmic electrode 35 of FIG. 3 (e). As can be seen from the side sectional view, the ridge-type waveguide shape 29 is formed so as to be connected to the pad portion 37 on the semi-insulating InP substrate 21 from the top surface.
[0027]
Finally, as shown in FIG. 3 (f), the resist pattern 33 'is removed and then cleaved to obtain a waveguide type light receiving element. Here, the resist pattern 33 may be made of a resin material such as polyimide and may not be finally removed, and at this time, the pad portion 37 may be formed on the polyimide.
[0028]
As described above, according to the present embodiment, as shown in FIG. 3C, the entire top of the ridge-type waveguide shape 29 and the wiring metal can be in ohmic contact without using precise mask alignment of photolithography. Therefore, the contact resistance can be greatly reduced with good reproducibility. In addition, since the wiring resist pattern 34 is formed on the resist pattern 33 ′, the electrode width of the ohmic electrode 35 at the top of the ridge-type waveguide shape 29 is set to the width of the top of the ridge-type waveguide shape 29. There is an advantage that it can be made larger than the width and the conductance of the wiring 36 can be reduced.
[0029]
Furthermore, since the ohmic electrode 35 at the top of the ridge-type waveguide shape 29 can be formed on the overhang, it does not contact the side surface of the ridge-type waveguide shape 29, that is, between the upper wiring and the semiconductor element. There is no risk of increasing the parasitic capacitance. Further, since the wiring in this embodiment is formed integrally with the ohmic electrode 35, the process can be simplified.
[0030]
As described above, according to the present embodiment, there is an advantage that a semiconductor light-receiving element having excellent high-frequency characteristics can be easily manufactured with high reproducibility such that series resistance and wiring inductance are small without increasing parasitic capacitance.
[0031]
The present invention has the following usage forms.
[0032]
In the above embodiment, the waveguide type light receiving element in which light is incident from the crystal side surface has been described. However, the present invention relates to a waveguide type optical semiconductor element, and has an ohmic electrode on the upper surface side that is simple and highly reproducible. It is formed with low contact resistance and low inductance, and at the same time, the wiring can be drawn out to the pad portion. That is, it goes without saying that the present invention can be applied not only to a light receiving element but also to an optical semiconductor element such as a waveguide type laser diode or an optical modulator operating at a high frequency.
[0033]
In addition, this invention is not limited to the said Example, A various deformation | transformation is possible based on the meaning of this invention, and these are not excluded from the scope of the present invention.
[0034]
【The invention's effect】
As described above in detail, according to the present invention, the following effects can be obtained.
[0035]
(1) According to the first aspect of the present invention, an optical semiconductor element having excellent high-frequency characteristics is provided while reducing the series resistance, inductance, and parasitic capacitance connected to the element as much as possible , and at the same time, the wiring is drawn out to the pad portion. be able to.
[0036]
(2) According to the second aspect of the present invention, a semiconductor light receiving element having a small series resistance and a small wiring inductance and excellent in high frequency characteristics can be manufactured easily and with high reproducibility without increasing the parasitic capacitance.
[Brief description of the drawings]
FIG. 1 is a front sectional view of a semiconductor light receiving element according to an embodiment of the present invention.
FIG. 2 is a side sectional view of a semiconductor light receiving element showing an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a manufacturing process of a semiconductor light receiving element showing an embodiment of the present invention.
FIG. 4 is a manufacturing process cross-sectional view of a conventional semiconductor light receiving element.
[Explanation of symbols]
21 Semi-insulating InP substrate 22 n-type InP ohmic layer 23 n-type InGaAsP clad layer 24 non-doped InGaAs light absorption layer 25 p-type InGaAsP clad layer 26 p-type InP ohmic layer 27 mask pattern 29 ridge-type waveguide shape 30 n-type Ohmic region 31 Insulating film 32, 35 Ohmic electrode 33, 33 ', 34 Resist pattern 36 Wiring 37 Pad part 38 Cleaved surface 39 Incident light

Claims (2)

リッジ形状を有する光半導体素子において、
リッジ上面側のオーミック性電極が該リッジ上面側と完全に接触するとともに前記オーミック性電極の電極幅が前記リッジ上面の幅よりも大きい形状を有するとともに、該リッジ上面側のオーミック性電極が同時にリッジ外部のパッド部にまでエアーブリッジ状に引き出される形状を有することを特徴とする光半導体素子。
In an optical semiconductor element having a ridge shape,
The ohmic electrode on the upper surface side of the ridge is in complete contact with the upper surface side of the ridge, and the electrode width of the ohmic electrode is larger than the width of the upper surface of the ridge. An optical semiconductor element having a shape that is drawn out in an air bridge shape to an external pad portion .
リッジ形状を有する光半導体素子の製造方法において、
(a)リッジ型の導波路形状を得る工程と、
(b)該リッジ型の導波路形状を覆うようにレジストを形成する工程と、
(c)半導体基板全体をアッシングして前記レジストを膜べりさせ、前記リッジ型の導波路形状の頂面上が露出したレジストパターンを得る工程と、
(d)開口幅が前記リッジ型の導波路形状より大きい新たなレジストパターンを形成する工程と、
(e)前記リッジ型の導波路形状の頂面とオーミック接触する配線金属によってオーミック性電極及び前記リッジ上面側のオーミック性電極が同時にリッジ外部のパッド部にまでエアーブリッジ状に引き出される形状を有する配線を形成する工程とを施すことを特徴とする光半導体素子の製造方法。
In the method of manufacturing an optical semiconductor element having a ridge shape,
(A) obtaining a ridge-type waveguide shape;
(B) forming a resist so as to cover the ridge-type waveguide shape;
(C) ashing the entire semiconductor substrate to remove the resist, and obtaining a resist pattern in which the top surface of the ridge-type waveguide shape is exposed;
(D) forming a new resist pattern having an opening width larger than that of the ridge-type waveguide;
(E) The wiring metal in ohmic contact with the top surface of the ridge-type waveguide shape has a shape in which the ohmic electrode and the ohmic electrode on the ridge upper surface side are simultaneously drawn out in an air bridge shape to the pad portion outside the ridge. And a step of forming a wiring.
JP24370597A 1997-09-09 1997-09-09 Optical semiconductor device and manufacturing method thereof Expired - Lifetime JP3623638B2 (en)

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