JP3623727B2 - Communication method - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a technology for improving information communication performance in a network configured by connecting information processing systems such as computer systems.
[0002]
In particular, the present invention relates to a technique for speeding up information communication processing in a network connected with an information processing system such as a computer system having a virtual memory.
[0003]
[Prior art]
A configuration example of an information processing system constituting a conventional network is shown in FIG.
[0004]
Here, the configuration of the intra-network computer 200 will be described as an example of an information processing system that configures a network.
[0005]
The intra-network computer 200 includes a processor 230, a memory 250, and a network adapter 210, and each component is connected to a system bus 280.
[0006]
The network adapter 210 further includes a DMA control unit 220, a transmission / reception buffer 221, a network transmission / reception unit 218, a reception DMA control information holding unit 211, a transmission DMA control information holding unit 212, an interrupt control information holding unit 213, and an adapter control information holding unit. Means 214 and adapter control means 215 are provided, which are connected by an internal bus 222.
[0007]
The DMA control unit 220 includes a transmission / reception buffer 221 based on information held in the reception DMA control information holding unit 211, the transmission DMA control information holding unit 212, the interrupt control information holding unit 213, and the adapter control information holding unit 214. It is a means for controlling data transfer to and from the memory 250, and can be realized by an electronic device such as TTL or CMOS.
[0008]
The transmission / reception buffer 221 is means for storing and holding a packet transmitted via the network 290 and a packet received via the network 290, and can be realized by a RAM or the like, for example.
[0009]
The network transmission / reception unit 218 is means for performing data communication between the network 290 and the transmission / reception buffer 221 and can be realized by, for example, various electronic devices such as TTL and CMOS.
[0010]
The reception DMA control information holding unit 211 is a unit that holds information related to control performed when data is transferred from the transmission / reception buffer 221 to the memory 250, and can be realized by, for example, an electronic device such as a RAM, various TTLs, and various CMOSs. .
[0011]
The transmission DMA control information holding unit 212 is a unit that holds information related to control performed when data is transferred from the memory 250 to the transmission / reception buffer 221. For example, the transmission DMA control information holding unit 212 is realized by an electronic device such as a RAM, various TTLs, and various CMOSs. it can.
[0012]
The interrupt control information holding unit 213 is used when issuing an interrupt at the end of the data transfer process between the transmission / reception buffer 221 and the memory 250 or at the end of a predetermined operation. A means for holding information, and can be realized by an electronic device such as a RAM.
[0013]
The adapter control information holding unit 214 is a unit that holds various control information used when the network adapter 200 operates, and can be realized by an electronic device such as a RAM, various TTLs, various CMOSs, for example.
[0014]
The adapter control means 215 is means for controlling the processor 230 to start and stop the operation of the network adapter 200, and can be realized by an electronic device such as RAM, various TTLs, various CMOSs, for example.
[0015]
The network transmission / reception unit 218 includes a self address holding unit 219 therein. The own address holding means 219 is a means for holding the own address so that the network transmission / reception unit 218 monitors a packet communicated via the network 290 and determines whether the packet is a packet addressed to the own computer. For example, it can be realized by an electronic device such as a RAM, various TTLs, and various CMOSs.
[0016]
Hereinafter, a processing procedure of reception processing in data communication using the conventional system as described above will be described.
[0017]
First, the network adapter 210 determines whether or not the transfer destination of a packet transmitted via the network 290 is its own computer.
[0018]
Next, when it is determined that the packet transfer destination is the local computer, the network adapter 210 takes the packet transmitted via the network into the transmission / reception buffer 221.
[0019]
Further, the DMA control unit 220 means DMA processing (abbreviation of “Direct Memory Access”: direct access to memory to perform input / output processing based on information held by the reception DMA control information holding unit 211, The captured packet is transferred to the received packet area 263 existing in the OS (operating system) space.
[0020]
Next, the network adapter 210 instructs the processor 230 to interrupt according to the content of the information held by the interrupt control information holding unit 213 after the data transfer processing by the DMA processing is completed.
[0021]
The processor 230 instructed to interrupt checks the user data 271 and the like existing in the user space to which the data is to be transferred based on the information in the packet existing in the reception packet area 263 existing in the OS space. A series of processes for transferring data to the application is performed by performing the process of copying the.
[0022]
Also, in the study of high-speed communication mechanisms, the effect of message communication on the performance of distributed memory parallel computers in the "Parallel Processing Symposium JSPP'93" in May 1993-Effects of communication and computation overlap and direct message reception In this announcement, a direct message communication means has been proposed, and it is conceivable to add a reception address to the message header. In this means, it is determined whether the received message can be transferred to the user area. And a means for detecting the address of the received message on the transmission side.
[0023]
[Problems to be solved by the invention]
In order to directly specify the address on the receiving side, it is essential for the transmitting side to know the address on the receiving side, but in order to do this, a predetermined notification is separately made prior to transmission and reception. There is a need. In the conventional method, since this is realized by performing communication in advance, the communication processing overhead cannot be reduced.
[0024]
In other words, until the transfer processing of the received packet to the memory is completed by hardware, the address of the application and the data area to which the data of the received packet is transferred cannot be specified.
[0025]
For this reason, a received packet must be received once by a reception buffer existing in the OS space, and then a process of transferring data to a target application by a data copy process or the like is required.
[0026]
In such data copy processing, the processing amount increases in proportion to the data amount. At present, since the ratio of the data copy process in the data communication process is high, it is a big problem in performing the high-speed data communication process.
[0027]
The present inventionThe purpose ofTechnology for improving information communication performance in networks configured by connecting information processing systems such as computer systemsTo provideIt is in.
[0030]
[Means for Solving the Problems]
The present invention operates while performing data communication via a network configured by connecting at least two computers including at least two arithmetic processing units, a main storage unit, and a network interface via respective network interfaces. A communication method in a computer system that includes:
Prior to data transfer, a reception area is pre-assigned to the main memory of the receiving computer, and an identifier for designating the pre-assigned reception area is added when transmitting via the network,
The receiving computer has information indicating the correspondence between the pre-assigned receiving area and the added identifier, and the correspondence between the receiving area and the identifier is received in the receiving computer for data transferred via the network. In this case, a pre-assigned receiving area as a receiving destination is specified, and data is transferred to the receiving area.
[0031]
That is,In the present invention, the current communication (TCP / IP etc ) In the same way as the above, the virtual line identifier used on the receiving side and the transmitting side is set, the transmitting side designates the identifier and transmits, and the receiving side receives the receiving area corresponding to the identifier. I want to send data directly without generating extra communication processing by converting the address to the address of the receiving area based on the identifier in hardware and then transferring the data. Data is sent to the area.
[0032]
Further, in the information processing system on the transmission side, communication in the network is further described in a specific area of the header part for each piece of data to be divided, indicating information that designates a transfer destination in the information processing system on the reception side. A method is also preferred.
[0033]
[Action]
In the present invention, the packet to be transmitted / received is configured to include information for dividing the packet and reception area designation information which is information indicating an area where the packet is to be received.
[0034]
Then, the information processing apparatus on the receiving side that configures the network, after receiving the packet, divides the packet based on information for dividing the packet, and the reception area existing on the memory included in the information processing apparatus Corresponding to the designation information, in order to designate a reception area, a conversion table provided in advance on the receiving side apparatus is referred to.
[0035]
By referring to the conversion table, the reception area of the data in the packet is determined, and the data in the packet is transferred to the reception area by DMA processing or the like.
[0036]
As described above, according to the present invention, a means having a high-speed data communication function capable of realizing communication between application processes communicating via a network without requiring data copy processing by a processor on the receiving side is inexpensive. Can be provided.
[0037]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
[0038]
FIG. 1 shows a configuration example of a computer in a network that is an example of an information processing system according to the present invention that constitutes a network.
[0039]
The network 190 configured with the intra-network computer 100 is usually configured to include at least two intra-network computers 100.
[0040]
Hereinafter, the configuration of the intra-network computer 100 will be described.
[0041]
The intra-network computer 100 includes a processor 130, a memory 150, and a network adapter 110, and these components are connected via a system bus 180.
[0042]
Further, depending on the system configuration of the intra-network computer 100, it is preferable to provide at least one I / O device 140.
[0043]
The network adapter 110 includes a multi-queue DMA control unit 120, a transmission / reception buffer 121, a network transmission / reception unit 118, a reception DMA control information holding unit 111, a transmission DMA control information holding unit 112, and interrupt control information. The holding unit 113, the adapter control information holding unit 114, the adapter control unit 115, the reception DMA control information selection unit 116, and the DMA division information holding unit 117 are configured. Connected through.
[0044]
The multi-queue DMA control unit 120 includes information held in the reception DMA control information holding unit 111, adapter control information holding unit 114, and reception DMA control information selection unit 116, information included in a packet received from the network, memory 150, data transfer processing (processing at the time of reception) from the transmission / reception buffer 121 to the memory 150 based on the information of the reception region designation information selection information 167 and the reception region designation information (164 to 165) held in 150, Further, from the memory 150 based on the information held in the transmission DMA control information holding means 112, the interrupt control information holding means 113, and the adapter control information holding means 114 and the transmission area designation information (166) of the memory 150. A means for performing data transfer processing (transmission processing) to the transmission / reception buffer 121 Ri, for example, various types of TTL, can be implemented by an electronic device such as CMOS.
[0045]
The transmission / reception buffer 121 is means for holding packets transmitted via the network 190 and packets received via the network 190, and can be realized by an electronic device such as a RAM, for example.
[0046]
The network transmission / reception unit 118 is means for performing data communication between the network 190 and the transmission / reception buffer 121, and can be realized by, for example, various electronic devices such as TTL and CMOS.
[0047]
The reception DMA control information holding unit 111 is a unit that holds information related to control performed when data is transferred from the transmission / reception buffer 121 to the memory 150, and can be realized by an electronic device such as a RAM, various TTLs, and CMOSs, for example. .
[0048]
The transmission DMA control information holding unit 112 is a unit that holds information related to control performed when data is transferred from the memory 150 to the transmission / reception buffer 121, and can be realized by an electronic device such as a RAM, various TTLs, and CMOSs, for example. .
[0049]
The interrupt control information holding unit 113 stores information used when issuing an interrupt at the end of the data transfer process between the transmission / reception buffer 121 and the memory 150 and at the end of a predetermined operation. It is a means to hold | maintain and can be implement | achieved by electronic devices, such as RAM, various TTL, CMOS, for example.
[0050]
The adapter control information holding unit 114 is a unit that holds control information used when the network adapter 110 operates, and can be realized by an electronic device such as a RAM, various TTLs, and CMOSs, for example.
[0051]
The adapter control unit 115 is a unit for causing the processor 130 to notify the network adapter 110 of control information or the like when data transfer control is performed on a transmission / reception packet by DMA processing. Can be realized.
[0052]
The network transmission / reception unit 118 outputs the contents of the transmission / reception buffer 121 to the network 190, monitors the communication packet on the network 190, and takes in the packet including its own address into the transmission / reception buffer 121 (this process) Is carried out by the following own address holding means 119), and can be realized by various electronic devices such as TTL and CMOS, for example. The own address holding unit 119 provided in the network transmission / reception unit 118 can be realized by an electronic device such as a RAM, for example.
[0053]
The transmission / reception buffer 121 can be realized by an electronic device such as a RAM. The processor 130 can be realized by a CPU (Central Processing Unit), for example, and the memory 150 can be realized by a RAM, for example.
[0054]
Next, the structure of data stored in the memory 150 will be described.
[0055]
The data structure stored in the memory 150 considers the data structure related to the reception process and the data structure related to the transmission process.
[0056]
Data structures related to the reception process include reception area designation information selection information 167, reception area designation information (164 to 165), reception protocol information (161 to 162), and user data (171 to 172).
[0057]
User data (171 to 172) is information stored in an area secured by the receiving side as an area for receiving data.
[0058]
The reception protocol information (161 to 162) is information stored in an area for transferring protocol information necessary for communication.
[0059]
The protocol information necessary for communication is, for example, information for specifying a process to be received.
[0060]
The reception area designation information (164 to 165) is control information for transferring a packet (during reception), for example, user data (171 to 172), address information of reception protocol information (161 to 162), etc. It is. The reception area designation information (164 to 165) may hold information indicating a plurality of user data.
[0061]
The reception area designation information selection information 167 existing in the memory 150 of FIG. 1 is based on the information indicated by the reception area designation information 312-b of the network packet, which will be described later. 165) is stored, and the data structure is in the form of a table.
[0062]
The data related to the transmission process is, for example, transmission protocol information (163), user data (173), etc. for the transmission area designation information (166).
[0063]
User data (173) is data stored in the data area transmitted by the transmission side. Transmission protocol information (163) is information stored in an area for transferring protocol information necessary for communication. The protocol information necessary for communication is, for example, information for specifying a receiving process.
[0064]
The transmission area designation information (166) is control information necessary for transferring a packet (when transmitting), and is, for example, address information and size information of user data (173) and transmission protocol information (163). The transmission area designation information (166) may hold information indicating a plurality of user data.
[0065]
The reception area designation information (164 to 165) is information for designating the transfer destination area of the reception protocol information (161 to 162) and user data (171 to 172). For example, the address, data size, etc. in the memory 150 are set. Have.
[0066]
The transmission area designation information 166 is information for designating the transmission protocol information 163 and the user data 173, and has, for example, an address in the memory 150, a data size, and the like.
[0067]
Here, a plurality of transmission protocol information 163 and user data 173 may be provided as in the reception processing side.
[0068]
In this embodiment, user data (171 to 172) and user data (173) exist in the user space 170 in the memory 150. On the other hand, reception area designation information selection information 167, reception protocol information (161 to 162), reception area designation information (164 to 165), transmission area designation information (166), and transmission protocol information 163 are stored in the OS space 160. Exists.
[0069]
Next, referring to FIG. 3, a configuration of a network packet, which is a packet transmitted and received on the network, is shown.
[0070]
A conventional network packet has, for example, data 310-a, type 320-a, transmission source address 321-a, and reception destination address 322-a.
[0071]
The data 310-a is information to be processed by the OS and software.
[0072]
The type 320-a is information necessary for the network adapter 110 to perform a predetermined process, for example, information such as the length of the entire data.
[0073]
The transmission source address 321-a is an identifier for identifying the computer in the network that has transmitted the packet. Further, the receiving address 322-a is an identifier for identifying a computer in the network that should receive the packet.
[0074]
The network packet according to the present invention includes data 310-b, division information 311-b, reception area designation information 312-b, type 320-b, transmission source address 321-b, and reception destination address 322-b. Is done.
[0075]
Data 310-b, type 320-b, source address 321-b, and destination address 322-b are data 310-a, type 320-a, source address 321-a, and destination address 322-a, respectively. It corresponds to.
[0076]
Here, the data 310-b includes, as the receiving side, from the above reception protocol information (161 to 162), reception area designation information 312-b, type 320-b, transmission source address 321-b, and reception destination. This information includes information excluding information corresponding to the address 322-b and user data (171 to 172).
[0077]
Alternatively, the data 310-b includes, from the transmission protocol information (163), the reception area designation information 312-b, type 320-b, transmission source address 321-b, and reception destination address 322. This is information configured to include information excluding information corresponding to b and user data (173).
[0078]
The division information 311-b is information indicating, for example, the number of packet divisions and the length at the time of division. Here, it goes without saying that the division information may include information for dividing the information into three or more. In addition, when a packet is divided, which part of the divided part corresponds to the reception protocol information (161 to 162) and the transmission protocol information (163), and which part is the user data (from 171 173) may be included. In addition, when the packet is divided into three or more, it is preferable to provide information indicating which divided portion of the divided portion corresponds to which portion of the user data.
[0079]
The reception area designation information 312-b is information for selecting reception area designation information indicating a transfer destination of the data when the packet data is transferred to the memory 150.
[0080]
The outline of packet transmission processing and reception processing will be described below.
[0081]
The packet transmission process is a process of creating a network packet according to the present invention with reference to FIG. 3 using the user data A173 and the transmission protocol information 163 and outputting the packet to the network.
[0082]
Hereinafter, software processing during transmission and operation of the network adapter 110 will be described.
[0083]
First, processing by software performed at the time of packet transmission processing will be described with reference to FIG.
[0084]
User data A173 holds user data to be transmitted.
[0085]
First, as shown in step 410, in the transmission protocol information 163, reception area designation information 312-b, type 320-b, transmission source address 321-b, and reception destination address 322-b are set.
[0086]
Here, as described above, the reception area designation information 312-b is an identifier for designating a reception area on the reception side. The type 320-b is information indicating, for example, the type of the upper protocol. The transmission source address 321-b is an identifier in the network of the own computer, and the reception destination address 322-b is an identifier in the network of the reception destination computer.
[0087]
Next, as shown in step 420, information specifying the user data A 173 and the transmission protocol information area 163 is set in the transmission area specifying information 166.
[0088]
Examples of information to be set include an address in the memory 170 and a data length. Here, in the information set in the transmission area designation information 166, a network packet is configured with the data length and the number of area designations as the division information 311-b.
[0089]
Next, as shown in step 430, the information of the transmission area designation information 166 is set in the transmission DMA control information holding unit 112.
[0090]
Information set in the transmission DMA control information holding unit 112 is an address of the area in the memory 170.
[0091]
Finally, as shown in step 440, an operation start notification is sent to the adapter control means 115. The transmission process is completed by the series of processes described above.
[0092]
Next, the operation of the network adapter 110 during transmission processing will be described with reference to FIG. The operation after the start of the operation by the operation start notification to the adapter control unit 115 will be described.
[0093]
First, as shown in step 510, the multi-queue DMA control unit 120 reads the content of the transmission area designation information 166 based on the information held in the transmission DMA control information holding means 112, and converts the content into the DMA. The division information holding unit 117 is set.
[0094]
Next, as shown in step 520, the multi-queue DMA control unit 120 holds the user data A 173 and transmission protocol information 163 according to the contents of the transmission area designation information 166 held in the DMA division information holding unit 117. The read information is read into the transmission / reception buffer 121.
[0095]
Next, as shown in step 530, the multi-queue DMA control unit 120 determines the data length and the number of area designations from the contents of the transmission area designation information 166 held in the DMA division information holding means 117 as “division information”. "311-b" is taken out for use.
[0096]
Next, as shown in step 540, the multi-queue DMA control unit 120 receives the user data A173, the reception area designation information 312-b, the type 320-b, the transmission source address 321-held in the transmission protocol information 163. b, information other than the destination address 322-b, constitutes data 310-b, and further includes reception area designation information 312-b, type 320-b, and source address 321 held in the transmission protocol information 163. The network packet according to the present invention is created and stored in the transmission / reception buffer 121 using -b and the destination address 322-b.
[0097]
Finally, as shown in step 550, the created network packet is output from the network transmission / reception unit 118 via the internal bus 122.
[0098]
Next, packet reception processing will be described.
[0099]
In the reception process, by using the network packet fetched from the network 190, only the data portion included in the packet is directly transferred to a predetermined user data storage area existing in the user space by the hardware process. The data can be transferred to the application program without performing the data copy process.
[0100]
The contents of the reception process will be described below.
[0101]
By the way, the reception processing is roughly divided into reception software preprocessing that is processing performed before arrival of data by the software, processing performed by the network adapter 110 when data arrives, and processing performed after data arrives by software. There is reception software post-processing that is processing.
[0102]
First, reception software preprocessing will be described.
[0103]
The reception software pre-process is a process for setting information in the reception area designation information selection information 167 and the reception area designation information (164 to 165) and notifying the network adapter 110 of the setting process.
[0104]
First, as shown in step 610, interrupt information related to an interrupt to be issued to the processor 130 at the end of data reception is set in the interrupt control information holding means 113.
[0105]
Next, as shown in step 620, how the reception area designation information 312-b in the network packet is associated with the reception area designation information (164 to 165) in the reception area designation information selection information 167. Determine and set the process.
[0106]
For example, the reception area designation information selection information 167 may adopt a configuration having a table-like data structure that can read the address of the reception area designation information based on the reception area designation information 312-b.
[0107]
Next, as shown in step 630, the information included in the user data (171 to 172) and the reception protocol information (161 to 162) is set in the reception area designation information (164 to 165). This information includes, for example, addresses of user data (171 to 172) and reception protocol information (161 to 162), data size, and the like.
[0108]
Finally, as shown in step 640, information indicated by the reception area designation information selection information 167 is set in the reception DMA control information holding unit 111.
[0109]
Next, the operation of the network adapter 110 from taking in network packets until receiving data will be described.
[0110]
First, as shown in step 710, the network transmission / reception unit 118 in the network adapter 110 monitors the network 190 and captures a network packet communicated on the network 190.
[0111]
Next, as shown in step 720, when the contents of the destination address 322-b of the network packet are equal to the contents held in advance in the own address holding means 119, branch to step 740, and if not equal Branch to step 730.
[0112]
In step 730, the captured network packet is discarded and the process is terminated.
[0113]
On the other hand, in step 740, the network packet is taken into the transmission / reception buffer 121.
[0114]
Next, as shown in step 750, the multi-queue DMA control unit 120 sets the content of the reception area designation information 312-b in the network packet in the reception DMA control information selection unit 116.
[0115]
Next, as shown in step 760, the multi-queue DMA control unit 120 uses a plurality of reception area designation information (164) based on the contents of the reception DMA control information holding means 111 and the contents of the reception DMA control information selection means 116. To 165) is selected.
[0116]
That is, this is a process of identifying one of the reception area designation information (164 to 165) by referring to the table of the reception area designation information selection information 167 according to the contents of the reception area designation information 312-b. It is.
[0117]
Next, as shown in step 770, the multi-queue DMA control unit 120 acquires address information from the selected reception area designation information (164 to 165).
[0118]
Next, as shown in step 780, the multi-queue DMA control unit 120 acquires the division information 311-b using the network packet taken into the transmission / reception buffer 121.
[0119]
Next, as shown in step 785, the multi-queue DMA control unit 120 performs processing for dividing the data portion of the network packet taken into the transmission / reception buffer 121 based on the division information 311-b.
[0120]
That is, of the division number and division length information held in the division information and the division portion of the packet data, which division portion corresponds to the reception protocol information (161 to 162) and which division portion is the user. The network packet data 310-b is divided into reception protocol information and user data from information indicating whether the data corresponds to the data (171 to 172).
[0121]
Next, as shown in step 790, the divided packet is separated into user data and reception protocol information based on the information of the reception area designation information specified in step 770 (for example, the address value in the memory 150). Then, the data is transferred to each transfer destination area.
[0122]
Finally, as shown in step 795, an interrupt is issued to the processor 130 according to the contents of the interrupt control information holding unit 113.
[0123]
Next, reception software post-processing performed after data arrival will be described.
[0124]
The reception software post-processing is started by an interrupt issued after a network packet is divided into user data and reception protocol information by hardware and transferred.
[0125]
First, as shown in step 810, when an interrupt is issued, the processor 130 specifies an application that has received data in accordance with information included in the reception protocol control information.
[0126]
Next, as shown in step 820, if the application that has received the data is in a waiting state after issuing a data reception request, it branches to step 830; otherwise, it branches to step 840. To do.
[0127]
In step 830, the reception request is made to activate the blocked application. On the other hand, in step 840, if the application receiving the data is not in a waiting state after issuing the data reception request, the status is notified so that the data can be delivered immediately when the reception request is issued. Set the flag to In such a case, a data delivery process is performed when a reception request is issued from the reception application.
[0128]
Next, in order to clarify the operation of the reception process, the operation as viewed from the application program that issued the reception request will be described with reference to FIG.
[0129]
First, as shown in step 910, reception buffer allocation processing is performed. This activates the processing described in FIG.
[0130]
Next, as shown in step 920, a reception request is issued. The reception request issuance process is a prerequisite that the reception buffer allocation process in step 910 is performed in advance, but it is not a necessary condition to issue a reception request immediately after the reception buffer allocation process.
[0131]
Here, in order to describe the flow of the reception process in the simplest manner, only the reception-related process is described. However, a predetermined process may exist between Step 910 and Step 920.
[0132]
Next, according to step 930, if the arrival of the reception data precedes the reception request, the process branches to step 960. Otherwise, the process branches to step 940.
[0133]
In step 960, since the flag indicating data arrival described in FIG. 8 is set, it is only necessary to receive data.
[0134]
In step 950, since data has not yet arrived, the process waits until the reception request process described with reference to FIG. 8 starts. The return processing from such a state is performed by the method described with reference to FIG.
[0135]
Embodiments according to the present invention will be described below in more detail with reference to the drawings.
[0136]
FIG. 10 shows a configuration example of an intra-network computer node 1101 (each of a plurality of computers is hereinafter referred to as a “node”), which is an example of an information processing apparatus according to the present invention that constitutes a network system. .
[0137]
The network configured with the intra-network computer node 1101 is configured by connecting at least two computer nodes 1101 shown in FIG.
[0138]
The network 1105 is a means for transmitting information such as packets, and may be configured using, for example, an electric cable or an optical fiber.
[0139]
Hereinafter, the configuration of the intra-network computer node 1101, which is an example of an information processing apparatus configuring the network, will be described with reference to the drawings.
[0140]
The intra-network computer node 1101 in this embodiment is configured to include a processor 1102, a memory 1103, and a network adapter 1110, and each component is connected via a system bus 1104.
[0141]
The network adapter 1110 includes a multi-queue DMA control unit 1111, a reception buffer 1112, a transmission buffer 1113, a network reception unit 1114, and a network transmission unit 1115.
[0142]
The computer node 1101 is preferably configured to include at least one or more I / O devices (not shown) depending on the system configuration.
[0143]
The multi-queue DMA control unit 1111, the network transmission unit 1115, and the network reception unit 1114 can be realized by various electronic devices such as TTL and CMOS, for example.
[0144]
The transmission buffer 113 and the reception buffer 112 can be realized by an electronic device such as a RAM, for example. Furthermore, the processor 1102 can be realized by a CPU, for example, and the memory 1103 can be realized by an electronic device such as a RAM, for example.
[0145]
FIG. 11 shows a configuration example of the multi-queue DMA control unit.
[0146]
The multi-queue DMA control unit includes a multi-queue control register group 1201 and a DMA control unit 1202. The multi-queue DMA control unit is connected to a system bus, a reception buffer, and a transmission buffer. ing.
[0147]
Multiqueue control register group 1201, ADP_COMMAND1211, ADP_STATUS1212, SEND_Q_ADR1221, SEND_Q_LEN1222, SEND_Q_HEAD1223, SEND_Q_TAIL1224, RECV_Q_TBL_ADR1231, RECV_Q_TBL_LEN1232, RECV_PORT_NO1233, RECV_Q_ADR1241, RECV_Q_LEN1242, RECV_Q_HEAD1243, configured with a respective registers RECV_Q_TAIL1244.
[0148]
Note that the multi-queue control register group 1201 can be realized by various electronic devices such as TTL, CMOS, and RAM, for example.
[0149]
The DMA control unit 1202 is a hard wired logic having a function of performing data transfer processing by DMA processing, and is realized by various TTL, CMOS, and the like, for example.
[0150]
ADP_COMMAND 1211 is a register for storing a command for controlling the network adapter, and ADP_STATUS 1212 is a register for holding status information for controlling the network adapter.
[0151]
SEND_Q_ADR1221, SEND_Q_LEN1222, SEND_Q_HEAD1223, and SEND_Q_TAIL1224 are storage units for various parameters having a list structure (hereinafter referred to as “command queue”) for processing a transmission command, and will be described later with reference to FIG. To do.
[0152]
RECV_Q_TBL_ADR1231 is a pointer indicating the address of the command queue selection table, RECV_Q_TBL_LEN1232 is the size of the command queue selection table, and RECV_PORT_NO1233 is a register for temporarily storing DMA_PORT_NO present in the header of the received packet. is there.
[0153]
The command queue selection table will be described with reference to FIGS. 13 and 14. Further, “DMA_PORT_NO” will be described with reference to FIG.
[0154]
RECV_Q_ADR 1241, RECV_Q_LEN 1242, RECV_Q_HEAD 1243, and RECV_Q_TAIL 1244 are parameter storage units for the reception command queue, and will be described later with reference to FIG.
[0155]
Next, FIG. 12 shows a data format of a packet communicated via the network.
[0156]
The packet data includes DATA_LENGTH 1301, HEADER_LENGTH 1302, DMA_PORT_NO 1303, SRC_NODE_NO 1304, DST_NODE_NO 1305, MODE 1306, and SOFT_HEADER 1311, and a packet data unit 13 including a SOFT_DATA 1312.
[0157]
The data length of each element constituting the hard header portion 1300 is preferably a fixed length.
[0158]
DATA_LENGTH 1301 stores information indicating the length of data composed of 1301, 1302, 1303, 1304, 1305, 1306, 1311, and 1312.
[0159]
HEADER_LENGTH 1302 indicates the length of data when the data in the packet is divided into a plurality of pieces and transferred to the storage area by DMA processing. This length is composed of 1301, 1302, 1303, 1304, 1305, 1306, and 1311. Is the length of the data to be processed.
[0160]
That is, HEADER_LENGTH 1302 is information indicating the length of the hard header portion.
[0161]
The DMA_PORT_NO 1303 is a selection process of the command queue selection table 1401 for selecting a command queue for transferring data to the main memory (not limited to the main memory) included in the receiving computer node by DMA processing. It is a parameter for performing.
[0162]
As described above, the command queue selection table 1401 will be described later.
[0163]
SRC_NODE_NO 1304 is information for identifying the computer node on the transmission side that transmits data via the network, and an address number or the like added in advance to the computer node may be used. DST_NODE_NO 1305 is information for identifying a receiving computer node that receives data via the network, and an address number or the like added to the computer node in advance may be used.
[0164]
The network reception unit 1114 shown in FIG. 10 is configured to perform packet capture processing when the content of DST_NODE_NO 1305 included in the packet matches the preset address number assigned to the own computer node, for example. It ’s fine.
[0165]
The MODE 1306 is a parameter for determining a command for executing the DMA processing, and its usage will be described in the description of the processing flow described later.
[0166]
Also, SOFT_HEADER 1311 is information used by software that performs protocol processing, and SOFT_DATA 1312 is, for example, data itself transmitted and received between applications via a network.
[0167]
Next, FIG. 13 shows an example of a data structure for subjecting received data to DMA processing. This may be stored in the memory 1103 in FIG.
[0168]
The data structure for reception DMA processing in the memory includes a command queue selection table 1401 and a port-specific command queue group 1410.
[0169]
Each entry 1401-1, 1401-2,..., 1401-N of the command queue selection table corresponds to information (described below) corresponding to the port-specific command queues 1410-1, 1410-2,. Information as shown in FIG. 14 is held.
[0170]
FIG. 14 shows the configuration of the command queue selection table 1401. This may be stored in the memory 1103.
[0171]
The head address of the table is indicated by RECV_Q_TBL_ADR1231 constituting the multi-queue control register group 1201 shown in FIG. 11, and the number of entries in the table is indicated by RECV_Q_TBL_LEN1232 constituting the multi-queue control register group 1201.
[0172]
Each entry 1401-1, 1401-2,..., 1401-N shown in FIG. 14 includes four parameters of “Q_ADR_M, Q_HEAD_M, Q_TAIL_M, Q_LEN_M” (where M = 1 to N: N is a positive integer). These are information for controlling each command queue.
[0173]
FIG. 15 shows a method for performing the predetermined control according to each of these parameters.
[0174]
Next, FIG. 15 shows a configuration example of the command queue. This is stored in the memory 1103 of FIG.
[0175]
The configuration of the command queue is basically the same on both the transmission side and the reception side.
[0176]
Q_ADR, Q_HEAD, Q_TAIL, and Q_LEN correspond one-to-one to SEND_Q_ADR221, SEND_Q_LEN222, SEND_Q_HEAD223, and SEND_Q_TAIL224 shown in FIG. 11 on the transmission side. Similarly, the reception side is shown in FIG. Further, there is a one-to-one correspondence with RECV_Q_ADR241, RECV_Q_LEN242, RECV_Q_HEAD243, and RECV_Q_TAIL244.
[0177]
Each will be described below.
[0178]
Q_ADR, Q_HEAD, Q_TAIL, and Q_LEN are information for managing the command queue.
[0179]
Q_ADR is a pointer indicating the head address of the command queue, Q_HEAD is a pointer indicating a command for performing the next DMA processing, and Q_TAIL indicates the last command currently set by the software Pointer.
[0180]
The command queue has a logical ring structure in which the head of the queue is connected to the tail of the queue.
[0181]
Q_LEN is a variable that holds command queue length information necessary to recognize the end of the command queue and wrap it back to the beginning.
[0182]
Next, commands provided in the command queue will be described.
[0183]
Each command unit includes COMMAND 1601, HEADER_POINTER 1602, HEADER_LENGTH 1603, DATA_POINTER 1604, DATA_LENGTH 1605, and RESULT_STATUS 1606.
[0184]
The COMMAND 1601 field holds information such as whether or not to issue an interrupt instruction when the DMA processing by this command is completed.
[0185]
A field of HEADER_POINTER 1602 is a field that holds a physical address of an area in which the hard header 1610 is stored.
[0186]
A field of HEADER_LENGTH 1603 is a field that holds information indicating the data length of the hard header 1610.
[0187]
The hard header 1610 includes DATA_LENGTH 1301, HEADER_LENGTH 1302, DMA_PORT_NO 1303, SRC_NODE_NO 1304, DST_NODE_NO 1305, MODE 1306, and SOFT_HEADER 1311.
[0188]
DATA_POINTER 1604 and DATA_LENGTH 1605 indicate the physical address (DATA_POINTER 1604) and length (DATA_LENGTH 1605) of the soft data area in the packet, respectively.
[0189]
In the command queue for reception, HEADER_LENGTH 1603 and DATA_LENGTH 1605 indicate the size of the storage area reserved for reception corresponding to the header portion and the data portion.
[0190]
The command has an area for setting a physical address in HEADER_POINTER 1602 and DATA_POINTER 1604 for each packet unit, and at the time of reception, by performing data transfer corresponding to this address, a virtual address is used as shown below. In this case, it is possible to perform data transfer processing in which the continuous area at the virtual address becomes a non-continuous area at the physical address.
[0191]
Acquisition of a physical address corresponding to a data area to be transmitted / received is performed by the OS. The simplest case is when the application is operating based on a physical address. In such a case, the OS sets the physical address of the data area of the application in DATA_POINTER 1604 where the upper physical address should be set. Good.
[0192]
Next, an example of a system in which the OS performs virtual memory management will be described.
[0193]
The memory 1103 is used by the OS and applications, and the program under the virtual memory management (ordinary application program) converts the address in the virtual memory into information set in the “process page table” for performing address conversion. The memory address is converted into a physical address.
[0194]
The table for converting the virtual memory address and the physical address is a process page table shown in FIG.
[0195]
Hereinafter, processing for obtaining a physical address from a logical address of an application data area performed by the OS will be described with reference to a process page table shown in FIG.
[0196]
This is a conversion table for using a virtual address instead of the physical address allocated on the memory 1103 in FIG.
[0197]
Specifically, as shown in FIG. 16, the process page table is a table indicating physical pages corresponding to the virtual pages of the process.
[0198]
Here, “page” is a basic unit in which the OS performs memory management. The page size is expressed as a power of 2, and many current OSs employ a size such as 2048, 4096, 8192 (bytes, etc.).
[0199]
The physical address and the virtual address are values obtained by adding the offset value in the page to the above-described page number. Note that the offset value in the page is the same for the physical address and the virtual address.
[0200]
When setting a physical address, it is possible to take a correspondence to a physical address corresponding to a logical address by referring to this table.
[0201]
For example, when a data area of an application is a logical page “M, M + 1” and data that exists across two areas is received, each physical page number 200 and physical page number 358 are multiplied by the page size. The physical address is calculated by adding the offset value in the page, and this is set in the DATA-POINTER 1604 of two consecutive commands in the command queue. By such processing, data can be transferred continuously from a physical address area that exists discontinuously to a virtual address area that exists continuously.
[0202]
Next, the relationship among the virtual space address, the physical space address, and the command queue will be described with reference to FIG.
[0203]
An application space exists in a part of the virtual memory space shown in FIG.
[0204]
A data buffer 1910 existing in the application space includes data A 1901, data B 1902, data C 1903, and data D 1904.
[0205]
Now, “3” in the data A 1901 is the page number in the virtual space, and corresponds to the area A 1921 and corresponds to the page number “52” in the physical space as shown in FIG.
[0206]
Since this correspondence is information set in the process table described with reference to FIG. 16, by referring to the process table, page “3” in the virtual space becomes page number “52” in the physical space. Judged by correspondence.
[0207]
Hereinafter, the data B 1902 has a page number “4” in the virtual space, corresponds to the area C 1923, and has a page number “73” in the physical space.
[0208]
The data C 1903 has a page number “5” in the virtual space, corresponds to the region B 1922, and has a page number “60” in the physical space.
[0209]
Finally, the data D1904 has a page number “6” in the virtual space, corresponds to the area D1924, and has a page number “81” in the physical space.
[0210]
Therefore, when data A1901, data B1902, data C1903, and data D1904 existing in the data buffer 1910 in the application space are received, a physical address to be set for a command in the command queue 1930 is determined. For the physical page, the page number “52” in the physical space is used for the command A1931. Also, the page number “73” in the physical space is used for the command B 1932. Further, the page number “60” in the physical space is used for the command C 1933. Finally, the command D1934 uses the page number “81” in the physical space. As described above, the physical address to be set in the command queue may be calculated.
[0211]
As described above, each entry is provided corresponding to the network packet of the command queue, and the area for setting the physical address is held for each entry, so that the physical address area that is discontinuous can be continuously Thus, data can be continuously received in a virtual address area that exists in a normal manner.
[0212]
Next, a series of processing according to the present invention will be described in the order of initialization processing, reception side processing, and transmission side processing.
[0213]
First, the operation of the initialization process will be described with reference to FIG.
[0214]
First, in step 2110, a command queue selection table 1401 is created and stored in the memory 1103.
[0215]
Next, in step 2120, a command queue is created and stored in the memory 1103.
[0216]
Subsequently, in step 2130, the management information of the command queue selection table 1401 created in step 2110 is set in RECV_Q_TBL_ADDR1231 and RECV_Q_TBL_LEN1232 in the multi-queue control register group 201 provided in the network adapter 1110.
[0217]
Thereafter, in step 2140, an activation command is set in the ADP_COMMAND 1211 in the multi-queue control register group 1201 provided in the network adapter 1110.
[0218]
Next, in step 2150, processing for determining a port to be used between applications is performed prior to communication processing.
[0219]
Initially, since the communication partner cannot be specified, at initialization communication, for example, “1” is used as the port number, and the maximum number of entries that can be used is statically set at initialization. Keep it.
[0220]
As an initialization communication method, communication between software that performs protocol processing in the kernel may be performed by a method similar to normal message passing.
[0221]
Note that the buffer used for communication is a buffer for the protocol server in the kernel.
[0222]
Through the initialization process described above, the software that performs the protocol process can perform communication similar to normal message communication (TCP / IP or the like).
[0223]
Next, as a process for determining a port to be used between applications prior to the communication process, a process for assigning port numbers of the transmission side and reception side systems is performed.
[0224]
First, processing for assigning ports is shown below.
[0225]
It is assumed that a port number is statically assigned to each computer in a network configured by connecting a plurality of computers in the network.
[0226]
That is, in the communication between the computer 1 and the computer 2, for example, port numbers are assigned so as to use the port numbers 100 to 200, and similarly, the range of port numbers used for broadcast communication is, for example, port A range of port numbers to be used is designated in advance so that numbers 1000 to 2000 are used.
[0227]
Since the range of port numbers that can be used for communication between computers is determined, the port number used between applications is determined by the same method as for protocols such as TCP / IP by communication between the protocol servers described above. Is done. The initialization process is completed by the above process.
[0228]
Next, FIG. 17 shows a flow of reception processing.
[0229]
In order to omit the data copy process at the time of communication, it is necessary that the data reception buffer is set prior to the data transmission.
[0230]
Therefore, first, in step 1810, the receiving-side application performs reception buffer allocation processing before starting data reception processing.
[0231]
Next, in step 1820, if the receiving system call is issued prior to the actual reception of the received data, the process branches to step 1830. Otherwise, the process branches to step 1850.
[0232]
In step 1830, the data is blocked until the end of data arrival (processing is waited for a predetermined time is referred to as “block”), and when all data arrives, the reception issuance process is started as shown in step 1840, Complete the reception process.
[0233]
On the other hand, in step 1850, after confirming that all data has arrived, the reception process is completed.
[0234]
Next, the reception multi-queue DMA process will be described with reference to FIG.
[0235]
First, in step 2010, packet data that has arrived via the network 1105 is captured by the network reception unit 1114 and stored in the reception buffer 1112.
[0236]
Next, in step 2020, the multi-queue DMA control unit 1111 monitors the reception buffer 1112. When packet data arrives, the multi-queue DMA control unit is activated and starts a series of processes.
[0237]
Specifically, the following processing is performed.
[0238]
First, a command queue to be executed is determined according to the contents of DMA_PORT_NO 1303 provided in the hard header portion of the packet. In this process, the contents of the RECV_Q_TBL_ADR1231 in the multi-queue control register group 1201 are multiplied by the contents of the DMA_PORT_NO 1303 times the size of each entry in the command queue selection table (for example, five entries when DMA_PORT_NO is “5”). In addition, this is done by calculating the address.
[0239]
Here, in order to improve security, for example, it is preferable that the DMA_PORT_NO 1303 is provided with information for security check, and data transfer is performed only when the information matches preset information. .
[0240]
Next, in step 2030, Q_ADR_O, Q_HEAD_O, Q_TAIL_O, and Q_LEN_O (O is equal to DMA_PORT_NO1303) are read out from the memory 1103 by DMA processing, and set to RECV_Q_ADR1241, RECV_Q_LEN1242, and RECV_QREV3_Q_EV12_Q_H_44_Q_EV12_Q_EV12.
[0241]
If the packet has the same DMA_PORT_NO 1303 and the same DMA_PORT_NO 1303 in the previous DMA processing, the processing in step 2030 can be omitted.
[0242]
In addition, by configuring the memory for holding a plurality of RECV_Q_ADR1241, RECV_Q_LEN1242, RECV_Q_HEAD1243, and RECV_Q_TAIL1244 in the network adapter 1110, the read processing by the DMA processing in step 2030 (reading from the memory 1103) is performed with high probability. Dashi processing) can be omitted.
[0243]
Next, in step 2040, if the content of the MODE 1306 in the packet header portion is “−1”, the process branches to step 2070; otherwise, the process branches to step 2050.
[0244]
In Step 2070, a command existing at a position indicated by a value obtained by adding REDV_Q_HEAD to RECV_Q_ADR is executed. Subsequent to step 2070, in step 2080, processing for adding the address for one command to the address where RECV_Q_HEAD exists so that the next address of the address where the command which executed the contents indicated by RECV_Q_HEAD exists is selected. And go to step 2090.
[0245]
On the other hand, in step 2050, the “RECV_Q_ADR + MODE” -th (command queue MODE-th) command is executed. Subsequent to step 2050, in step 2060, a process of adding an address for (1 + MODE) command to an address where RECV_Q_HEAD exists so that the next address of the address where the command executing the RECV_Q_HEAD contents exists is selected. Go to step 2090.
[0246]
In step 2090, the contents of RECV_Q_ADR1241, RECV_Q_LEN1242, RECV_Q_HEAD1243, and RECV_Q_TAIL1244 are written in the entries Q_ADR_O, Q_HEAD_O, Q_TAIL_O, Q_LEN_O (O is equal to DMA_PORT_, and 130 is completed as DMA_PORT_NO).
[0247]
By repeating the multi-queue DMA processing described above, the packet data is directly transferred to the data buffer in the application space.
[0248]
Next, processing on the transmission side will be described with reference to FIG.
[0249]
First, in step 2210, the application issues a transmission process.
[0250]
Next, in step 2220, the physical address of the transmission data buffer in the application that issued the transmission processing command is calculated by the method described with reference to FIG.
[0251]
Next, in step 2230, a command having the physical address calculated in step 2220 as a parameter is set in the transmission command queue.
[0252]
Next, in step 2240, the application that issued the transmission process is blocked.
[0253]
Subsequently, in step 2250, the network adapter 1110 performs data transmission, that is, transmission processing. When the network adapter finishes transmission, it issues an interrupt.
[0254]
Next, in step 2260, the processor 1102, which has received the instruction to interrupt, issues a transmission process to start the blocked application. This completes the transmission process.
[0255]
As described above, a series of processing according to the present invention, that is, initialization processing, reception side processing, and transmission side processing is performed, and high-speed communication of packets in the network is possible.
[0256]
【The invention's effect】
According to the present invention, in a network configured by connecting a plurality of information processing systems, data transmission / reception processing within a packet can be performed at high speed without performing data copying, page table change processing, or the like by the receiving side information processing system. It is possible to provide a means capable of simple information communication at low cost.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a computer network system.
FIG. 2 is a configuration diagram of a conventional network system.
FIG. 3 is a configuration diagram of a network packet.
FIG. 4 is a flowchart of a transmission software process.
FIG. 5 is an explanatory diagram of a network adapter transmission operation.
FIG. 6 is an explanatory diagram of reception software pre-processing.
FIG. 7 is an explanatory diagram of a network adapter reception operation.
FIG. 8 is an explanatory diagram of received software post-processing.
FIG. 9 is an explanatory diagram of reception application processing.
FIG. 10 is a configuration diagram of a computer network system.
FIG. 11 is a configuration diagram of a multi-queue DMA control unit.
FIG. 12 is a configuration diagram of a packet.
FIG. 13 is an explanatory diagram of a data structure for DMA processing.
FIG. 14 is an explanatory diagram of a configuration of a command queue selection table.
FIG. 15 is a configuration diagram of a command queue.
FIG. 16 is an explanatory diagram of a process page table.
FIG. 17 is an explanatory diagram of a processing flow on the receiving side.
FIG. 18 is an explanatory diagram of correspondence of buffer command queues.
FIG. 19 is an explanatory diagram of a multi-queue DMA processing flow on the receiving side.
FIG. 20 is an explanatory diagram of an initialization process flow.
FIG. 21 is an explanatory diagram of a transmission processing flow.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Computer in a network, 110 ... Network adapter, 111 ... Reception DMA control information holding means, 112 ... Transmission DMA control information holding means, 113 ... Interrupt control information holding means, 114 ... Adapter control information holding means, 115 ... Adapter control Means 116: Reception DMA control information selection means 117 ... DMA division information holding means 118 118 Network transmission / reception unit 119 ... Own address holding means 120 ... Multi-queue DMA control unit 121 ... Transmission / reception buffer 122 ... Internal bus , 130 ... processor, 140 ... I / O device, 150 ... memory, 160 ... OS space, 170 ... user space, 161 ... reception protocol information, 162 ... reception protocol information, 163 ... transmission protocol information, 164 ... reception area designation information 165 ... Reception area designation information, 167 ... Reception Area designation information selection information, 171 ... user data, 172 ... user data, 173 ... user data, 200 ... computer in network, 230 ... processor, 250 ... memory, 210 ... network adapter, 211 ... received DMA control information holding means, 212 ... Transmission DMA control information holding means, 213 ... Interrupt control information holding means, 214 ... Adapter control information holding means, 215 ... Adapter control means, 218 ... Network transmitting / receiving section, 219 ... Own address holding means, 220 ... DMA control section, 221: Buffer for transmission / reception, 222: Internal bus, 280 ... System bus, 1101 ... Computer node, 1102 ... Processor, 1103 ... Memory, 1104 ... System bus, 1110 ... Network adapter, 1111 ... Multi-queue DMA controller, 1112 ... Reception for Ffa, 1113 ... transmission buffer, 1114 ... network reception unit, 1115 ... network transmission unit, 1201 ... multiqueue control register group, 1202 ... DMA controller, 1300 ... hard header part, 1310 ... packet data unit

Claims (1)

A communication method for communicating data between applications of a computer in a network configured by connecting at least two computers including at least an arithmetic processing unit, a main storage unit, and a network adapter via each network adapter. There,
Prior to the communication of the data, an identifier for performing direct transfer of data between the application of the sending computer and the application of the receiving computer is determined by message communication,
After the application of the receiving computer pre-assigns a reception area corresponding to the identifier to the main storage unit of the computer, and sets information indicating the correspondence between the allocated reception area and the identifier in a table format,
When the sending application computer issues a transmission process, the network adapter of the sender computer transmits the data by adding the identifier to the data,
Network adapter receiver side computer, for said identifier that is transferred over the network is added data, searching for information indicating a correspondence relationship prior Symbol receiving area identifier, assigned in advance a receiving destination identify receiving area, rows that have the transfer of data to the receiving area,
When the application of the receiving computer issues a reception request, it is blocked if the data is not yet transferred to the receiving area, and is blocked if the data is transferred to the receiving area. When the application is started and receives the data transferred to the receiving area,
A communication method characterized in that, when an application of a receiving computer issues a reception request, if the data has already been transferred to the reception area, the data transferred to the reception area is immediately received .

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