JP3627743B2 - Node in data transmission system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transmission system that transmits time-sequential data such as digital audio data in a predetermined cycle via a communication network, and is transmitted without providing a dedicated synchronization signal line in particular. The present invention relates to a data transmission system configured so that original data can be accurately reproduced on the receiving side in consideration of the state of time-series change on the receiving side.
[0002]
[Prior art]
Data transmission methods via a network are roughly classified into a synchronous method and an asynchronous method. Generally, in the synchronization method, a dedicated synchronization signal line or the like is provided between the transmission side and the reception side, and data is transmitted so as to synchronize with it, so that the reception side is based on the transmitted data. Data can be accurately reproduced. Therefore, the synchronous data transmission method is a method suitable for transmission of digital audio data or the like that requires accurate reproduction of the temporal position of information on the receiving side. However, a configuration for separately providing a synchronization signal line or synchronizing between transmission and reception is necessary. Further, since the line is dedicated only for the communication during the communication by the synchronous method, there is a drawback that the versatility as the communication method is lacking.
On the other hand, the asynchronous method is suitable for transmitting character data or still image data such as personal computer communication because it is not necessary to secure a dedicated synchronization signal line. However, the packet transmission employed in the asynchronous system is not suitable for transmission of digital audio data or the like because information on the original temporal position of data is lost.
[0003]
[Problems to be solved by the invention]
Therefore, recently, each node has an individual clock oscillation circuit and a clock counter that counts the clock, and the node on the transmission side adds time data (time stamp) indicating the time position of the data to the head of the packet data. The data is transmitted over the network, the receiving node compares the time data with the count value of the internal clock counter, and if they do not match, the count value is corrected with the time data, and the corrected clock counter The pseudo-synchronous method of sequentially reproducing the data based on the count value of the system has been adopted. For example, IEEE 1394 is one that defines such a pseudo synchronous communication method (isochronous communication method).
That is, in this pseudo-synchronization method, the clock oscillation circuit of each node does not always oscillate at the same frequency completely, and recognizes that there is a certain amount of error, and the deviation due to the error is detected at every synchronization timing, that is, time A method of correcting the count value of the clock counter in accordance with the time data every time data is received is adopted.
When correcting this count value, it follows the rule that the same value as the count value is repeated or skipped in the positive direction, but only the backward movement in the negative direction is not allowed.
In accordance with such rules, when the digital audio data etc. is reproduced as the original data accurately in consideration of the time-series change state on the receiving side based on the transmitted data, the count value becomes positive. When flying, there is a problem that the data of the skipped data is not read, or in the worst case, if the data of the skipped data is specified by the time stamp, the subsequent packet data cannot be reproduced correctly. occured. In addition, since jumping in the positive direction is permitted, there is a problem that a circuit for generating a clock becomes complicated.
The present invention has been made in view of the above points, and in the pseudo-synchronization method, data that can eliminate the jump of the value of the time information caused by the deviation of the oscillation frequency of the clock oscillation circuit provided for each node. The node is to be configured so that a transmission system can be provided. Furthermore, it is an object of the present invention to configure a node so as to provide a data transmission system capable of accurately reproducing the reproduction time relationship of data using such accurate time information.
[0004]
[Means for Solving the Problems]
A node according to the present invention according to claim 1 is composed of a plurality of nodes that operate asynchronously and a communication network that connects the plurality of nodes, and each node cycles according to a clock generated by a built-in oscillation circuit. A time is counted, and a certain node among the plurality of nodes transmits a cycle start packet including a cycle start time indicating a cycle time of a start timing of one isochronous cycle to another node, and receives the cycle start packet The other node synchronizes the cycle start time and the cycle time, and is configured to perform synchronous communication using a synchronous data packet including a time stamp based on the synchronized cycle time between the plurality of nodes. In a data transmission system A receiving unit that receives the cycle start packet or the synchronous data packet via the communication network, the higher-order bits corresponding to the information amount of the cycle start time, and the cycle start according to the clock; A counter that sequentially generates cycle time count data consisting of lower-order bits corresponding to time information with accuracy exceeding the minimum resolution of time, and generation of the counter when the receiving unit receives the cycle start packet from the certain node A counter synchronizer that matches the time indicated by the cycle time count data with the time indicated by the cycle start time, and a cycle in which the upper bit of the cycle time count data is the cycle time at the node. When the time supply unit and the reception unit receive the synchronization data packet, the received synchronization data is based on the cycle time supplied from the cycle time supply unit and the time stamp included in the received synchronization data packet. And a data synchronizer for controlling the packet read timing.
The node according to the present invention according to claim 2 claims a node that receives a synchronous data packet according to the present invention, and includes a plurality of nodes that operate asynchronously and a communication network that connects the plurality of nodes. Each of the nodes counts a cycle time according to a clock generated by a built-in oscillation circuit, and a cycle including a cycle start time in which a certain node among the plurality of nodes indicates a cycle time of a start timing of one isochronous cycle. A time based on the synchronized cycle time between the plurality of nodes, wherein the other node that has transmitted the start packet to another node and has received the cycle start packet synchronizes the cycle start time and the cycle time. Same including stamp The other node in the data transmission system configured to perform synchronous communication using a data packet, the receiving unit receiving the cycle start packet via the communication network, and the cycle according to the clock A counter that sequentially generates cycle time count data consisting of upper bits corresponding to the amount of information of start time and lower bits corresponding to time information with accuracy exceeding the minimum resolution of the cycle start time; and the receiving unit from the certain node When the cycle start packet is received, a counter synchronization unit that matches the time indicated by the cycle time count data generated by the counter at the same time as the time indicated by the cycle start time; and Upper bits Characterized by comprising a cycle time supply unit to the cycle time at the node.
[0005]
A node among a plurality of nodes connected to the communication network becomes a node that transmits a cycle start packet including a cycle start time, and other nodes receive this. Each node has an oscillation circuit incorporated therein. In the node defined in claims 1 and 2, according to the clock generated by the built-in oscillation circuit, the upper bit corresponding to the information amount of the cycle start time and the lower order corresponding to time information with accuracy exceeding the minimum resolution of the cycle start time A counter that sequentially generates cycle time count data consisting of bits, and when the cycle start packet from the certain node is received, the time indicated by the cycle time count data generated by the counter is the time indicated by the cycle start time And the upper bits of the cycle time count data are used as the cycle time of the node. Thus, the cycle time of each node is pseudo-synchronized with reference to the cycle start time given by the cycle start packet. At that time, the cycle time count data is composed of upper bits corresponding to the information amount of the cycle start time and lower bits corresponding to time information with accuracy exceeding the minimum resolution of the cycle start time. Since the higher order bits are used, even if the oscillation frequency of each oscillation circuit of the certain node that transmits the cycle start packet and the other node that receives the packet slightly deviates, It is possible to eliminate the jump of the generated cycle time value. Furthermore, by controlling the read timing of the received synchronous data packet using such an accurate cycle time, the reproduction time relationship of the received data can be accurately reproduced. Therefore, there is an excellent effect that data that takes into consideration the state of time-series change such as digital audio data can be accurately reproduced on the receiving node side.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
FIG. 2 is a schematic block diagram showing the overall configuration of an embodiment of the data transmission system according to the present invention. FIG. 3 is a diagram showing a configuration example of data transmitted by this data transmission method. In this specification, a case where data transmission is performed according to the above-described IEEE 1394 communication method will be described as an example.
The figure shows a case where the transmitting side node 10, the receiving side node 20, and the other nodes 30 and 40 are connected via the communication network 90. In the following, for convenience of explanation, only data transmission between the transmission side node 10 and the reception side node 20 will be described. However, many other nodes may be connected, or the transmission side node and the reception side may be connected. It goes without saying that only the nodes may be connected, or data transmission between the transmitting side node 10 and the receiving side node 20 (nodes 30 and 40) may be performed.
In this embodiment, when the node 30 sequentially outputs a cycle start packet signal corresponding to a synchronization signal (cycle sync) of a normal cycle period of 125 μsec as shown in FIG. 3, the transmitting side node 10 is as shown in FIG. A case will be described in which a simple data sequence is transmitted to the communication network 90, and the data sequence 9 is received and reproduced by the receiving side node 20.
[0007]
In the transmission side node 10, the data generation circuit 11 operates in accordance with a clock having a predetermined frequency (for example, a frequency of 24.576 MHz (period about 40 nsec)) generated by a built-in crystal oscillator (not shown), and performs predetermined sampling. A plurality of data having a time-series arrangement with a period T is sequentially generated and output. For example, sequential sample data of a digital audio signal is output. For example, the data generation circuit 11 may include an audio playback device such as a CD (compact disc) player, or may include a sound synthesis device that synthesizes sound sample data in real time. . The sampling period T of data output from the data generation circuit 11 may be appropriately changed according to the data source.
[0008]
The data output from the data generation circuit 11 is temporarily stored in the transmission data buffer 12 in chronological order. The transmission data buffer 12 is a buffer register that performs input / output operations asynchronously.
The counter circuit 13 generates time stamp data, that is, time data, and is a 32-bit running counter that counts a clock having a predetermined frequency generated by a crystal oscillator (not shown).
The network interface 14 is based on the data temporarily stored in the transmission data buffer 12 in synchronization with a predetermined transmission interrupt cycle (synchronization signal (cycle sync) output from the node 30 described above) as shown in FIG. A data string 9 (hereinafter referred to as a “cycle packet string”) corresponding to one isochronous cycle is configured and transmitted to the communication network 90.
[0009]
As shown in FIG. 3, the cycle packet string 9 includes a cycle start packet 91, a synchronous data packet group 92, and an asynchronous data packet group 93.
The cycle start packet 91 is composed of 32 bits, the upper 20 bits are data indicating the cycle timing of the cycle packet sequence 9, and the lower 12 bits are the synchronization signal (cycle) on the communication network 90. This is data indicating cycle start data X indicating how much time delay is transmitted from sync).
The synchronization data packet group 92 is composed of a plurality of P pieces of packet data to be subjected to pseudo synchronization signal processing. In the figure, five synchronous data packets from channel J to channel N are shown as an example. The number P of synchronous data packets can be arbitrarily set. Further, each synchronous data packet has a plurality of groups each consisting of a predetermined number Q of data and time stamp data indicating the time position of any one of them (in this embodiment, the first data). In this embodiment, one group is composed of four data and one time stamp. That is, in the figure, one piece of time stamp data T1, T2 is provided for each of the four pieces of data D1-D4, D5-D8. The time stamp data T1 indicates the time position of the first data D1, and the time stamp data T2 indicates the time position of the data D5. Therefore, each synchronous data packet is composed of an integral multiple of (Q + 1) data groups. Note that there are cases in which digital audio data is transmitted even if the number of data is less than Q because of communication, but detailed description thereof will be omitted.
The asynchronous data packet group 93 includes a plurality of R pieces of packet data to be subjected to asynchronous signal processing. In the figure, two packet data, packet B and packet C, are shown as an example. The asynchronous data packet may not exist.
[0010]
In the receiving side node 20, the network interface 24 receives the cycle packet sequence 9 transmitted via the communication network 90, and temporarily stores it in the reception data buffer 22 in time series in the order of reception. The reception data buffer 22 is a buffer register that performs input / output operations asynchronously. Based on the cycle start data X in the cycle start packet of the received cycle packet sequence 9, the clock generation circuit 23 reproduces the same original sampling period T as the data supplied from the data generation circuit 11 of the transmission side node 10. To do.
The data generation circuit 21 sequentially reads and reproduces the data temporarily stored in the reception data buffer 22 according to the reproduced sampling period T given from the clock generation circuit 23. The read data is used as appropriate. The form in which the reproduced data is used is arbitrary. For example, D / A conversion may be performed as it is, and sound may be generated from a speaker or the like, or data such as sound generated or processed from a speaker or the like after processing of an effect or the like may be transmitted to the outside. Also good.
[0011]
A detailed configuration of the reception side node 20 will be described with reference to FIG.
In FIG. 1, the cycle time extraction circuit 51 extracts a cycle start packet 91 from the transmitted cycle packet sequence 9, outputs the cycle start packet data to the reception cycle time register 52, and the remaining synchronous data packets. The group 92 and the asynchronous data packet group 93 are output to the data separation circuit 55.
The reception cycle time register 52 is a register having a 34-bit configuration. A constant “00” is stored in advance in the lower 2 bits, and a 32-bit configuration extracted by the cycle time extraction circuit 51 in the upper 32 bits. The cycle start packet data is temporarily stored and the 34-bit data is transferred to the built-in cycle time counter 53 as it is.
The built-in cycle time counter 53 is a 34-bit counter that counts a clock having an oscillation frequency of 98.304 MHz (period: about 10 nsec) output from a crystal oscillator built in the reception node 20. The contents are sequentially rewritten by the transferred data. Note that the value of the internal cycle time counter 53 may be rewritten only when the 34-bit count values of the reception cycle time register 52 and the internal cycle time counter 53 are different.
The cycle time register 54 always stores the count value of the upper 32 bits of the built-in cycle time counter 53. Accordingly, when the count value of the upper 32 bits of the built-in cycle time counter 53 is changed or rewritten, the value of the cycle time register 54 is also changed accordingly.
The relationship among the reception cycle time register 52, the built-in cycle time counter 53, and the cycle time register 54 is illustrated in FIG. As is apparent from the figure, the 34-bit data of the reception cycle time register 52 is output to the internal cycle time counter 53 as it is, and the upper 32-bit data of the internal cycle time counter 53 is output to the cycle time register 54 as it is. Become.
[0012]
The data separation circuit 55 extracts time stamp data from the packet data constituting the synchronous data packet, outputs the time stamp data to the time stamp register 56, and outputs the remaining data to the reception data buffer 22. For example, as shown in FIG. 3, when one time stamp data T1 is provided for four data D1 to D4, the first time stamp data T1 is output to the time stamp register 56, and the rest The data D <b> 1 to D <b> 4 are output to the reception data buffer 22. The data separation circuit 55 does not perform any processing on the packet data of the asynchronous data packet group, and transfers the data to the reception data buffer 22 as it is.
The time stamp register 56 temporarily stores the time stamp data T1 separated by the data separation circuit 55.
The comparison circuit 57 compares the stored values of the cycle time register 54 and the time stamp register 56, and if they match, the comparison signal (clock signal) is sent via the gate circuit 58 to the phase difference detection circuit of the clock generation circuit 23. To 61.
[0013]
The gate circuit 58 enters a through state in which the coincidence signal output from the comparison circuit 57 is output to the phase difference detection circuit 61 as it is when the output of the flip-flop circuit 5A is high level “1”, and the output of the flip-flop circuit 5A is low. When the level is “0”, the gate state of cutting off the output of the comparison circuit 57 is established.
The detection circuit 59 detects whether the value of the lower 2 bits of the built-in cycle time counter 53 has become “00”, and outputs a set signal to the set terminal S of the flip-flop circuit 5A when it has become “00”. The output Q of the flip-flop circuit 5A is set to the high level “1”.
The flip-flop circuit 5A inputs the detection signal from the detection circuit 59 to the set terminal S, the coincidence signal of the comparison circuit 57 to the reset terminal R via the gate circuit 58, and outputs the output Q as the gate control terminal of the gate circuit 58. Output to.
[0014]
The clock generation circuit 23 is a PLL circuit including a phase difference detection circuit 61, a VCO 62, and a 1 / Q frequency division circuit 63, and is based on a coincidence signal from a comparison circuit 57 input via a gate circuit 58. Operate. Here, Q is the number of data constituting one group of synchronous data packets as described above. Accordingly, when the number of data Q is four, a 1/4 frequency divider is used for the frequency divider, and when the number of data is 8, a 1/8 frequency divider is used for the frequency divider.
The data generation circuit 21 includes a read control circuit 71 and a D / A conversion circuit 72. The read control circuit 71 sequentially reads the data stored in the reception data buffer 22 in synchronization with the clock from the VCO 62 of the clock generation circuit 23 and outputs it to the D / A conversion circuit 72. The D / A conversion circuit 65 converts the data read by the read control circuit 71 into an analog signal.
[0015]
Hereinafter, the operation of the reception side node 20 in FIG. 1 will be described with reference to FIG.
FIG. 5 shows the passage of time on the vertical axis, and how the values of the reception cycle time register 52, the built-in cycle time counter 53, and the cycle time register 54 change with the passage of time. FIG. 5A shows a case where the built-in crystal oscillator of the transmission side node 10 oscillates at a slightly higher frequency than the built-in crystal oscillator of the reception side node 20, and FIG. The case where the built-in crystal oscillator of the side node 10 oscillates at a slightly lower frequency than the built-in crystal oscillator of the reception side node 20 is shown.
[0016]
First, the case of FIG. 5A will be described.
When the built-in crystal oscillator of the transmitting node 10 oscillates at a slightly higher frequency than the built-in crystal oscillator of the receiving node 20, the count operation of the built-in cycle time counter 53 is gradually delayed, and the cycle start when the count value is received. It becomes smaller than the value of the cycle start data X of the lower 12 bits included in the packet. Such a case is called a delayed state. That is, the cycle start packet including the cycle start data X of “326” must be extracted by the cycle time extraction circuit 51 at the time t4 when the value of the built-in cycle time counter 53 is “326.00”. In the generated state, the value of the cycle time counter 53 is extracted at the time point t3 of “325.75”. Therefore, the value of the built-in cycle time counter 53 is rewritten to “326.00” at the time t3 when the cycle start data X is extracted, and thereafter, the count is sequentially incremented according to the clock of the built-in crystal oscillator.
In accordance with such data rewriting processing of the built-in cycle time counter 53, the value of the cycle time register 54 advances and changes by one clock of the built-in crystal oscillator. The output timing of the coincidence signal output from the comparison circuit 57 is also slightly longer, but it is absorbed by the operation of the clock generation circuit 23, that is, the PLL circuit.
Since the numbers after the decimal point are expressed by 2 bits, “. 00 ”,“. 25 ”,“. 50 ”and“. 75 ”.
[0017]
Next, the case of FIG. 5B will be described.
When the built-in crystal oscillator of the transmitting side node 10 oscillates at a slightly lower frequency than the built-in crystal oscillator of the receiving side node 20, this time, the counting operation of the built-in cycle time counter 53 proceeds gradually, and the count value is received. It becomes larger than the value of the low-order 12-bit cycle start data X included in the start packet. Such a case is called a state where progress has occurred. That is, the cycle start packet including the cycle start data X of “325” must be extracted by the cycle time extraction circuit 51 at the time t1 when the value of the built-in cycle time counter 53 is “325.00”. In the generated state, the value of the cycle time counter 53 is extracted at time t2 of “325.25”. Accordingly, the value of the built-in cycle time counter 53 is rewritten to “325.00” at the time t2 when the cycle start data X is extracted, and thereafter, the count is sequentially incremented according to the clock of the built-in crystal oscillator. In the state where this advance has occurred, the value of the cycle time register 54 does not change in accordance with the data rewrite processing of the internal cycle time counter 53, but the value of the lower 2 bits of the internal cycle time counter 53 is "00" is detected. That is, the detection circuit 59 detects “00” between the time t2 and the time t1, outputs a set signal to the set terminal S of the flip-flop circuit 5A, and sets the output Q of the flip-flop circuit 5A to the high level “ Since it is set to 1 ″, the coincidence signal is continuously output from the comparison circuit 57 to the clock generation circuit 23 in the same manner in a short time. In this case as well, this clock generation circuit 23, that is, the PLL circuit is output. It is absorbed in the operation of and has no effect.
In accordance with the data rewriting process of the built-in cycle time counter 53, the value of the cycle time register 54 changes with a delay of one clock of the built-in crystal oscillator. The output timing of the coincidence signal output from the comparison circuit 57 is also slightly shifted, but it is absorbed by the operation of the clock generation circuit 23, that is, the PLL circuit.
According to the above-described embodiment, since the skip of the built-in cycle time counter 53 can be eliminated, a comparison circuit between the time stamp register and the coil time register 54 can be configured easily and the jitter amount of the digital audio data can be reduced. Can do. In addition, since the built-in cycle time counter 53 is corrected by the decimal part, the jitter of the digital audio data is dispersed on the time axis, so that the clock generation circuit 23, that is, the PLL circuit can be easily filtered.
[0018]
In the above-described embodiment, the case where the number of data constituting one group of the synchronous data packet is four has been described. Furthermore, it is preferable to set Q to a power of 2 because the division operation can be simplified.
Alternatively, a process of adding unique time data may be performed on data to which time stamp data is not added, and reproduction and reading may be performed with reference to the unique time data of each data.
In the above-described embodiment, the case in which the lower 2 bits are added to the built-in cycle time counter to increase the count clock by four has been described, but another register or the like may be provided.
In the above-described embodiment, a case has been described in which the reception side node operates at a frequency (98.304 kHz) four times that of the transmission side node. However, the transmission side node operates at the same frequency as the reception side node, and communication is performed. When data is transmitted on the network, it may be transmitted at a normal frequency (24.576 kHz).
In the above-described embodiment, the case where the value of the built-in cycle time counter 53 is rewritten with the value of the reception cycle time register 52 when the low-order 12-bit cycle start data X included in the cycle start packet is received has been described. Time stamp data may be extracted from the packet data constituting the synchronous data packet, and the rewriting process may be performed for each extracted time stamp data.
[0019]
【The invention's effect】
According to the present invention, in the pseudo-synchronous method (isochronous communication method), the cycle time count data generated at each receiving node includes the upper bits corresponding to the information amount of the cycle start time included in the cycle start packet and the cycle start time. It consists of low-order bits corresponding to time information with accuracy exceeding the minimum resolution, and the high-order bits are used as the actual cycle time. Even if the oscillation frequency of each oscillation circuit of the node (reception node) slightly deviates, the jump of the cycle time value caused by the deviation of the oscillation frequency can be eliminated. Furthermore, by controlling the read timing of the received synchronous data packet using such an accurate cycle time, the reproduction time relationship of the received data can be accurately reproduced. Therefore, there is an excellent effect that data in consideration of the state of time-series change such as digital audio data can be accurately reproduced on the receiving node side.
[Brief description of the drawings]
FIG. 1 is a detailed configuration block diagram showing an embodiment of a receiving node in a data transmission system according to the present invention.
2 is a schematic block diagram showing an overall configuration of an embodiment of a data transmission system including a receiving node shown in FIG. 1;
FIG. 3 is a diagram showing a configuration example of data transmitted by the data transmission system according to the present invention.
4 is a diagram showing a relationship among a reception cycle time register, a built-in cycle time counter, and a cycle time register in FIG. 1;
FIG. 5 is a diagram showing changes in values of a reception cycle time register, a built-in cycle time counter, and a cycle time register over time.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Transmission side node, 11 ... Data generation circuit, 12 ... Transmission data buffer, 13 ... Counter circuit, 14 ... Network interface, 20 ... Reception side node, 21 ... Data generation circuit, 22 ... Reception data buffer, 23 ... Clock generation circuit , 24 ... Network interface, 30, 40 ... Other nodes, 90 ... Communication network, 51 ... Cycle time extraction circuit, 52 ... Receive cycle time register, 53 ... Built-in cycle time counter, 54 ... Cycle time register, 55 ... Data separation Circuit 56... Time stamp register 57 57 comparator circuit 58 gate circuit 59 detection circuit 5A flip-flop circuit 61 phase difference detection circuit 62 VCO 63 frequency divider 71 read control Circuit, 72... D / A conversion circuit.

Claims (2)

Each node is composed of a plurality of nodes that operate asynchronously and a communication network that connects the plurality of nodes. Each node counts a cycle time according to a clock generated by a built-in oscillation circuit. A node transmits a cycle start packet including a cycle start time indicating a cycle time of a start timing of one isochronous cycle to another node, and the other node receiving the cycle start packet transmits the cycle start time and the cycle start time The other node in the data transmission system configured to perform synchronous communication using a synchronous data packet including a time stamp based on the synchronized cycle time between the plurality of nodes. And
A receiving unit for receiving the cycle start packet or the synchronous data packet via the communication network;
According to the clock, a counter that sequentially generates cycle time count data consisting of upper bits corresponding to the information amount of the cycle start time and lower bits corresponding to time information with accuracy exceeding the minimum resolution of the cycle start time;
A counter synchronization unit for causing the time indicated by the cycle time count data generated by the counter to coincide with the time indicated by the cycle start time when the receiving unit receives the cycle start packet from the certain node; ,
A cycle time supply unit that sets the upper bit of the cycle time count data as the cycle time in the node;
When the reception unit receives the synchronization data packet, the read timing of the received synchronization data packet is determined based on the cycle time supplied from the cycle time supply unit and the time stamp included in the received synchronization data packet. And a data synchronization unit for controlling the node. Each node is composed of a plurality of nodes that operate asynchronously and a communication network that connects the plurality of nodes. Each node counts a cycle time according to a clock generated by a built-in oscillation circuit. A node transmits a cycle start packet including a cycle start time indicating a cycle time of a start timing of one isochronous cycle to another node, and the other node receiving the cycle start packet transmits the cycle start time and the cycle start time The other node in the data transmission system configured to perform synchronous communication using a synchronous data packet including a time stamp based on the synchronized cycle time between the plurality of nodes. And
A receiving unit that receives the cycle start packet via the communication network;
According to the clock, a counter that sequentially generates cycle time count data consisting of upper bits corresponding to the information amount of the cycle start time and lower bits corresponding to time information with accuracy exceeding the minimum resolution of the cycle start time;
A counter synchronization unit for causing the time indicated by the cycle time count data generated by the counter to coincide with the time indicated by the cycle start time when the receiving unit receives the cycle start packet from the certain node; ,
A node comprising: a cycle time supply unit that uses the upper bits of the cycle time count data as the cycle time in the node.

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