JP3629861B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a field effect transistor such as a GaAs MESFET for high output.
[0002]
[Prior art]
A Pt buried type field effect transistor in which a gate electrode is formed of Pt and the gate electrode is subjected to heat treatment to form a Schottky junction with the active layer has a desired Schottky characteristic, current value, threshold voltage, A high withstand voltage is obtained and it is a very effective device.
[0003]
FIG. 1 is a sectional view showing a manufacturing process of a conventional Pt buried type GaAs MESFET 9. FIG. 1A is a view showing a semi-insulating GaAs substrate 1 before forming a gate electrode, a source and a drain electrode, and an active layer 2 made of an n-type ion implantation layer is formed on the surface of the GaAs substrate 1. Under this, a p-layer 3 is formed. Further, on both sides of the active layer 2 and the p layer 3, n ⁺ regions (source regions and drain regions) 4 into which n-type ions are implanted at a high concentration are formed.
[0004]
First, a source electrode 5 and a drain electrode 6 that are in ohmic contact with the n ⁺ region are formed on the n ⁺ region 4 of the GaAs substrate 1 by photolithography as shown in FIG. A heat treatment is applied for conversion. Subsequently, Pt which becomes the gate electrode 7 is deposited on the upper surface of the active layer 2 by a vapor deposition method or the like at a vapor deposition rate of 100 to 200 Å / sec. Thereafter, when heat treatment is performed in H ₂ gas at about 400 ° C., Pt diffuses into the active layer and Pt and GaAs undergo a solid phase reaction to form a metal compound mainly composed of PtAs, PtGa, or the like. The reaction layer 8 made of PtAs, PtGa or the like becomes a good Schottky junction, and the junction position moves into GaAs as the solid-phase reaction progresses, and a buried Pt gate electrode as shown in FIG. GaAs MESFET 9 having 7 is formed.
[0005]
[Problems to be solved by the invention]
Since Pt has a large film stress and its adhesion to a semiconductor substrate such as a GaAs substrate is not very good, if the film thickness of the Pt gate electrode is increased, the adhesion becomes poor and the film is easily peeled off. Therefore, in a field effect transistor using Pt as a gate electrode, Pt is formed relatively thin (film thickness is about 500 mm). However, if the film thickness of the Pt gate electrode is reduced at a deposition rate of 100 to 200 liters / sec, it becomes difficult to control the film thickness, and variations in the thickness of the gate electrode cause variations in characteristics as they are. There was a problem that a field effect transistor could not be produced.
[0006]
Therefore, in order to improve the adhesion between Pt and the semiconductor substrate, a technique of thinly forming a metal such as Ti or Si under the Pt is used. However, in these methods, if the layer of Ti, Si or the like for improving the adhesion is too thick, the original Schottky characteristic cannot be obtained, so the layer of Ti, Si, etc. must be formed thin. However, there was a problem in the controllability, and there was a problem that a field effect transistor with uniform characteristics could not be produced.
[0007]
The present invention has been made in view of the drawbacks of the conventional examples described above, and an object of the present invention is to form a Pt layer having good adhesion on a Schottky electrode of a semiconductor device and to form a thin film. The object is to make it possible to produce a thick Pt layer with good controllability.
[0008]
DISCLOSURE OF THE INVENTION
A method of manufacturing a semiconductor device according to the present invention includes forming a Schottky electrode having at least the lowest layer of Pt on a semiconductor substrate, and subjecting the Pt layer to the semiconductor substrate by heat treatment. In this case, the lowermost layer of Pt of the Schottky electrode is deposited on the semiconductor substrate at a deposition rate of 20 速度 / sec or less.
[0009]
When the Pt of the Schottky electrode was formed at a deposition rate of 20 cm / sec or less, a Pt layer having a small film stress could be formed, and good adhesion to the semiconductor substrate was exhibited. Accordingly, Pt film peeling can be made difficult to occur, and the yield of the semiconductor device can be improved.
[0010]
Moreover, since the film thickness control of the Pt film is facilitated by slowing down the deposition rate in this way, the film thickness variation hardly occurs even if the thin Pt film is formed, and the pinch-off voltage Vp, the saturation drain current Idss, etc. The characteristics can be stabilized. Further, since it is not necessary to form a layer such as Ti or Si under the Pt layer as in the prior art, the problem of controllability does not occur.
[0011]
On the other hand, the deposition rate of the lowermost layer of Pt is desirably 2 で / sec or more. This is because if the deposition rate is slower than this, the film thickness cannot be easily controlled, and the diffusion amount of Pt into the semiconductor substrate fluctuates and the device characteristics such as the pinch-off voltage vary.
[0012]
Such a semiconductor device can be applied to a device using a compound semiconductor, and in particular, can be used for a GaAs MESFET. In particular, a high effect can be achieved by using it for a Pt buried type field effect transistor in which a lowermost Pt layer and an active layer are reacted to form a Schottky junction. Moreover, in that case, if the lowermost Pt layer is completely reacted with the active layer by heat treatment, variations in the element characteristics can be reduced and the element characteristics can be stabilized, and the film of the lowermost Pt layer can be obtained. The element characteristics can be easily managed by controlling the thickness.
[0013]
As the structure of the Schottky electrode, it is desirable that the Mo layer is formed on the Pt layer (the reaction layer after the heat treatment), the Ti layer is formed thereon, and the low resistance metal layer such as Au or Al is formed thereon. According to such an electrode configuration, a satisfactory Schottky junction can be obtained by completely reacting the lowermost Pt layer with the active layer, and a satisfactory operation can be performed even under forward bias. Furthermore, the gate resistance can be reduced by the low resistance metal layer. Also, the action of the Mo layer prevents interdiffusion between the Pt layer and the Ti layer, and stops the reaction between the gate electrode and the active layer when the Pt layer has completely reacted with the active layer. it can. Furthermore, although the Mo layer has a large film stress and poor adhesion to the Au layer or Al layer, the adhesion to the Mo layer can be improved by forming a Ti layer on the Mo layer.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment)
2A to 2H are schematic cross-sectional views showing a manufacturing process of a Pt buried type GaAs MESFET (Pt gate FET) according to an embodiment of the present invention. The optimum embodiment of the present invention will be described below with reference to FIG. First, as shown in FIG. 2A, p-type ions such as Be and Mg are implanted into the surface of the semi-insulating GaAs substrate 11 at an acceleration energy of 200 keV and an implanted ion density of 2 × 10 ¹² / cm ² to form a p layer. 12 is formed. Next, as shown in FIG. 2B, an n-type active layer 13 is formed by implanting n-type ions, for example, Si at an acceleration energy of 100 keV and an implanted ion density of 5 × 10 ¹² / cm ² .
[0015]
Next, as shown in FIG. 2 (c), the surface of the GaAs substrate 11 is covered with a photoresist 14, and the photoresist 14 is opened in a region where a source region and a drain region are to be formed by photolithography. 14 is used as a mask, and n-type ions such as Si are selectively implanted through the mask opening at an acceleration energy of 180 keV and an implanted ion density of 1 × 10 ¹³ / cm ² to form an n ⁺ region 15 (source region and drain region). . Thereafter, as shown in FIG. 2D, the source electrode 16 and the drain electrode 17 are formed on the n ⁺ region 15 using a metal made of Au—Ge, and the both electrodes 16 and 17 are alloyed by heat treatment. Then, an ohmic junction is formed on the n ⁺ region 15.
[0016]
Next, a resist film 19 is formed on the surface of the GaAs substrate 11, and photolithography is performed. As shown in FIG. 2E, the resist film 19 has an opening 20 having a width equal to the gate length and having an inversely tapered shape. I'm going to Next, the recess 18 is formed by dipping in a phosphoric acid-based etching solution.
[0017]
After that, as shown in FIG. 2 (f), 300 μm thick Pt, 200 μm thick Mo, 1000 μm thick Ti, film is formed on the active layer 13 through the opening 20 of the resist film 19 by vapor deposition. A gate electrode metal layer 21 made of Pt having a thickness of 500 、 and Au having a thickness of 3500 Å is sequentially deposited. At this time, when vapor-depositing the lowermost Pt layer, the vapor deposition rate (deposition) is set to 2 to 20 Å / sec. The metal layer 21 for gate electrode made of Pt / Mo / Ti / Pt / Au thus deposited on the resist film 19 is peeled off (lifted off) together with the resist film 19, and as shown in FIG. 2 (g) and FIG. A gate electrode 22 made of Pt / Mo / Ti / Pt / Au is formed.
[0018]
Thereafter, the GaAs substrate 22 is heat-treated at about 380 ° C. for 1 minute. When heat treatment is performed, as schematically shown in FIGS. 4A and 4B, the lowermost layer of Pt diffuses into GaAs and reacts with GaAs to form an alloy, thereby generating a compound such as PtAs or PtGa. In this heat treatment step, Pt diffuses into the active layer by about 500Å, reacts with GaAs in a solid phase to generate a reaction layer 23 containing PtAs, PtGa, and the like, and the gate electrode 22 and Schottky junction are formed with the active layer 13. As a result, as shown in FIG. 2 (h), a Pt gate FET 24 having a Pt buried type gate electrode 22 of a good Schottky junction made of a reaction layer (PtAs, PtGa) / Mo / Ti / Pt / Au. Is formed.
[0019]
(Features of this embodiment)
In the Pt gate FET manufactured by the above process, the gate electrode is made of Pt (or reaction layer) / Mo / Ti / Pt / Au. Among these, the lowermost Pt layer reacts with the active layer as described above, generates a reaction layer made of PtAs, PtGa, or the like to form a buried gate electrode, and realizes a good Schottky junction. is there.
[0020]
In the manufacturing method of the present invention, it is not always necessary that the Pt layer at the lowest layer of the gate electrode is diffused into GaAs and completely reacted with GaAs. However, as described below, it is necessary to completely react with GaAs. preferable.
[0021]
If a Pt layer that does not react with GaAs remains, or if a metal other than Pt diffuses into GaAs and reacts with GaAs, the reaction layer changes due to heat in the heat treatment process or heat during device operation, and device characteristics It varies, becomes unstable, or deteriorates. On the other hand, if the reaction layer is formed by completely reacting the Pt layer formed on the active layer with GaAs, in the subsequent process after the formation of the gate electrode, the heat treatment temperature is equal to or higher than the heat treatment temperature of the gate electrode. Even at the heat treatment temperature, the reaction between the Pt layer and GaAs does not proceed any further, and the device characteristics do not change. In particular, the pinch-off voltage of the element does not fluctuate. Similarly, there is no possibility that the device characteristics such as the pinch-off voltage change and become unstable due to heat generation during device operation. Therefore, it is desirable that the lowermost Pt layer is completely reacted with GaAs.
[0022]
Further, according to the manufacturing method of the present invention, the lowermost Pt layer of the gate electrode is formed by a vapor deposition method at a vapor deposition rate (deposition) of 2 to 200 Å / sec. By forming the Pt layer at a deposition rate of 20 Å / sec or less, a Pt layer having a low film stress could be formed on the GaAs substrate, and a Pt layer having good adhesion could be formed. On the other hand, when the deposition rate was 20 Å / sec or more, a film having a large stress was formed, and film peeling occurred partially or entirely.
[0023]
FIG. 5 shows the result of inspecting the peeling rate by changing the deposition rate of the Pt layer to 100 Å / sec. As can be seen from FIG. 5, when the deposition rate is 20 蒸 着 / sec or less, the peeling rate is almost 0, whereas when it exceeds 20 Å / sec, the peeling rate increases rapidly. Therefore, when the deposition rate of the Pt layer is 20 Å / sec or less, film peeling of the Pt layer can be made difficult to occur, and the yield of the semiconductor device can be improved.
[0024]
Moreover, since the film thickness control of the Pt film is facilitated by slowing down the deposition rate in this way, the film thickness variation hardly occurs even if the thin Pt film is formed, and the pinch-off voltage Vp, the saturation drain current Idss, etc. The characteristics can be stabilized.
[0025]
On the other hand, if the deposition rate of the Pt layer is made slower than 2 Å / sec, the film thickness cannot be easily controlled, and the amount of Pt diffused into the semiconductor substrate fluctuates and the device characteristics such as the pinch-off voltage vary. Accordingly, the deposition rate of the Pt layer is desirably 2 to 200 liters / sec.
[0026]
In order to perform heat treatment of the gate electrode satisfactorily, it is preferable that the thickness of the Pt layer, the structure of the active layer, and the like are as follows.
[0027]
(Pt layer thickness)
Here, in order for the Pt layer to completely react with the active layer by heat treatment, it is necessary to reduce the thickness of the Pt layer. According to the prototype, the thickness of the Pt layer is preferably 500 mm or less. In particular, in the above embodiment, the thickness of the Pt layer is set to 250 mm as an optimum value. As the thickness of the Pt layer increases, not only does the heat treatment time for completely reacting the Pt layer with the active layer increase, but also when the same pinch-off voltage is realized as the thickness of the Pt layer increases, the mutual conductance gm rises. The steepness also decreases, and when the film thickness increases, the film stress of the Pt layer increases and the adhesion to the GaAs substrate also deteriorates.
[0028]
On the other hand, if the thickness of the Pt layer is less than 100 mm, it is difficult to control the thickness with the current technology, and Pt is not sufficiently diffused, so that a good Schottky junction cannot be obtained. The thickness of the layer is preferably 100 mm or more. From the above, the film thickness of the Pt layer is desirably 100 to 500 mm.
[0029]
(Diffusion depth of Pt layer)
When the Pt layer is completely diffused into the active layer by heat treatment, it is important to control the pinch-off voltage Vp to a desired value. Here, when the Pt layer is diffused to the active layer by about twice its thickness, the reaction layer becomes thermally stable and reliable when the thickness of the reaction layer becomes about twice the thickness of the Pt layer. It has been experimentally found that the device characteristics are stabilized.
[0030]
(Relationship between thickness of active layer and film thickness of Pt layer)
Further, the thickness of the active layer before the heat treatment is preferably 2 to 10 times the thickness of the Pt layer thereon. Since the diffusion depth of the Pt layer is preferably about twice the film thickness of the Pt layer, in order to prevent the entire active layer from being blocked by the reaction layer, the thickness of the active layer is 2 times the film thickness of the Pt layer. More than double is required. The thickness of the active layer becomes more than 10 times the thickness of the Pt layer, the steepness of the rise of the transconductance g _m is deteriorated characteristics of the device decreases.
[0031]
(Function of Mo layer)
The Mo layer acts as a diffusion barrier layer, ensuring that the Pt layer reacts completely with the active layer and prevents reaction of other metals with the active layer.
[0032]
As described above, in order to produce a stable Pt gate FET with small manufacturing variations, the diffusion of the gate electrode to the active layer is stopped when the Pt layer is completely diffused into the active layer and the reaction layer is formed. Therefore, it is necessary to prevent metals other than Pt from diffusing into the active layer. First, since Mo hardly reacts with GaAs, as shown in FIG. 4B, the reaction between the gate electrode and the active layer occurs when the Pt layer reacts with the active layer and the reaction layer contacts the Mo layer. Stops. Further, since Mo is a diffusion barrier layer that blocks the diffusion of other metals, it prevents Ti, Au, etc. from diffusing into the active layer or reaction layer and changing device characteristics such as the pinch-off voltage Vp. Furthermore, since the Mo layer also prevents the lowest Pt from diffusing into the Ti layer, the amount of Pt layer diffusing into the Ti layer and diffusing into GaAs fluctuates, resulting in variations in the depth of the reaction layer. Can be prevented. Therefore, by forming a Mo layer having a certain thickness on the Pt layer, the required accuracy such as process control and processing time management for completely reacting only the Pt layer with the active layer is eased. .
[0033]
This Mo layer is also formed thin like the Pt layer, and has a thickness of 200 mm in the above embodiment. Since the Mo layer has a large film stress, when the gate length is short, the adhesion becomes poor when a thick film is formed. Therefore, the thickness of the Mo layer is reduced.
[0034]
The Ti layer is for assisting the diffusion preventing effect of the thin Mo layer. In order to suppress diffusion of the upper Au and Al layers into the Pt / GaAs reaction layer, the Ti layer and the intermediate Pt. It is essential to improve the adhesion to the layer.
[0035]
In addition, since W, Ta, Cr, etc. are known as such a diffusion barrier, metals such as W, Ta, Cr, etc. may be used as the diffusion barrier layer instead of the Mo layer.
[0036]
(Other metal layers)
The uppermost Au layer is a layer for reducing the resistance of the gate electrode and has the largest film thickness. That is, in the above embodiment, the film thickness is 3500 mm. Therefore, Al having a small specific resistance may be used instead of the Au layer.
[0037]
The intermediate Pt layer on the Ti layer functions as a diffusion barrier that prevents the reaction between Ti and Au. Cr may be used instead of Pt.
[0038]
When the gate length is short, if a thick Mo film is stacked on the lowermost Pt layer, there is a problem of adhesion, etc., and it is difficult to stack a thick Mo film. It becomes impossible to prevent mutual diffusion between the layer and the Ti layer. Therefore, in the above gate structure, the Mo film is made very thin by facilitating the formation of the Mo film, and further, interdiffusion is prevented by the intermediate Pt layer and Ti layer. It is important to improve the adhesion of
[Brief description of the drawings]
FIGS. 1A to 1D are schematic cross-sectional views showing manufacturing steps of a conventional Pt gate FET.
FIGS. 2A to 2H are schematic cross-sectional views showing a manufacturing process of a Pt gate FET according to an embodiment of the present invention.
FIG. 3 is a schematic enlarged sectional view showing a gate electrode formed on an active layer.
FIGS. 4A and 4B are diagrams schematically showing that a Pt layer on an active layer is diffused into GaAs and alloyed.
FIG. 5 is a graph showing the relationship between the deposition rate of Pt and the peel rate of the Pt layer.
[Explanation of symbols]
11 Semi-insulating GaAs substrate 13 Active layer 16 Source electrode 17 Drain electrode 22 Gate electrode 23 Reaction layer

Claims (5)

In a manufacturing method of a semiconductor device in which a Schottky electrode including at least a lowermost layer of Pt is formed on a semiconductor substrate, and the Pt layer and the semiconductor substrate are subjected to a Schottky junction by heat-treating the Schottky electrode.
A method of manufacturing a semiconductor device, comprising depositing Pt in the lowermost layer of the Schottky electrode on a semiconductor substrate at a deposition rate of 20 Å / sec or less. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a deposition rate of the lowermost layer Pt is 2 Å / sec or more. 2. The Schottky electrode according to claim 1, wherein a Mo layer is formed on the Pt layer, a Ti layer is formed thereon, and a low resistance metal layer is formed thereon. The manufacturing method of the semiconductor device of description. 2. The method of manufacturing a semiconductor device according to claim 1, wherein, of the lowermost Pt layer, Pt in a region in contact with the active layer is completely reacted with the active layer. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a compound semiconductor substrate.

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