JP3631391B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a dry etching method for forming a recess having a depth value larger than the size of an opening in a semiconductor substrate or an insulating film on the semiconductor substrate.
[0002]
[Prior art]
Conventionally, when forming a recess (hereinafter referred to as a high aspect ratio trench) having a depth value larger than the size of the opening in the semiconductor substrate, first, a deep trench reaching the surface of the semiconductor substrate is formed on the insulating film on the semiconductor substrate. And forming a high aspect ratio trench in a semiconductor substrate using the deep trench as an etching mask.
[0003]
The formation of a deep trench in an insulating film is usually performed using a resist as a mask. At this time, a high aspect ratio etching of a thick insulating film with a high-resolution thinning resist is required. Etching of this thick insulating film is usually performed by a dry etching method using a fluorine-based gas, but in order to perform etching at a high aspect ratio, it is necessary to perform etching for a long time under the condition of applying high power and high frequency. Needed.
[0004]
For this reason, the temperature of the object to be processed rises during etching, and an etching product made of fluoride adhering to the upper portion of the resist is caused to move around the trench opening due to heat, and a normal scallop ( A concavo-convex shape called a scallop concavo-convex shape is generated.
[0005]
The unevenness of the opening is transferred to the inside of the trench in the trench processing, and if the trench is formed in the silicon substrate using the interlayer insulating film on which the scallop is generated as an etching mask, the high aspect ratio trench formed in the silicon substrate. Since the scallop is further transferred to the inside of the trench, a concavo-convex shape is also generated inside the trench, which causes a leak current in the trench capacitor portion formed inside the trench.
[0006]
With the progress of microfabrication technology, interlayer insulation film masks for forming high aspect ratio trenches on silicon substrates have been required to be high aspect ratio etching masks. Since the resist mask used at this time is thinned, it has been extremely difficult to form a deep trench in the interlayer insulating film with the resist mask in relation to the so-called film reduction problem.
[0007]
[Problems to be solved by the invention]
As described above, in forming a high aspect ratio etching mask made of, for example, an interlayer insulating film, which is conventionally used for forming a deep trench in a silicon substrate, the etching of the high aspect ratio becomes extremely difficult due to the thinning of the resist mask. There was a problem of becoming.
[0008]
The present invention has been made to solve the above-described problems. A semiconductor using a new high aspect ratio dry etching, which is easy to perform fine processing in forming an etching mask and replaces high aspect ratio etching using a resist mask. An object is to provide a method for manufacturing a device.
[0009]
[Means for Solving the Problems]
In the method for manufacturing a semiconductor device of the present invention, in the formation of an etching mask having a high aspect ratio made of an insulating film, a pillar made of silicon single crystal or polycrystalline silicon (hereinafter referred to as polysilicon) is formed on a silicon substrate. An insulating film is formed so as to embed, and the top of the pillar is exposed on the top surface of the insulating film by planarizing the insulating film, and the pillar is etched away from the top using anisotropic dry etching. Thus, a high aspect ratio trench is formed in the interlayer insulating film.
[0010]
Specifically, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a silicon substrate and forming an opening reaching the surface of the silicon substrate in the first insulating film; Forming a silicon portion on the silicon substrate having the same cross-sectional shape as the opening, and forming a second insulating film so as to cover the silicon portion, and the surface of the second insulating film. And a step of exposing the silicon portion by using the surface of the second insulating film as an etching mask.
[0011]
Preferably, the silicon portion is made of silicon formed by selective epitaxial growth on a silicon substrate.
[0012]
More preferably, in the selective epitaxial growth, a metal film is selectively formed on a silicon substrate, the metal film is subjected to a heat treatment and melted, and the silicon portion is formed on the silicon substrate through the melted metal film. It is characterized by that.
According to a method of manufacturing a semiconductor device of the present invention, a step of forming a first insulating film on a silicon substrate, forming an opening in the first insulating film, and forming the opening on the first insulating film. A process of depositing a polysilicon film so as to be embedded and planarizing the surface of the polysilicon film, and forming an etching mask on the planarized polysilicon film in accordance with the position of the opening, and using this etching mask Anisotropically etching the planarized polysilicon film;
A second insulating film is formed so as to cover a silicon portion made of a part of the polysilicon film formed by this anisotropic etching, and the silicon portion is exposed by flattening the surface of the second insulating film. And a step of etching and removing the silicon portion using the second insulating film as an etching mask.
[0013]
Preferably, the first and second insulating films from which the silicon portions have been removed by etching are used as etching masks for forming recesses in the silicon substrate.
[0014]
Preferably, the recess provided in the silicon substrate is used for forming a capacitor of a semiconductor device.
[0015]
Preferably, the second insulating film or the polysilicon film is planarized by a CMP (Chemical Mechanical Polish) method.
[0016]
As described above, when forming an etching mask made of an interlayer insulating film or the like, the dry etching according to the present invention performs anisotropic etching of a column made of single crystal or polysilicon instead of high aspect ratio trench processing using a resist mask. By using this method, it is possible to prevent the formation of a scallop shape inside the deep trench formed in the silicon substrate, and to process the deep silicon trench with good controllability.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0018]
1 to 4 are sectional views showing a manufacturing process for forming a deep trench in a silicon substrate according to the first embodiment of the present invention. As shown in FIG. 1A, the surface of the silicon substrate 1 is thermally oxidized to form a silicon thermal oxide film 2 made of SiO ₂ , and this thermal oxidation is subsequently performed by a normal CVD (Chemical Vapor Deposition) method. A nitride film 3 made of Si ₃ N ₄ is formed on the film. Here, the thermal oxide film 2 is a buffer layer for improving the adhesion between the silicon substrate 1 and the nitride film 3.
[0019]
Next, an antireflection film 4 made of, for example, polysilane and a resist 5 are applied on the silicon nitride film 3 to form post-exposure resist openings 5a. Here, the antireflection film 4 prevents reflection of light used for exposure from the surface of the silicon substrate, and serves to form the opening 5a with high resolution.
[0020]
Next, as shown in FIG. 5B, an anti-reflection film is formed using a normal reactive ion etching method (hereinafter referred to as RIE; Reactive Ion Etching) using the resist 5 having the opening 5a as an etching mask. 4, the nitride film 3 and the thermal oxide film 2 are opened, and the surface 6 of the silicon substrate 1 is exposed at the bottom of the opening. After the opening reaching the surface of the silicon substrate 1 is formed in this way, the resist 5 and the antireflection film 4 are peeled off as shown in FIG.
[0021]
Next, as shown in FIG. 2 (d), an Au film was deposited on the entire surface, and subsequently, as shown in FIG. 2 (e), the nitride film 3 was deposited on top of the nitride film 3 using ordinary CMP as a stopper. The Au film 7 is removed.
[0022]
Thus, the silicon substrate 1 in which the Au film 7 remains only in the opening is inserted into a normal epitaxial growth apparatus shown in FIG. 10, and silicon pillars are epitaxially grown from the silicon substrate surface via the Au film 7.
[0023]
The epitaxial growth apparatus shown in FIG. 10 includes a gas introduction pipe 13, a workpiece 14 installed on an installation table 15, a heater 16, a temperature adjustment mechanism 17, and an exhaust port 18. FIG. 10 schematically shows a basic configuration of a normal CVD epitaxial apparatus. The growth of the silicon pillar of the present invention does not require any new growth apparatus, and can be performed using a normal CVD epitaxial apparatus as it is.
[0024]
The silicon substrate 1 (silicon wafer) that has completed the steps up to FIG. 2 (e) is placed on an installation table 15 having a heater 16 and a temperature adjustment mechanism 17 as an object to be processed 14, and the chamber shown in FIG. Evacuate to a vacuum.
[0025]
Next, the temperature of the installation base is set to 950 ° C., and the Au film 7 is reacted with the surface of the silicon substrate 1 as shown in FIG. Au 8 containing Si is formed by melting so as to cover the surface of the silicon substrate 1 in the opening.
[0026]
After forming the Au-Si liquid phase alloy layer, a mixed gas of about 1/50 (molar ratio) of SiCl ₄ / H _{2 with a} pressure of 1 atm and a total gas flow rate of 1 (l / min) using H ₂ as a carrier gas is used. A columnar silicon single crystal 9 is grown through Au8 containing Si as shown in FIG. 3G by flowing into the chamber using the gas introduction pipe 13 and the exhaust pipe 18.
[0027]
At this time, the growth rate in the vertical direction of the silicon single crystal 9 is about 5 mg / cm ² , and the columnar silicon single crystal 9 is easily formed with the silicon substrate surface 6 exposed at the bottom of the opening 5a in FIG. can do. That is, if the opening 5a is circular, the cross section of the column is also circular, and if it is rectangular, a column having a rectangular cross section is obtained.
[0028]
In this way, the columnar silicon single crystal 9 having an arbitrary cross-sectional shape can be formed on the silicon substrate 1. For example, the silicon single crystal 9 having a circular cross section having a diameter of about 30 μm and a length of about 600 μm can be easily obtained by the above-described method, and the diameter of the column is almost constant over the length direction.
[0029]
The growth rate of 5 mg / cm ² is constant even when the value of the diameter changes, and by using this method, the columnar silicon single crystal 9 having various cross-sectional shapes and cross-sectional areas can be formed with high controllability. It was confirmed that
[0030]
The growth of the silicon single crystal 9 is performed through the Au 8 containing Si at the top of the silicon single crystal 9, but during the growth of the silicon single crystal 9, the Au 8 containing Si is not necessarily in a liquid phase and has a Si content. As it increases, it approaches the solid phase. The high-speed growth of the columnar silicon single crystal seems to proceed by high-speed diffusion and precipitation of Si from solid-phase Au containing a large amount of Si.
[0031]
After the columnar silicon single crystal 9 is grown on the silicon substrate 1 in this way, a thick silicon oxide film 10 (usually called a P-TEOS film) made of plasma SiO ₂ using well-known TEOS (Tetraethylorthosilicate) is used. (Usually used for forming an interlayer insulating film) is formed as shown in FIG. At this time, the thickness of the silicon oxide film 10 is set so that the silicon single crystal 9 and the Au 8 containing Si are completely embedded.
[0032]
Next, the surface of the silicon oxide film 10 is planarized by normal CMP. This planarization process is further advanced, and the Au 8 containing Si on the silicon single crystal 9 is removed as shown in FIG.
[0033]
Subsequently, if the silicon single crystal 9 is anisotropically etched under a RIE condition for etching a silicon substrate having a high etching selectivity to the silicon oxide film, a high aspect ratio composed of the silicon oxide film 10, the silicon nitride film 3, and the thermal oxide film 2 is obtained. Ratio etching masks can be formed.
[0034]
Further, if the anisotropic etching of the silicon substrate 1 by RIE is further advanced, a deep trench having a high aspect ratio can be easily formed in the silicon substrate 1 as shown in FIG.
[0035]
According to the etching mask forming method of the first embodiment, a high aspect ratio etching mask made of a thick insulating film is formed without using a resist. Occurrence of a scallop shape can be completely avoided.
[0036]
Therefore, if a trench having a high aspect ratio is formed in a silicon substrate using the etching mask, scallop-like irregularities are not generated in the trench, and a highly reliable trench capacitor with a small leakage current can be obtained.
[0037]
Further, when the etching mask having a high aspect ratio is formed, the thickness of the etching mask made of an insulating film is controlled by the height of the columnar silicon single crystal 9 having high controllability. In particular, there is a feature that can significantly increase the dimensional accuracy of an important part.
[0038]
In the first embodiment, the patterning of the Au film 7 was performed by forming the opening of the nitride film 3, vapor-depositing the entire surface of the Au film, and removing the Au film deposited outside the opening by CMP. However, it is not necessarily limited to this method.
[0039]
For example, an Au film having a thickness of 20 nm is directly deposited on the surface of the silicon substrate 1, a positive resist (LP-14A) having a thickness of 10 μm is applied on the entire surface, an opening is provided, and Au is deposited on the bottom of the opening. A part of the film is exposed, and Au plating is further performed on the Au vapor-deposited film exposed on the bottom surface of the opening under the conditions of 42 ° C. and 0.5 mA / cm ² using a KAu (CN) ₂ solution. Patterning of the Au film 7 corresponding to FIG. 2 may be performed by a method in which the Au vapor deposition film other than the opening is etched away at room temperature using a HCl and HNO ₃ mixed solution.
[0040]
At this time, although the thermal oxide film 2 and the nitride film 3 do not exist, the growth of the silicon single crystal 9 shown in FIG. 3G and the subsequent manufacturing steps can be performed as they are. In the first embodiment, a Si (111) ± 0.5 degree off wafer was used as the silicon substrate, Au deposition conditions were 10 ⁻⁵ Torr, and substrate heating was 200 ° C.
[0041]
Further, when forming a high aspect ratio etching mask, P-TEOS was used to form the silicon oxide film 10, but other methods such as plasma, reduced pressure, atmospheric pressure CVD and HDP (High Density Plasma) are used. Can do. Organic and inorganic oxide films formed by a coating type apparatus can also be used. In this case, since it is a coating type, flattening is easy.
[0042]
Next, a second embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 5A, a thermal oxide film 2 is formed on a silicon substrate 1, and a silicon nitride film 3 is formed by laminating it. Here, the thermal oxide film 2 serves as a buffer layer for improving the adhesion between the silicon substrate 1 and the silicon nitride film 10 as in the first embodiment.
[0043]
Next, a silicon oxide film 10 is formed on the silicon nitride film using a CVD method. This silicon oxide film 10 is provided in order to improve the adhesion to the polysilicon film formed in the next step and to serve as a dry etching stopper shown in the subsequent step. Subsequently, the antireflection film 4 and the resist 5 are applied, and openings 5a are formed in the resist in a pattern.
[0044]
Next, as shown in FIG. 5B, the antireflection film 4, the silicon oxide film 10, the silicon nitride film 3, and the thermal oxidation are performed using normal RIE anisotropic etching and using the resist opening 5 a as a mask. The film 2 is removed by etching, the surface 6 of the silicon substrate 1 is exposed on the bottom surface of the opening 5, and the resist 5 and the antireflection film 4 are peeled off to remove the multilayer insulating film as shown in FIG. An opening is formed.
[0045]
Next, as shown in FIG. 6D, a thick polysilicon film 12 is formed so as to fill the opening. Here, the thickness of the polysilicon film 12 is set to be equal to or greater than the thickness of the target high aspect ratio etching mask. Subsequently, as shown in FIG. 6E, the surface of the polysilicon film 12 is flattened by CMP so that the thickness thereof becomes equal to the thickness of the etching mask.
[0046]
After the antireflection film 4 and the resist 5 are further applied on the polysilicon film 12 thus flattened, as shown in FIG. 7F, the antireflection film 4 and the resist film 4 are aligned with the opening. A pattern is formed with the resist 5.
[0047]
Next, using the resist 5 as a mask, a columnar silicon portion made of the polysilicon film 12 is formed as shown in FIG. At this time, the silicon oxide film 10 is used as a stopper for anisotropic etching.
[0048]
As shown in FIG. 8H, after the resist 5 and the antireflection film 4 at the top of the pillar are peeled off, a pillar-shaped silicon portion made of the polysilicon film 12 is embedded as shown in FIG. As shown in FIG. 9J, the surface of the silicon oxide film 10 is flattened by CMP so that the silicon at the top of the pillar is exposed.
[0049]
Next, as shown in FIG. 9 (k), RIE anisotropic etching is performed using a high aspect ratio etching mask composed of the silicon oxide film 10, the silicon nitride film 3, and the thermal oxide film 2. The process for forming the deep trench is exactly the same as in the first embodiment. The silicon oxide film 10 formed on the nitride film 3 is used as a part of the silicon oxide film 10 that serves as an etching mask together with the silicon nitride film 3.
[0050]
In the second embodiment, since the silicon single crystal 9 in the first embodiment is replaced with the polysilicon 12, the scallop shape formed on the silicon substrate 1 is avoided. Needless to say, it is included in
[0051]
The present invention is not limited to the above embodiment. For example, in the first embodiment, it has been described that a silicon single crystal is selectively epitaxially grown on a silicon substrate via Au containing Si, but Au is not necessarily used.
By using a material that can contain a large amount of Si at a lower temperature than the direct vapor deposition temperature on silicon, a columnar silicon single crystal can be selectively epitaxially grown. Further, the same processing technique advantage can be obtained by using a method capable of growing a silicon whisker corresponding to a desired trench shape on a silicon substrate without necessarily using a metal as a medium. Various other modifications can be made without departing from the scope of the present invention.
[0052]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, when forming a high aspect ratio etching mask for forming a deep trench in a silicon substrate, a columnar silicon portion made of single crystal or polycrystal is formed on the semiconductor substrate. After the formation, the silicon part is filled with an insulating film, the surface of the insulating film is flattened, and at the same time, the top of the silicon part is exposed, and this silicon part is selectively anisotropically etched to provide high dimensional accuracy and control. It is possible to easily provide a desired etching mask that is excellent in performance and suitable for fine processing.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view showing a first embodiment of the present invention,
(A) is a figure which shows the opening part of a resist.
(B) is a figure which shows the opening part which reaches the silicon substrate surface.
(C) is a figure which shows the opening part after a resist and antireflection film peeling.
FIG. 2 is a process cross-sectional view showing the continuation of the first embodiment of the present invention,
(D) is a figure which shows the state after vapor-depositing Au film | membrane.
(E) is a figure which shows the state after CMP.
(F) is a figure which shows the state after heat processing.
FIG. 3 is a process sectional view showing the continuation of the first embodiment of the present invention,
(G) is a figure which shows columnar silicon single crystal formation.
(H) is a view showing a silicon single crystal embedded state by an oxide film,
FIG. 4 is a process sectional view showing a continuation of the first embodiment of the present invention,
(I) is a figure which shows the state after CMP.
(J) is a figure which shows trench formation of a silicon substrate.
FIG. 5 is a process cross-sectional view showing a second embodiment of the present invention,
(A) is a figure which shows the opening part of a resist.
(B) is a figure which shows the opening part which reaches the silicon substrate surface.
(C) is a figure which shows the opening part after a resist and antireflection film peeling.
FIG. 6 is a process sectional view showing the continuation of the second embodiment of the present invention,
(D) is a diagram showing a state after polysilicon film formation.
(E) is a diagram showing a state of the polysilicon film after CMP.
FIG. 7 is a process sectional view showing a continuation of the second embodiment of the present invention,
(F) is a figure which shows the state after resist pattern formation.
(G) is a figure which shows formation of columnar polysilicon.
FIG. 8 is a process sectional view showing the continuation of the second embodiment of the present invention,
(H) is a figure which shows the state after resist peeling.
(I) is a figure which shows the embedding state of the columnar polysilicon by an oxide film.
FIG. 9 is a process sectional view showing the continuation of the second embodiment of the present invention,
(J) is a diagram showing a state after CMP.
(K) is a figure which shows trench formation of a silicon substrate.
FIG. 10 is a schematic diagram of an epitaxial growth apparatus for silicon single crystal.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Thermal oxide film 3 ... Silicon nitride film 4 ... Antireflection film 5 ... Resist 5a ... Resist opening 6 ... Silicon substrate surface 7 ... Au film 8 ... Au containing Si
DESCRIPTION OF SYMBOLS 9 ... Silicon single crystal 10 ... Silicon oxide film 11 ... Deep silicon trench 12 ... Polysilicon 13 ... Gas introduction pipe 14 ... To-be-processed object 15 ... Installation stand 16 ... Heater 17 ... Temperature control mechanism 18 ... Exhaust pipe

Claims (7)

Forming a first insulating film on the silicon substrate, and forming an opening reaching the surface of the silicon substrate in the first insulating film;
Forming on the silicon substrate a silicon portion having a cross-sectional shape equal to the opening from the opening reaching the silicon substrate surface;
Forming a second insulating film so as to cover the silicon portion, and exposing the silicon portion by planarizing a surface of the second insulating film;
Etching the silicon portion using the second insulating film as an etching mask;
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon portion is made of silicon formed by selective epitaxial growth on the silicon substrate. In the selective epitaxial growth, a metal film is selectively formed on a silicon substrate, the metal film is subjected to a heat treatment and melted, and the silicon portion is formed on the silicon substrate through the melted metal film. The method of manufacturing a semiconductor device according to claim 2, wherein: Forming a first insulating film on the silicon substrate and forming an opening in the first insulating film;
Depositing a polysilicon film on the first insulating film so as to fill the opening, and planarizing the surface of the polysilicon film;
Forming an etching mask on the planarized polysilicon film in accordance with the position of the opening, and anisotropically etching the planarized polysilicon film using the etching mask;
A second insulating film is formed so as to cover a silicon portion made of a part of the polysilicon film formed by this anisotropic etching, and the surface of the second insulating film is planarized to thereby form the silicon portion. An exposure process;
Etching the silicon portion using the second insulating film as an etching mask;
A method for manufacturing a semiconductor device, comprising: The said 1st and 2nd insulating film from which the said silicon part was removed by etching is used as an etching mask for providing a recessed part in the said silicon substrate, The Claim 1 characterized by the above-mentioned. Semiconductor device manufacturing method. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the recess provided in the silicon substrate is used for forming a capacitor of the semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the planarization of the second insulating film or the polysilicon film is performed by a CMP method.

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