JP3631616B2 - Staff synchronous multiplex communication equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital communication device that has a clock that is a reference in each country and performs international digital communication, and more particularly to a staff synchronous communication device of a satellite communication system and a multistage relay system thereof.
[0002]
[Prior art]
Staff synchronous multiplex communication is adopted in digital satellite communication and international communication. Stuff synchronization means that when digital signals generated from each device are multiplexed, the signals are temporarily stored in a memory and read out with a common clock signal that is a little faster than the signal to be multiplexed, thereby converting to the same speed. Refers to the method. The difference is compensated by inserting useless pulses (stuff pulses) as necessary (see “Latest Information Communication Glossary” issued by the Telecommunications Association).
[0003]
FIG. 4 is a simple block diagram of a conventional stuff synchronous multiplex communication apparatus. The state where the 1st station and the 2nd station are connected by the staff synchronous multiplex communication apparatus is shown. The first station includes a multiplexing circuit 101 and multiplexes additional information including the input main signal a1 and stuff information bits (or stuff pulses). A phase monitoring circuit 102 to which a signal a2 of an oscillation circuit 403 that oscillates a frequency (radio frequency: ft1) higher than the main signal a1 by the amount of additional information is input. The phase monitoring circuit 102 monitors the phase difference between both signals a 1 and a 2 and inputs the signal a 3 to the multiplexing circuit 101. The output signal a4 of the multiplexing circuit 101 is sent to the second station via the propagation path.
[0004]
In the second station, a frame synchronization is established with respect to the signal a5 added with jitter through the propagation path, and a separation circuit 204 that reproduces the main signal (memory write signal) a6 and a memory circuit that accumulates the main signal a6 205. This memory circuit 205 removes jitter by reading with the output signal a8 of the oscillation circuit 206 having the frequency fr2, monitors the write phase (address) of a6 and the read phase (address) of a9, and writes and reads. When the address relationship becomes a predetermined relationship, the transmission frequency control information of a7 is transmitted.
[0005]
On the other hand, the transmitter of the second station and the receiver of the first station have the same configuration as the transmitter of the first station and the receiver of the second station, respectively. That is, the transmission unit of the second station includes a multiplexing circuit 201, a phase monitoring circuit 202, and an oscillation circuit 503. The receiving section of the first station includes a separation circuit 104, a memory circuit 105, and an oscillation circuit 106.
[0006]
In digital radio transmission, information transmission is performed by multiplexing various additional information on a main signal. For example, there are a frame synchronization signal, a digital service signal, a control signal, an alarm signal, and a coded redundant signal for error correction of a propagation path for establishing frame synchronization between the transmission and reception stations. In order to add such additional information, the transmitter of the wireless device has an oscillation circuit that oscillates a frequency (radio frequency: ft1) higher than the main signal (a1) by the additional information.
[0007]
When the radio frequency and the frequency of the main signal are in an asynchronous relationship, or when a plurality of main signals are connected from an asynchronous network, it is necessary to employ a stuff synchronization method. In the stuff synchronization method, stuff bits are allocated on a radio frame by a predetermined number of bits. The phase is adjusted by advancing or delaying the phase by assigning the stuff bit to the main signal (raw data) or making it a useless bit based on the phase monitoring result of monitoring the phase of the main signal and radio frequency. Thus, the asynchronous signal is synchronized to transmit the signal.
[0008]
On the other hand, in satellite communication that performs international communication, each country has a standard clock. The transmitted signal includes jitter due to the propagation path and the Doppler effect, and the quality is deteriorated. Therefore, it is necessary to change the signal with a stabilized reference clock possessed by each country. At this time, since the transmission clock and the reception clock are asynchronous, a slip (data loss) generally occurs at the time of clock transfer.
[0009]
The clock transfer is realized by writing to the memory circuit with the transmitted clock and reading with the reference clock on the receiving side. This memory circuit is called Doppler Purejiokuro eggplant buffer, slip frequency is determined by the frequency difference between the memory capacity M (bits) (fw-fr) (Hz ). Due to this slip, the signal is interrupted, and the sound and the image are disturbed.
[0010]
[Problems to be solved by the invention]
In the prior art, since the oscillation frequencies ft1 and ft2 of the oscillation circuits 403 and 503 in FIG. 4 are fixed, the slip occurs as described above.
Further, in the international communication has a reference clock stabilized with various countries, since the country is configured to operate at clock its stabilization (Purejiokuro eggplant operation), frequency and synchronization of digital signals from the transmission countries However, since the reproduction is performed using the stabilized reference clock independently possessed by the receiving country, there is a problem that slip (data loss) occurs.
[0011]
Accordingly, an object of the present invention is to provide a stuff synchronous multiplex communication device that improves the transmission effect and transmission quality of international communication by reducing the slip frequency determined by the buffer memory capacity and the frequency difference between transmission and reception stations. There is to do.
[0012]
[Means for Solving the Problems]
In order to solve the above-described problem, a stuff synchronous multiplex communication apparatus according to the present invention has the following characteristic configuration.
[0013]
(1) In a stuff synchronous multiplex communication device having a transmitting unit and a receiving unit in a first station and a second station connected via a propagation path,
The first station and the second station operate based on asynchronous clock frequencies for transmission processing and reception processing, respectively .
Memory means for absorbing jitter at the receiving station;
Comparison determination means for monitoring write and read addresses to the memory means and determining advance or delay with respect to a preset address relationship;
A transmission unit that transmits a control signal based on a determination result of the comparison determination unit to a game using a radio time slot;
A stuff synchronous multiplex communication device comprising: a transmission frequency variable means for controlling a transmission frequency based on the control signal of the transmission means.
[0014]
(2) The stuff synchronous multiplex communication apparatus according to (1), wherein the memory means of the receiving station performs a pre-geochronous operation using a reference clock that is asynchronous with respect to the clock of the transmitting station.
[0015]
(3) By speeding up processing time for variably controlling the transmission frequency, stuff synchronization multiplex communication apparatus to shorten the transmission delay time while reducing the memory capacity of said memory means for performing Purejiokuro eggplant operation (2).
[0016]
(4) The stuff synchronous multiplex communication apparatus according to (1), (2) or (3), wherein a satellite and a ground wireless communication line are connected in multiple stages as the propagation path.
[0017]
(5) The variable control of the transmission frequency is performed based on the absolute value of the difference between the values obtained by latching the write and read addresses of the memory means at the frame pulse timing (1), (2), (3) or (4 ) Staff synchronous multiplex communication device.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a preferred embodiment of a staff synchronous multiplex communication apparatus according to the present invention will be described in detail with reference to the accompanying drawings.
[0019]
First, a description will be given with reference to FIG. 1 showing a block diagram of an embodiment of a staff synchronous multiplex communication apparatus of the present invention. Since this stuff synchronous multiplex communication apparatus uses the same elements as those of the conventional apparatus of FIG. 4, the corresponding reference numerals are assigned to the corresponding elements.
[0020]
The transmission unit of the first station includes a multiplexing circuit 101 and a phase monitoring circuit 102. The receiving unit also includes a separation circuit 104, a memory circuit 105, and an oscillation circuit 106. On the other hand, the receiving unit of the second station includes the separation circuit 204, the memory circuit 205, and the oscillation circuit 206, and the transmission unit includes the multiplexing circuit 201 and the phase monitoring circuit 202, and is the same as the conventional apparatus of FIG. It is.
[0021]
However, as apparent from the comparison of the block diagrams of FIGS. 1 and 4, the stuff synchronous multiplex communication apparatus of the present invention shown in FIG. 1 has the following differences. The separation circuit 104 of the reception unit of the first station separates a16 in the additional information, and controls the oscillation frequency of the oscillation circuit 103 of the transmission unit based on this a16. Further, the oscillation circuit 203 of the transmission unit of the second station inputs the oscillation signal a11 controlled by a12 to the phase monitoring circuit 202.
[0022]
Next, in the stuff synchronous multiplex communication apparatus having the configuration shown in FIG. 1, the first station and the second station facing each other are connected to the stuff synchronous multiplex communication apparatus, and the signal transmitted by the first station is stabilized in the second station. The procedure for reading with the reference clock will be described.
[0023]
The transmission unit of the first station can change the oscillation frequency ft1 by a multiplexing circuit 101 that multiplexes additional information including stuff information bits into the input main signal a1 and a control signal from the opposite station (second station). It has an oscillation circuit 103 and a phase monitoring circuit 102 that monitors the phase difference between a1 and a2.
[0024]
On the other hand, the receiving section of the second station establishes frame synchronization for the fixed oscillation circuit 206 that oscillates a stable reference clock (ft2) a8 and a5 to which jitter is added by the propagation path, and separates additional information. The stuff bit can be recognized by the stuff information bit “1” or “0” to determine whether the main signal is a useless bit, and the main signal (the separation circuit 204 for reproducing the memory write signal a6 and the jitter by reading it with a8) The memory circuit 205 monitors the write phase (address) of a6 and the read phase (address) of a9, and sends the transmission frequency control information of a7 when the write and read address relationship becomes a predetermined relationship. Have
[0025]
On the other hand, the transmitter of the second station has the same configuration as the transmitter of the first station. That is, the multiplexing circuit 201 is the same as 101, and also multiplexes a control signal a7 that changes the transmission frequency of the first station as additional information. The phase monitoring circuit 202 and the oscillation circuit 203 have the same functions as 102 and 103, respectively, and the signals a14 and a15 are equivalent to a4 and a5, respectively.
[0026]
The receiving unit of the first station is the same as the receiving unit of the second station, and the separation circuit 104 separates a16 in the additional information and inputs it to the oscillation circuit 103 of the transmission unit, and the oscillation frequency of the oscillation circuit 103 To control. The output of the separation circuit 104 is stored in the memory circuit 105.
[0027]
Next, the operation or function of the staff synchronous multiplex communication apparatus of FIG. 1 will be described in detail. First, the slip period will be described. The memory capacity of the memory circuit 205 is M, the write frequency is fw, and the read frequency (reference clock frequency) is fr. The slip period Tslip is expressed by the following equation.
Tslip = (fr × M / 2) ÷ | fw−fr |
When fw and fr are constant as in the prior art, it can be seen that increasing M from the above equation increases Tslip. However, in this case, slip always occurs at the Tslip period.
[0028]
Here, even in a system in which M is the same as that of the conventional system, Tslip can be improved as compared with the conventional system by increasing or decreasing fw within the staff ratio variation. In a stuff synchronizer that cycles with a transmission signal, when changing the stuff ratio, it is necessary to consider stuff jitter during signal reproduction at the receiving end. However, especially in the case of Purejiokuro eggplant operation, because it is configured to read the reference clock reception terminal is proprietary stabilized, this consideration is not necessary.
[0029]
Next, the form of the transmission frequency control signal (a7 to a16) will be described. There are three control modes: (1) increase the frequency, (2) decrease the frequency, and (3) maintain the frequency. At least the forms (1) and (2) are indispensable. As a specific example of operation, 1 bit of control signal is assigned for each of (1) and (2), and the same control signal is transmitted in 5 time slots in the basic unit of the frame in consideration of radio channel error. The control value is determined by majority decision at the receiving end. Here, the time slots for (1) are e1 to e5, and the time slots for (2) are d1 to d5. At the receiving end, 3/5 majority decision is made for each of e and d. This means that erroneous control is not caused even when two of e1 to e5 are erroneous due to a propagation path error. When the determination result of e and d is “1, 0”, the control (1) for increasing the frequency is performed, and when the determination result is “0, 1”, the control (2) for decreasing the frequency is performed. When “1, 1” or “0, 0”, the frequency is maintained (3).
[0030]
Next, the transmission operation of the transmission frequency control information a7 will be described. In FIG. 1, the transmission of the control signal a7 is determined such that the write phase (address) of a6 and the read phase (address) of a9 are monitored to the memory circuit 205, and the address relationship between writing and reading suppresses slipping. When the above relationship is established, the control signal a7 is transmitted.
[0031]
This operation will be described in detail below with reference to FIGS. FIG. 2 is a detailed block diagram of the memory circuit 205 of FIG. A memory 301 into which multiplexed data (memory write data) a6 of the received and reproduced radio frame is input. A gate 303 for generating a memory write clock b3 generated from the clock a6 ′ of the multiplexed data a6 is provided, and data is written to the memory 301 having the memory capacity M with the memory write clock b3. The memory 301 reads and outputs the raw data a9 with the reference clock a8. Further, the memory 301 generates a write address Aw and a read address Ar, and a comparison / determination circuit (COMP) 304 compares the addresses Aw and Ar.
[0032]
FIG. 3 is a timing chart for explaining the operation of each part of the memory circuit 205 shown in FIG. FIG. 3 shows an example of a radio frame in which additional information is 1 bit for 2 bits of raw data. The clock a6 ′ is input to the timing generation circuit 302 and the gate 303. The timing circuit (TIMGEN) 302 includes a gate signal b1 indicating a multiplexing time slot of additional information (information indicated by hatching in a6) in the multiplexed data a6, and a frame pulse b2 indicating a multiplexing period of the radio frame. Is output. The gate 303 generates a write clock b3 for writing the raw data into the memory 301 by eliminating the clock a6 ′ by the gate signal b1.
[0033]
On the other hand, the memory 301 has counters (not shown) that respectively count the write clocks b3 and a8, and generates a write address Aw and a read address Ar. These addresses Aw and Ar and the frame pulse b2 are input to the comparison determination circuit 304. The comparison determination circuit 304 latches the addresses Aw and Ar at the timing of the frame pulse b2, and calculates | Aw′−Ar ′ | = N based on the latched values Aw ′ and Ar ′. According to an example where the calculation result is N = M / 2 (Case 1), an example where N = M / 2 + 1 = Nmax (Case 2), and an example where N = M / 2−1 = Nmin (Case 3) It operates as follows. In Case 1, a control value for maintaining the transmission frequency is output. In Case 2, a control value for lowering the transmission frequency is output. For Case 3, a control value for increasing the transmission frequency is output. This output signal is the frequency control signal a7.
[0034]
This frequency control signal a7 needs to be multiplexed at an integral multiple of the radio frame multiplexing period. This is because, as described above, the receiving side has a majority circuit for suppressing propagation path errors.
[0035]
Finally, the control amount (fstep) of the transmission frequency (fradio) will be described. Memory capacity M, write frequency fw, read frequency (reference clock frequency) fr, slip period Tslip, effective time from when frequency control signal a7 is instructed to change frequency to when signal can be received at controlled frequency Is Twait. In this case, the frequency control amount fstep in one control may have the following relationship.
Tslip≈ (fr × M / 2) ÷ | fw−fr | (1)
fstep> | fw−fr | × K (2)
K ≒ Tslip / Twait (integer)
In the above equation, | fw−fr | is the frequency difference between the write frequency and the read frequency to the memory 301, but the radio must be controlled within a variation range in which stuff synchronization can be established in the first place.
[0036]
Also, the radio frequency is radio, the reference frequency (raw data frequency) of the transmitter is f, the raw data number within the radio frame multiplexing period is Nraw, the additional information raw data number excluding stuff bits is Nadd, and the stuff bits are 1 If it is a bit,
f × (Nraw + Nadd + 1) / (Nraw + 1) ≦ fradio ≦
f × (Nraw + Nadd + 1) / Nraw
f = fw
fradio = fw + fstep
fw × (m / n−1) ≦ fstep ≦ fw × (m / (t−1) −1 (3)
Nraw + Nadd + 1 = m, Nraw + 1 = n
It is set in consideration of the above formulas (1) to (3).
[0037]
【The invention's effect】
As can be understood from the above description, according to the staff synchronous multiplex communication apparatus of the present invention, the following effects can be obtained. It has a variable control function of the transmission frequency, since the variable control of the transmission frequency of the remote station by using time slots of particular additional information, can be suppressed periodically slip in Purejiokuro eggplant operation. In addition, since the jitter is not output to the subsequent time in order to perform the memory reading operation with the stabilized reference clock, the destuffing jitter generated in the stuff synchronous communication can be suppressed. Furthermore, since the memory is read out even with a stabilized reference clock and jitter is not output to the subsequent stage, the jitter transmission characteristics of the transmission signal can be improved for each transmission section, and deterioration of output jitter characteristics can be prevented even when connected in multiple stages. It has a remarkable effect on practical use.
[Brief description of the drawings]
FIG. 1 is a block diagram of a preferred embodiment of a stuff synchronous multiplex communication apparatus of the present invention.
FIG. 2 is a detailed block diagram of a memory circuit of the stuff synchronous multiplex communication device of FIG. 1;
FIG. 3 is a timing chart for explaining the operation of the memory circuit of FIG. 2;
FIG. 4 is a block diagram of a conventional stuff synchronous multiplex communication device.
[Explanation of symbols]
101, 201 Multiplexing circuit 102, 202 Phase monitoring circuit 103, 203 Oscillation circuit 104, 204 Separation circuit 105, 205 Memory circuit 106, 206 Oscillation circuit 301 Memory 302 Timing generation circuit 303 Gate 304 Comparison determination circuit

Claims (5)

In the stuff synchronous multiplex communication device having the transmitting unit and the receiving unit in the first station and the second station connected via the propagation path,
The first station and the second station operate based on asynchronous clock frequencies for transmission processing and reception processing, respectively .
Memory means for absorbing jitter at the receiving station;
Comparison determination means for monitoring write and read addresses to the memory means and determining advance or delay with respect to a preset address relationship;
A transmission unit that transmits a control signal based on a determination result of the comparison determination unit to a game using a radio time slot;
A stuff synchronous multiplex communication apparatus comprising: a transmission frequency variable means for controlling a transmission frequency based on the control signal of the transmission means. 2. The stuff synchronous multiplex communication apparatus according to claim 1, wherein the memory means of the receiving station performs a pre-geochronous operation using a reference clock that is asynchronous with respect to the clock of the transmitting station. The stuff according to claim 2, wherein the processing time for variably controlling the transmission frequency is increased to reduce the memory capacity of the memory means for performing the pre-geochronous operation and to shorten the transmission delay time. Synchronous multiplex communication device. The stuff synchronous multiplex communication apparatus according to claim 1, 2, or 3, wherein a satellite and a ground wireless communication line are connected in multiple stages as the propagation path. 5. The variable control of the transmission frequency is performed based on an absolute value of a difference between values obtained by latching a write address and a read address of the memory unit at a frame pulse timing. Staff synchronous multiplex communication device.

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