JP3632043B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric transistor that modulates carriers appearing in a semiconductor active region by utilizing the remanent polarization of a ferroelectric and an integrated circuit thereof, and has a data retention characteristic more than a field effect transistor having a conventional structure. The present invention relates to a semiconductor device that is excellent.
[0002]
[Prior art]
Conventionally, in a ferroelectric field effect transistor, a gate electrode / ferroelectric thin film / semiconductor (MFS) structure or a gate electrode / ferroelectric thin film / insulating film / semiconductor (MFIS: Metal / Ferroelectric / Insulator / Insulator / Semiconductor) (Semiconductor) structure is used (for example, refer nonpatent literature 1). That is, in both the MFS and MFIS structures, the ferroelectric thin film (F layer) is directly connected to the gate electrode.
[0003]
[Non-Patent Document 1]
E. Tokumitsu, G. et al. Fujii, and H.H. Ishiwara, Appl. Phys. Lett. (1999), Vol. 75, p. 575
[0004]
[Problems to be solved by the invention]
In the conventional ferroelectric gate field effect transistor, residual polarization controlled by the gate electrode is generated in the ferroelectric thin film (F layer), and the channel is turned on / off by carriers generated in the semiconductor so as to cancel the polarization charge. Control is in progress.
However, in this case, for example, in the MFS structure, a ferroelectric capacitor and a paraelectric capacitor caused by a depletion layer generated in the semiconductor layer are connected in series in terms of an equivalent circuit, and the ferroelectric is formed when the gate electrode is short-circuited to the semiconductor layer. The paraelectric capacitor generated in the capacitor and the semiconductor layer acts in a direction to cancel each other's electric field. This is called a depolarizing electric field. As a result of the generation of the depolarizing electric field, a minute current leak occurs in the ferroelectric capacitor and the paraelectric capacitor, and the electric field in each capacitor is canceled. That is, the charge generated by the residual polarization of the ferroelectric in the semiconductor layer disappears, and the channel on / off information is lost.
[0005]
Even in the case of the MFIS structure, since the I layer functions as a paraelectric capacitor, a depolarizing electric field is generated in the same manner, and the problem that channel on / off information cannot be retained for a long time has been pointed out. As a result, even with the best results reported so far, the data retention time of the ferroelectric field effect transistor is only about 10 hours, and there is a problem that it cannot be used as a practical memory.
[0006]
In order to solve this problem, a circuit configuration that uses a highly insulating material for the I layer or relaxes the depolarization electric field has been proposed. Improvement cannot be expected. In other words, it is no exaggeration to say that a structure that essentially does not generate a depolarizing electric field is a precondition for use as a practical memory.
[0007]
[Means for Solving the Problems]
In the conventional ferroelectric field effect transistor, one of the ferroelectrics is in direct contact with the gate electrode, and the charge induced there is not protected in a so-called naked state. On the other hand, on the opposite side adjacent to the semiconductor, the carrier of the semiconductor seals the polarization charge and a protected state is realized. The depolarized electric field is generated when a bare electric charge appearing on the gate electrode eventually contacts the semiconductor through various paths.
[0008]
Therefore, if both sides of the ferroelectric thin film are protected with a semiconductor to prevent the generation of a depolarizing electric field and screening is performed near the heterointerface between the ferroelectric and the semiconductor, the electric field is locally compensated at the heterointerface. Therefore, no electric field is generated even if two adjacent semiconductors are short-circuited with the ferroelectric substance interposed therebetween. That is, by using a structure in which the semiconductor is sandwiched between the ferroelectric thin film and the gate electrode, a depolarizing electric field is not generated, and the polarization charge of the ferroelectric is protected.
[0009]
However, when such a structure is manufactured, it becomes a problem how to control the semiconductor channel and operate the transistor. In the present invention, attention is paid to the fact that the charge appearing on the semiconductor side of the hetero interface between the ferroelectric thin film and the semiconductor is a carrier in the semiconductor, and the fact that the switch operation can be realized by moving it by an electric field parallel to the hetero interface is utilized. Yes. In this operation, since the polarization state of the ferroelectric is always kept in the screened state, a good holding characteristic can be realized.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
<Example 1>
FIG. 1 shows an embodiment of the present invention. First, a field oxide film for element isolation is provided on a single crystal silicon substrate to form a transistor active region. Next, a contact region in which a high concentration impurity is diffused for connecting the source and drain electrodes with low resistance is formed, and an SiO ₂ layer of about 5 nm is formed thereon by thermal oxidation. On top of that, a ferroelectric thin film of SrBi ₂ Ta ₂ O ₉ having a thickness of 200 nm was deposited by sol-gel method and crystallized in an oxygen atmosphere at 800 ° C. for one hour. On top of this, 100 nm of SrTiO ₃ was also deposited by the sol-gel method to form a semiconductor region. On this, 50 nm of Pt to be a gate electrode is deposited, the gate electrode is processed into the shape shown in FIG. 1 by using a normal photolithography technique, and contact holes for forming the source and drain electrodes are further opened to become electrodes there. W is deposited and annealed in 100% nitrogen at 300 ° C. for 30 minutes to obtain ohmic contact.
[0011]
FIG. 2 shows an example of the relationship between the gate applied voltage and the source-drain current of the transistor of this embodiment. When a voltage applied to the ferroelectric thin film by an electric field higher than the electric field (coercive electric field) necessary for the ferroelectric thin film to reverse the polarization is applied to the gate electrode, the ferroelectric polarization is reversed and hysteresis appears in the current-voltage characteristics. That is, the state in which the channel resistance at the heterointerface changes due to inversion of the charge induced in the semiconductor and the current value between the source and drain changes. In the case of FIG. 2, depending on the polarization direction in the ferroelectric thin film, the current value can be kept high or low. That is, the on / off state is stored in a nonvolatile manner.
[0012]
FIG. 3 shows the time dependency of the source-drain current in the state where the gate voltage is maintained at −0.5V. This is a so-called holding characteristic. Two curves in the figure correspond to changes in the current value in the on state and changes in the current value in the off state. As is apparent from the figure, in the case of the structure of the present invention, even after the elapse of 100 hours or more, the current value hardly changes except for the very initial stage, and it can be seen that good holding characteristics are realized. The initial current drop represents a process in which carriers are trapped at the defect level generated at the ferroelectric / semiconductor heterointerface, and can be overcome by improving the quality of the interface characteristics. The figure also shows the holding characteristics of the element having the structure (MFIS structure) in which only the SrTiO ₃ semiconductor layer is omitted in this example. Here, the ON / OFF state approaches rapidly within several hours due to the influence of the depolarizing electric field, and the ON / OFF distinction cannot be made after about 10 hours. That is, the on / off information is lost.
[0013]
FIG. 7 shows a band structure diagram centering on the ferroelectric thin film. According to the present invention, the electric field generated by the remanent polarization in the ferroelectric thin film is completely screened by the compensation charge appearing on the semiconductor side of the two heterointerfaces, and the electric field generated by the remanent polarization at the terminals a and b provided on both surfaces of the semiconductor. The change by does not appear.
Therefore, even if the terminals a and b are short-circuited, no depolarizing electric field is applied to the inside of the ferroelectric or semiconductor. Further, most of the compensation charges appearing in the semiconductor are movable electrons and holes, that is, carriers, and an electric field can be applied in parallel to the heterointerface to move the carriers and allow current to flow.
In addition, even if the compensation charge is moved in this way, the charge compensation condition in the direction perpendicular to the heterointerface is maintained, so that the residual polarization inside the ferroelectric is not affected.
[0014]
That is, according to the present invention, since the depolarizing electric field that has a detrimental effect on the holding characteristics of the ferroelectric field effect transistor can be eliminated, it is possible to realize good data holding characteristics as shown in FIG. .
[0015]
<Example 2>
FIG. 4 shows a second embodiment of the present invention. As in Example 1, after forming a semiconductor / ferroelectric / insulator / semiconductor (SrTiO ₃ / SrBi ₂ Ta ₂ O ₉ / SiO ₂ / Si), about 2 nm of Al ₂ O ₃ was formed, and then a Pt gate electrode Form. That is, it is a field effect transistor having a cross-sectional structure of gate electrode / insulator / semiconductor / ferroelectric / insulator / semiconductor (Pt / Al ₂ O ₃ / SrTiO ₃ / SrBi ₂ Ta ₂ O ₉ / SiO ₂ / Si). . By inserting thin Al ₂ O ₃ directly under the gate electrode, the gate breakdown voltage is improved, and it is possible to apply a high electric field higher than the coercive electric field to the ferroelectric layer with a high yield.
[0016]
<Example 3>
5 and 6 show a third embodiment of the present invention. Similar to the first embodiment, the source electrode and the gate electrode / semiconductor / ferroelectric / insulator / semiconductor (Pt / SrTiO ₃ / SrBi ₂ Ta ₂ O ₉ / SiO ₂ / Si) cross-sectional structure are formed on the Si semiconductor substrate. It has a structure having a drain electrode.
A cross section taken along the line AA 'in FIG. 5 has the structure shown in FIG. Further, the cross section cut along BB ′ has the structure of FIG.
In FIG. 6, contact holes are formed in the SrTiO ₃ semiconductor layer, and Au is deposited to realize ohmic contact to form source and drain electrodes.
As shown in FIG. 5, the two sets of source / drain electrodes share one gate electrode, and a single voltage application via the gate electrode realizes an on state in the Si semiconductor layer and an off state in the SrTiO ₃ semiconductor layer. Is possible. If the polarity of both semiconductor layers is changed, it is possible to realize a state in which both transistors are turned on by transistors having p-type and n-type channels. If applying a voltage higher than the coercive electric field to the gate electrode is defined as a write operation, information is stored in a nonvolatile manner by these write operations. In addition, as shown in Embodiment 1, there is no occurrence of a depolarizing electric field due to these writing operations or source / drain voltage application, and nonvolatile information can be stably held for a long time.
Further, as shown in Embodiment 3, it is possible to realize an element that can share one gate and can hold two states in a nonvolatile manner.
[0017]
In the embodiments of the present invention, SrBi ₂ Ta ₂ O ₉ polycrystal is used as the ferroelectric thin film. Needless to say, other ferroelectric materials such as Bi ₄ Ti ₃ O ₁₂ and (La, Bi) _{4 are used.} The use of a ferroelectric thin film such as Ti ₃ O ₁₂ is equally effective. It is also possible to use another paraelectric material instead of the SiO ₂ insulating film.
[0018]
Naturally, the present invention is also effective for a semiconductor other than a Si substrate, and a single crystal element in which a ferroelectric, a second semiconductor, an insulating film, etc. thereon are formed epitaxially can also be used.
[0019]
If a single crystal element can be fabricated in this way, it can be expected that defects at the heterointerface will be reduced and slight current deterioration seen at the beginning of the data retention characteristics shown in FIG. 3 can be suppressed.
[0020]
【The invention's effect】
According to the present invention, since the depolarization electric field does not appear by compensating the residual polarization of the ferroelectric in the semiconductor adjacent to the ferroelectric thin film, there is no effect of reversing the residual polarization of the ferroelectric. It has become possible to realize long-term data retention characteristics.
[Brief description of the drawings]
FIG. 1 is a cross-sectional structure of a ferroelectric field effect transistor according to a first embodiment.
FIG. 2 shows the relationship between the gate voltage and the source-drain current of the transistor of the first embodiment.
FIG. 3 shows retention characteristics of source-drain current of the first embodiment.
FIG. 4 is a schematic diagram of a ferroelectric field effect transistor according to a second embodiment.
FIG. 5 is a bird's-eye view of a ferroelectric field effect transistor according to a third embodiment.
6 is a cross-sectional structure of a ferroelectric field effect transistor cut along BB ′ in FIG. 5;
FIG. 7 is a band diagram of the ferroelectric / semiconductor double heterostructure of the present invention.
[Explanation of symbols]
1 is a single crystal silicon substrate, 2 is a source electrode contact region in which high concentration impurities are diffused, 3 is a drain electrode contact region in which high concentration impurities are diffused, 4 is a source electrode, 5 is a drain electrode, and 6 is a thermally oxidized SiO ₂ film 7 is a SrBi ₂ Ta ₂ O ₉ ferroelectric thin film, 8 is a SrTiO ₃ semiconductor layer, 9 is a gate electrode, 10 is remanent polarization in the ferroelectric thin film, and 11 is induced in the second semiconductor by remanent polarization. Screening charge, 12 is screening charge induced in the first semiconductor by remanent polarization, 13 is an Al ₂ O ₃ insulating film, 14 is a source electrode in ohmic contact with the second semiconductor layer, and 15 is a second semiconductor. The drain electrode in ohmic contact with the layer, 16 is the band structure of the second semiconductor, 17 is the band structure of the ferroelectric thin film, and 18 is the band structure of the first semiconductor. .

Claims (12)

A semiconductor substrate;
A first impurity diffusion layer formed in a surface layer portion of the semiconductor substrate;
A second impurity diffusion layer formed in the surface layer portion at a predetermined interval with respect to the first impurity diffusion layer;
An insulating film bridged between the first and second impurity diffusion layers on the semiconductor substrate;
A ferroelectric film formed on the insulating film,
A semiconductor thin film is provided on the ferroelectric film;
A first source region and a first drain region respectively formed at one end and the other end of the semiconductor thin film;
A first source electrode and a first drain electrode that are ohmically connected to the first source region and the first drain region, respectively.
Furthermore, a second source electrode and a second drain electrode that are ohmically connected to the first and second impurity diffusion layers, respectively, are provided,
A semiconductor device, wherein a gate electrode is provided on the semiconductor thin film. A first heterointerface formed at an interface between the ferroelectric film and the semiconductor thin film;
A second hetero interface formed at the interface between the ferroelectric film and the semiconductor substrate via the insulating film;
An electric field parallel to the first and second heterointerfaces is applied to electrons or holes induced at the first and second heterointerfaces by applying a voltage to the gate electrode, respectively. The semiconductor device according to claim 1. 2. The semiconductor device according to claim 1, wherein residual polarization in the ferroelectric film is controlled by the gate electrode that applies an electric field in a direction perpendicular to the first and second heterointerfaces. 2. The electron source or the hole in / out of the semiconductor thin film is performed by the first source electrode and the first drain electrode that apply an electric field parallel to the first hetero interface. Semiconductor device. 2. The electron source or the hole in / out of the semiconductor substrate is performed by the second source electrode and the second drain electrode that apply an electric field parallel to the second hetero interface. Semiconductor device. 2. The semiconductor device according to claim 1, wherein an electric field is applied in a direction perpendicular to the first and second heterointerfaces by the gate electrode to control remanent polarization in the ferroelectric film. A semiconductor substrate;
A first impurity diffusion layer and a second impurity diffusion layer formed on the surface layer portion of the semiconductor substrate at a predetermined interval;
A first insulating film bridged between the first and second impurity diffusion layers on the semiconductor substrate;
A ferroelectric film formed on the first insulating film,
A semiconductor thin film is formed on the ferroelectric film, and a second insulating film is further provided on the semiconductor thin film;
A first source region and a first drain region respectively formed at one end and the other end of the semiconductor thin film;
A first source electrode and a first drain electrode that are ohmically connected to the first source region and the first drain region, respectively.
Furthermore, a second source electrode and a second drain electrode that are ohmically connected to the first and second impurity diffusion layers, respectively, are provided,
A semiconductor device, wherein a gate electrode is provided on the second insulating film. A first hetero interface formed at an interface between the ferroelectric film and the semiconductor thin film via the first insulating film;
A second hetero interface formed at the interface between the ferroelectric film and the semiconductor substrate via the second insulating film;
An electric field parallel to the first and second heterointerfaces is applied to electrons or holes induced at the first and second heterointerfaces by applying a voltage to the gate electrode, respectively. The semiconductor device according to claim 7. The semiconductor device according to claim 7, wherein remanent polarization in the ferroelectric film is controlled by the gate electrode that applies an electric field in a direction perpendicular to the first and second heterointerfaces. 8. The electron source or the hole insertion / extraction into / from the semiconductor thin film is performed by the first source electrode and the first drain electrode that apply an electric field parallel to the first hetero interface. Semiconductor device. 8. The electron source or the hole insertion / extraction into / from the semiconductor substrate is performed by the second source electrode and the second drain electrode that apply an electric field parallel to the second hetero interface. Semiconductor device. 8. The semiconductor device according to claim 7, wherein an electric field is applied in a direction perpendicular to the first and second hetero interfaces by the gate electrode to control remanent polarization in the ferroelectric film.

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