JP3636276B2 - Programmable controller and control system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a programmable controller and a control system .
[0002]
[Prior art]
For example, in order to transmit data by connecting the master (main unit board) and slave (subunit board) of the programmable controller with a bus, the address, data, There are cases where a synchronous bus through which a control signal is transmitted is used and cases where an asynchronous bus through which an address, data, and control signals are transmitted without being synchronized with a clock supplied from a master or a slave is used.
[0003]
Dedicated semiconductor devices such as ASICs (hereinafter referred to as ASICs) used for programmable controllers, etc., are designed to be used for both synchronous and asynchronous buses. Is set to the circuit. Conventionally, the ASIC side discriminates this setting and operates according to each situation.
[0004]
That is, the conventional use state determination circuit for determining whether the use state of the bus is synchronous or asynchronous, as shown in FIG. 4, the clock signal line for the synchronous bus from the master or slave is connected to one pin P1 of the ASIC 10. CLK is connected, and the other pin P2 of the ASIC is connected to the synchronous / asynchronous setting line S. The above two pins P1 and P2 are connected to the input terminal of the multiplexer 20 in the ASIC. . The synchronous / asynchronous setting line S is switched to a high level constant voltage power supply V _DD in the case of a synchronous bus and to a low level constant voltage power supply V _SS in the case of an asynchronous bus.
[0005]
When the input from the pin P2 is a low level V _SS , the multiplexer 20 determines that the bus is an asynchronous bus and outputs V _SS to the internal bus control unit 30 so that the internal bus operates asynchronously. Control. On the contrary, when the input from the pin P2 is the high level V _DD , it is determined as a synchronous bus and the synchronous clock from the pin P1 is output to the internal bus control unit 30, thereby causing the internal bus to be synchronized with the synchronous clock. Control to operate.
[0006]
As described above, the reason why the control of the bus inside the ASIC is also switched according to the synchronization / asynchronization of the bus is that if the ASIC operates asynchronously even though it is connected to the synchronization bus, it is synchronized with the clock. This is because an unwaited wait signal is sent to the bus side and synchronization is lost, so that the master or slave receives this wait signal at the next clock.
[0007]
[Problems to be solved by the invention]
By the way, the ASIC is provided with a large number of pins for wiring connection projecting to the outside depending on the application, and these pins are inserted into the holes of the receptacle on the printed circuit board side so as to be connected to the printed circuit board. It has become. The number of pins is prepared according to the standard according to the size and application of the ASIC. However, as the ASIC becomes more multifunctional, the number of pins required increases, making it difficult to assign pins at the time of design. May be. In such a case, the use of two pins as in the above-described use state determination circuit (see FIG. 4) to determine whether the bus is synchronous or asynchronous causes a problem in design. there were.
[0008]
The present invention solves the above-described problems and provides a programmable controller and a control system that require only one ASIC pin for inputting a synchronous clock.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides a process in which the master performs processing without synchronizing with the slave when transmitting data between the master and the slave each having an MPU via a bus. A programmable controller that selects a case where processing is performed in synchronization with the slave using the clock signal line of the bus, wherein the master is a semiconductor device connected to the bus, and the semiconductor Provided outside the device, when the master processes in synchronization with the slave, outputs a clock signal on the clock signal line of the bus, and the master processes without synchronizing with the slave Includes a clock and a constant voltage gate for generating and outputting a constant level signal, and the semiconductor device has a plurality of pins for connecting the substrate. One pin is connected to the output terminal of the clock / constant voltage gate as a synchronous bus signal input pin, and the clock signal or a constant level signal is input from the output terminal, and a predetermined time-up time is set and activated. A timer that is started by a signal, a counter that counts a clock of a signal that is input to the synchronous bus signal input pin during operation of the timer, a synchronous bus if the counter is counted, and a counter that is not counted A bus use state determination unit that determines an asynchronous bus .
[0010]
Further, the present invention is a control system that includes a master and a slave each having an MPU, and transmits data by connecting the master and the slave via a bus including a clock signal line and a data line. A case where processing is performed without synchronizing with the slave and a case where processing is performed in synchronization with the slave using the clock signal line of the bus can be selected and has a plurality of pins for board connection And a semiconductor device connected to the bus, and a synchronization / output device that is provided outside the semiconductor device and outputs a signal according to whether the master performs processing in synchronization with the slave or processing without synchronization. An asynchronous setting unit, and the semiconductor device includes a synchronous bus signal input pin in the plurality of pins, and the synchronous / asynchronous setting unit via the synchronous bus signal input pin. An output signal is input, and a bus control unit that selectively controls whether the bus is used as a synchronous bus or an asynchronous bus; and the synchronization based on an input signal of the synchronous bus signal input pin A determination unit that determines the setting of the asynchronous setting unit and notifies the determination result to the bus control unit, and the synchronous / asynchronous setting unit can capture the clock signal from the clock signal line of the bus In the case of a synchronous bus, the bus clock signal is output to the synchronous bus signal input pin. In the case of an asynchronous bus, a constant level signal is generated and output to the synchronous bus signal input pin. The determination unit can confirm that the signal input from the synchronous / asynchronous setting unit via the synchronous bus signal input pin is a clock signal. Determines that the synchronous bus, and characterized in that to determine that an asynchronous bus if it can be confirmed that a constant level signal.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a programmable controller according to the present invention. In FIG. 1, PCB 1 is a master printed circuit board constituting a main unit (master) that is responsible for overall control of the programmable controller. PCB2 is a slave printed circuit board that constitutes a subunit (slave) that operates under the control of the master printed circuit board PCB1. The master printed circuit board PCB1 and the slave printed circuit board PCB2 are connected by a local bus Local Bus so as to transmit and receive each other.
[0012]
The master printed circuit board PCB1 is provided with an MPU, a RAM, an ASIC, and the like, and is connected to each other via an MPU bus or the like. One ASIC (ASIC1) 10 is directly connected to the MPU (Slave) provided on the slave printed circuit board PCB2 by a local bus Local Bus, and a clock signal from the MPU (Slave) is a clock signal of the local bus Local Bus. Received via the line.
[0013]
Note that the other ASIC (ASIC 2) of the master printed circuit board PCB1 is connected to an external device via an I / O bus, and communicates with the external device. The printed circuit board PCB2 is also provided with RAM and the like other than the MPU, but these are not directly related to the present invention, and thus detailed description thereof is omitted.
[0014]
The local bus Local Bus is provided with a control signal line, a data line, etc. in addition to the clock signal line, and an MPU (Slave) clock provided on the slave printed circuit board PCB2 according to the control system used. The data from the slave printed circuit board PCB2 is processed by the master printed circuit board PCB1 and the data is processed without being synchronized.
[0015]
FIG. 2 is a block diagram illustrating the bus use state determination apparatus in FIG. 1. In FIG. 2, reference numeral 10 denotes an ASIC (ASIC 1 in FIG. 1). A predetermined time-up time is set in the ASIC 10, and a start signal The timer 1 that is started by the above, the counter 2 that counts the clock of the input signal of the synchronous bus signal input pin P during the operation of the timer 1, and the bus synchronization / asynchronism is determined from the count value of the clock counted by the counter 2 A synchronous / asynchronous determination unit (bus use state determination unit) 3 that performs the determination, and an internal bus control unit 30 that receives the determination result of the synchronous / asynchronous determination unit 3 and controls the internal bus of the ASIC 10 as synchronous or asynchronous. It has been.
[0016]
Reference numeral 4 denotes an AND gate (clock / constant voltage gate) provided on the printed circuit board PCB side outside the ASIC 10. The input terminal of the AND gate 4 has a clock signal line CLK for synchronous bus and a synchronous / asynchronous setting line. S and the output terminal of the AND gate 4 are connected to the synchronous bus signal input pin P. The synchronous / asynchronous setting line S is connected to a high level constant voltage power supply (high level power supply) V _DD in the case of a synchronous bus, and to a low level constant voltage power supply (low level power supply) V _SS in the case of an asynchronous bus. The connection is switched.
[0017]
The clock / constant voltage gate 4 and the synchronous bus signal input pin P of the semiconductor device 10 connected to the output terminal of the clock / constant voltage gate 4 and a predetermined time-up time are set and activated by an activation signal. The timer 1 and the counter 2 that counts the clock of the input signal of the synchronous bus signal input pin P during the operation of the timer 1 constitute a bus use state determination unit.
[0018]
With the above configuration, in the case of a synchronous bus, high level V _DD is always applied to the input end of the AND gate 4 on the side of the synchronous / asynchronous setting line S, as shown in FIG. Its output is equal to the synchronization clock CLK and this clock is sent to pin P. The start signal for timer 1 is normally sent to timer 1 when the system is reset. The timer 1 is activated, and the counter 2 counts the clock from the pin P until a very short time-up time corresponding to several clocks, and sends the count value to the synchronous / asynchronous determination unit 3. The synchronous / asynchronous determination unit 3 determines that the bus is synchronous because the clock count has been confirmed, and notifies the internal bus control unit 30 of the determination.
[0019]
On the other hand, in the case of an asynchronous bus, a low level V _SS is always applied to the input terminal of the AND gate 4 on the synchronous / asynchronous setting line S side, as shown in FIG. , Always low and this is sent to pin P. Even if the counter 2 operates until the time-up time after the timer 1 starts, the count value remains 0 because there is no clock from the pin P. The counter 2 sends this result to the synchronous / asynchronous determination unit 3. The synchronous / asynchronous determination unit 3 determines that the bus is asynchronous because the clock count cannot be confirmed, and notifies the internal bus control unit 30 of the determination.
[0020]
As described above, in the bus use state determination apparatus according to the present invention, it is possible to automatically determine whether the bus is a synchronous bus or an asynchronous bus by using only one pin of the ASIC 10 for inputting a clock for synchronization.
[0021]
In the above embodiment, when the low level V _SS is applied to the synchronous / asynchronous setting line S side using the AND gate 4, the output is always set to the low level to block the clock. However, when a high level V _DD is applied to the synchronous / asynchronous setting line S side using, for example, an OR gate (OR-Gate) instead of the AND gate 4 as a clock / constant voltage gate, the output is always output. The clock may be blocked by setting it to a high level.
[0022]
【The invention's effect】
As can be understood from the above description, according to the bus use state determining apparatus of the present invention, a clock signal from the clock signal line of the bus is input in the case of a synchronous bus, and a signal at a constant level in the case of an asynchronous bus. A synchronous bus signal input pin to which a predetermined time-up time is set, a timer that is started by a start signal, a counter that counts the clock of the input signal of the synchronous bus signal input pin during operation of the timer, Since the counter has a bus usage state determination unit that determines the synchronous bus when the clock is counted and the asynchronous bus when the clock is not counted, there is no need to use a special pin for determining the synchronous / asynchronous bus. Since the synchronization / asynchronization of the bus can be determined by using only one pin for clock input for synchronization, ASIC pin assignment Giving a margin to hand, it is possible to increase the degree of freedom of ASIC design, practical value is large.
[0023]
According to the programmable controller of the present invention, the clock / constant voltage gate having the input terminal connected to the clock signal line of the bus and one of the high-level power supply and the low-level power supply, and the clock A synchronous bus signal input pin of a semiconductor device connected to the output terminal of the constant voltage gate, a timer set with a predetermined time-up time and started by a start signal, and the synchronous bus signal input pin of the synchronous bus signal input pin during operation of the timer The wait release timing is optimal because it has a counter that counts the clock of the input signal and a bus usage state determination unit that determines that the clock is counted by the counter as a synchronous bus, and if it is not counted as an asynchronous bus And the efficiency of the processing of the programmable controller is significantly improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing a bus use state determination device in FIG. 1;
3 is a timing chart of the AND gate in FIG. 2, where (a) is a clock input terminal, (b) is a synchronous / asynchronous setting line input terminal and output terminal in the case of a synchronous bus, and (b) is a case of an asynchronous bus. The timing charts of the synchronous / asynchronous setting line input end and output end are shown.
FIG. 4 is a block diagram showing a conventional bus use state determination circuit;
[Explanation of symbols]
1 Timer 2 Counter 3 Synchronous / Asynchronous Judgment Unit (Bus Usage Status Judgment Unit)
4 AND Gate (Clock / Constant Voltage Gate)
10 ASIC
30 Internal bus control section P Synchronous bus signal input pin S Synchronous / asynchronous setting line CLK Clock signal line PCB1 Master printed circuit board (master)
PCB2 Slave printed circuit board (slave)

Claims (2)

When transmitting data between a master and a slave each having an MPU via a bus, the master performs processing without synchronizing with the slave, and uses the clock signal line of the bus. In the programmable controller that selects when processing in synchronization with the slave,
The master is provided outside the semiconductor device connected to the bus and the semiconductor device, and outputs a clock signal on a clock signal line of the bus when the master performs processing in synchronization with the slave. A clock and a constant voltage gate for generating and outputting a constant level signal when the master performs processing without synchronizing with the slave; and
The semiconductor device has a plurality of pins for board connection, and one of the pins is connected to the output terminal of the clock / constant voltage gate as a synchronous bus signal input pin, and the clock signal or the constant level signal is output from the output terminal. A timer that is set by a start signal after a predetermined time-up time is set, a counter that counts a clock of a signal input by the synchronous bus signal input pin during operation of the timer, and the counter A bus usage state determination unit that determines a synchronous bus when the clock is counted and an asynchronous bus when the clock is not counted
A programmable controller characterized by that . In a control system consisting of a master and a slave each having an MPU, and transmitting data by connecting the master and slave by a bus including a clock signal line and a data line,
The master can select a case where processing is performed without synchronizing with the slave and a case where processing is performed in synchronization with the slave using the clock signal line of the bus. A semiconductor device having a plurality of pins and connected to the bus, and a signal provided outside the semiconductor device, depending on whether the master performs processing in synchronization with the slave or not. A synchronous / asynchronous setting unit that outputs
The semiconductor device includes a synchronous bus signal input pin in the plurality of pins, and inputs a signal output from the synchronous / asynchronous setting unit via the synchronous bus signal input pin, and the bus is connected to the synchronous bus A bus control unit that selectively controls whether to use as an asynchronous bus or an asynchronous bus, and determines the setting of the synchronous / asynchronous setting unit based on an input signal of the synchronous bus signal input pin, and the determination result is the bus control A determination unit for notifying the unit,
The synchronous / asynchronous setting unit can take in a clock signal from the clock signal line of the bus, and outputs the clock signal of the bus to the synchronous bus signal input pin in the case of a synchronous bus. In the case of a bus, a constant level signal is generated and output to the synchronous bus signal input pin.
The determination unit determines that the signal input from the synchronous / asynchronous setting unit via the synchronous bus signal input pin is a clock signal, and determines that the signal is a synchronous bus. If the signal is confirmed to be a constant level signal, the determination unit is asynchronous. It is determined to be a bus
A control system characterized by that.

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