JP3637007B2 - ATM cell transfer system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an ATM (Asynchronous Transfer Mode) cell transfer system, and more particularly to a system for connecting an ATM layer device to a plurality of PHY (Physical Layer Protocol) layer devices. The present invention relates to an ATM cell transfer system that makes it possible to acquire a transfer right to transfer an ATM cell to an ATM layer device by outputting an address.
[0002]
[Prior art]
In an ATM device for multiplexing and demultiplexing ATM cells, an interface named UTOPIA (Universal Test and Operation PHY (Physical Layer Protocol) Interface for ATM) as a standardized interface between an ATM layer device and a PHY layer device. Is advocated by the ATM Forum. The ATM Forum (formally The ATM Forum) is a private-level organization established for the purpose of quickly spreading ATM as a user-friendly network construction technology. We perform activities such as.
[0003]
There are several levels of UTOPIA interfaces, and the UTOPIA level 2 interface mainly defines an interface between one ATM layer device and a plurality of PHY layer devices. The upper limit of the number of PHY layer devices that can be connected to one ATM layer device is 31.
[0004]
As an example of a technique related to such UTOPIA level 2, a “UTOPIA level 2 polling control system” described in Japanese Patent Application Laid-Open No. 11-27276 is known. In this publication, the PHY number is arbitrarily set within the range based on the UTOPIA specification for connecting the ATM layer function and the PHY layer function without impairing the polling operation, thereby preventing the performance from being deteriorated and the polling operation. A technique for optimization is described.
[0005]
The interface between one ATM layer device and a plurality of PHY layer devices as defined in UTOPIA level 2 will be described with reference to FIGS. 16 to 20, one ATM layer device is called a master V, a plurality of PHY layer devices subordinate to the master V are called a slave W, and one of the plurality of slaves W is a slave W1, The other one will be described below as a slave W2.
[0006]
FIG. 16 is a diagram showing a connection form of each signal line between one ATM layer device (master) and a plurality of PHY layer devices (slave) in the conventional UTOPIA level 2.
[0007]
One master V and a plurality of slaves W (slave W1, slave W2) are connected by signal lines in a bus connection form as shown in FIG. A signal transmitted and received between the master V and each slave W will be described with reference to FIG.
[0008]
FIG. 17 is a diagram for explaining signal lines of a conventional UTOPIA level 2 interface. In FIG. 17, the master V is simply referred to as a master, and the slave W is simply referred to as a slave.
[0009]
In FIG. 17, (A) shows a signal used when the master transmits an ATM cell (hereinafter, ATM cell is simply abbreviated as a cell) to the slave (Tx), and (B) shows that the master is a slave. The signal used when receiving a cell from (Rx) is shown.
[0010]
TxClk in FIG. 17A is a transmission clock signal transmitted from the master to the slave, and the slave performs a signal transmission / reception operation in synchronization with the transmission clock signal.
[0011]
TxAddr [4..0] is a 5-bit transmission address signal for selecting a cell transmission destination slave, and is transmitted from the master to the slave. Since TxAddr is 5 bits and all 5 bits are “1” addresses (ie, “1Fh”) are reserved words in UTOPIA level 2, the upper limit of the number of slaves that can be connected to one master is The number is limited to 31 (2 5 −1 = 31).
[0012]
TxData [M..0] is a cell transmission data signal transmitted from the master to the slave. In the 8-bit mode with M value of 7, TxData [7..0] uses 8 transmission data buses. However, in the 16-bit mode where the value of M is 15, an expansion bus of TxData [15..8] is used.
[0013]
TxClav is a signal indicating the state of the cell storage buffer of the slave, and is transmitted from the slave to the master when the cell storage buffer is available in an empty state, that is, when a cell transmitted from the master can be received.
[0014]
TxEnb * is a signal indicating cell transmission data transfer enable, and is transmitted from the master to the slave. Note that “*” after the signal name indicates negative logic, is low active, and the same applies to the following signals.
[0015]
TxSOC is a signal indicating the head of a cell to be transmitted, and is transmitted from the master to the slave.
[0016]
RxClk in FIG. 17B is a reception clock signal transmitted from the master to the slave, and the slave performs a signal transmission / reception operation in synchronization with this reception clock signal.
[0017]
RxAddr [4..0] is a 5-bit reception address signal for selecting a transmission source slave of a cell received by the master, and is transmitted from the master to the slave.
[0018]
RxData [M..0] is the received data signal of the cell that the master receives from the slave. In the 8-bit mode with M value of 7, RxData [7..0] uses 8 received data buses. However, in the 16-bit mode where the value of M is 15, an expansion bus of RxData [15..8] is used.
[0019]
RxClav is a signal indicating the state of the cell storage buffer of the slave, and is transmitted from the slave to the master when the cell is held in the cell storage buffer, that is, when the cell that the master wants to receive is held.
[0020]
RxEnb * is a signal indicating cell receive data transfer enable, and is sent from the master to the slave.
[0021]
RxSOC is a signal indicating the head of the cell to be received, and is transmitted from the slave to the master.
[0022]
Next, the operation in the connection form of each signal line shown in FIG. 16 will be described with reference to timing charts shown in FIGS.
[0023]
FIG. 18 is a timing chart when a cell is transmitted from a master (ATM layer device) to a slave (PHY layer device).
[0024]
In FIG. 18, the master V outputs (a) the TxClk signal as a transmission reference clock of the cell on the transmission side as seen from the master V. In synchronization with this reference clock, the master V outputs an address corresponding to each slave W (slave W1, slave W2) and “1Fh” to the (b) TxAddr [4..0] signal every other clock. At this time, assuming that the number of slaves W subordinate to the master V is 31 which is the maximum number defined in UTOPIA level 2, the address transmitted to the TxAddr [4..0] signal at this time is “0h”. ~ "1Eh"("1Fh" is a reserved bit in the UTOPIA level 2 specification).
[0025]
If the slaves W1 and W2 can accept a cell transmitted from the master V when their address is output to the TxAddr [4..0] signal, (c) “1” is set in the TxClav signal. (TxClav signal is normally "0"). At time t4 in FIG. 18, “1” is output to the TxClav signal from the slave W (slave W1 or slave W2) having “2h” as its own address.
[0026]
If the destination slave W (slave W1 or slave W2) can accept the cell, the master V outputs the destination address to the TxAddr [4..0] signal (at time t7 in FIG. 18) ( d) “0” is output to the TxEnb * signal (at time t8 in FIG. 18). When the slave W1 and W2 output their own address to the TxAddr [4..0] signal and “0” to the TxEnb * signal, the slave V1 and the cell W2 (f) TxData [M..0] Wait for output.
[0027]
The master V outputs a cell to the (f) TxData [M..0] signal, and simultaneously outputs (1) "1" for one reference clock to the TxSOC signal at the beginning of the cell (at time t8 in FIG. 18). ). Then, after the time point t8 in FIG. 18, (f) TxData [M..0] signal as a cell data signal, the first header (header: destination information) H1, the second header H2, the fifth A header H5 (not shown), a first payload (Payload: user information) P1 (not shown), and a 48th payload P48 are continuously output.
[0028]
In addition, the master V continues to output (b) the TxData [M..0] to the slave W (slave W1, slave W2) in response to the (b) TxAddr [4..0] signal. The corresponding address is output, and it is continuously checked whether each slave W can receive a cell or not. This operation is called polling.
[0029]
FIG. 19 is a timing chart when the master (ATM layer device) receives a cell from the slave (PHY layer device).
[0030]
In FIG. 19, the master V outputs (a) the RxClk signal to the cell reception reference clock on the receiving side as seen from the master V. Also, the address corresponding to each slave W (slave W1, slave W2) and “1Fh” are alternately output to the (b) RxAddr [4..0] signal, and the cell that each slave W wants to receive by the master V is sent. Check if you have it. This operation is called polling. If the slave W1 or the slave W2 has a cell to be received by the master V when (b) its own address is output to the RxAddr [4..0] signal, (c) the RxClav signal is set to “1”. (The RxClav signal is normally "0"). At time t4 in FIG. 19, “1” is output to the RxClav signal from the slave W (slave W1 or slave W2) having “2h” as its own address.
[0031]
The master V looks at the state of this (c) RxClav signal and confirms whether there is a slave W holding a cell to be received by the master V. If there is a slave W holding the cell to be received, (b) the address corresponding to the slave W is output to the RxAddr [4..0] signal (at time t7 in FIG. 19), (d ) “0” is output to the RxEnb * signal (at time t8 in FIG. 19). When slave W1 or slave W2 has its own address output to the RxAddr [4..0] signal and "0" is output to the RxEnb * signal, (f) RxData [M..0] signals the cell. Output (at time t9 in FIG. 19). (F) When a cell is output to the RxData [M..0] signal, the slave W1 or the slave W2 outputs "1" to the RxSOC signal for one clock of the reference clock at the head of the transmission cell. (Time t9 in FIG. 19). Then, after time t9 in FIG. 19, cells (up to H1, H2,..., P48) are output from the slave W to the (f) RxData [M..0] signal. Master V always polls even if it is receiving a cell from slave W.
[0032]
Next, the configuration of the slave W on the transmission side will be described with reference to FIG.
[0033]
FIG. 20 is a detailed block diagram showing the configuration of the transmission side of the slave (PHY layer device) in the conventional UTOPIA level 2.
[0034]
In FIG. 20, the transmitting side (the receiving side as seen from the master V) in the slave W includes a cell transfer control unit 110, an address control unit 111, and a cell transfer request unit 112.
[0035]
The cell transfer control unit 110 outputs the transfer cell possession signal 120 to the address control unit 111 when the transfer cell signal 122 is input from the cell transfer request unit 112. The address control unit 111 having received the transfer cell possession signal 120 waits for its own address to be output to the RxAddr [4..0] signal, and outputs “1” to the RxClav signal when the own address is output. To do. Thereafter, when the master V outputs its own address again to the RxAddr [4..0] signal and “0” is output to the RxEnb * signal, it recognizes that the master V is in a receivable state. After confirming that the master V is receivable, the address control unit 111 outputs a cell transfer permission signal 121 to the cell transfer control unit 110. The cell transfer control unit 110 that has received the cell transfer permission signal 121 outputs the held cell to the RxData [M..0] signal, and outputs “1” to the RxSOC signal at the head of the cell.
[0036]
[Problems to be solved by the invention]
In the interface between one ATM layer device (master) and a plurality of PHY layer devices (slave) as defined in the conventional UTOPIA level 2 described above, the master V receives cells from the slaves W1 and W2. When receiving, from the start of receiving one cell until the reception is completed, the reference clock (RxClk) requires 53 clocks (since one cell is composed of 53 bytes), whereas the master V It takes 31 × 2 = 62 clocks before polling all the addresses “0h” to “1Eh” of the slave W (UTOPIA level 2 specification). For this reason, the master V requires 53 clocks to complete reception of one cell, but 62 clocks are required to poll all addresses, so 62-53 = 9 clocks are wasted. In other words, when the slave W wants the master V to receive a cell, when the master V starts to receive another slave W cell, it may take up to 62 clocks until the master V receives the next cell. However, there is a problem that the cell reception efficiency is lowered.
[0037]
Furthermore, in the current UTOPIA level 2 specification, the RxAddr [4..0] signal is 5 bits, but in order to make many slaves W subordinate to one master V, the RxAddr [4..0] signal is multi-bited For example, if the 6-bit configuration of RxAddr [5..0] is used, RxClk needs 63 × 2 = 126 clocks to poll all slaves W, further reducing the cell reception efficiency. It has the problem that it ends up. For this reason, there is a problem that the UTOPIA level 2 method defined in the current ATM Forum cannot be easily applied as it is.
[0038]
In the ATM Forum UTOPIA Level 2 specification, the present invention does not reduce the cell transfer efficiency on the receiving side seen from the master, and reception seen from the master even if more slaves are subordinate to one master. An object of the present invention is to provide an ATM layer device (master) and a plurality of PHY layer devices (slave) in the UTOPIA Level 2 specification. In particular, the PHY layer device itself can obtain the transfer right to transfer the ATM cell to the ATM layer device by outputting its own address. It is to provide a transfer method.
[0039]
[Means for Solving the Problems]
The ATM cell transfer system of the present invention is an ATM cell transfer system in a system in which an ATM layer device and a plurality of PHY layer devices are connected at UTOPIA level 2, and the PHY layer devices transfer cells to the ATM layer device. Acquire the right to Therefore, the PHY layer device includes a self address output signal line for outputting the self address to the ATM layer device by the PHY layer device itself. Cell transfer right acquisition means, and when the PHY layer device wants to transfer a cell to the ATM layer device, the cell transfer right acquisition means acquires the right to transfer the cell and immediately transfers the cell. Features.
[0041]
Also The self-address output signal line is composed of arbitrary N + 1 bits, and there is no upper limit to the number of the PHY layer devices that can be subordinate to the ATM layer device.
[0042]
further The cell transfer right acquisition means gives a high priority to the PHY layer device having a small address of the PHY layer device when a plurality of PHY layer devices try to acquire a right to transfer a cell simultaneously. It is characterized by.
[0043]
Also The cell transmission side configuration of the PHY layer device includes a cell transfer request unit that outputs a transfer cell signal when a cell to be received by the ATM layer device is held, and a cell transfer acquisition request when the transfer cell signal is input. A cell transfer control unit that outputs a signal; and when the cell transfer acquisition request signal is input, the cell transfer right acquisition means acquires a right to transfer the cell, and when the right to transfer the cell is acquired, the cell transfer And an arbitration unit that outputs an acquisition signal to the cell transfer control unit.
[0044]
further In the ATM cell transfer system of a system in which an ATM layer device and a plurality of PHY layer devices are connected at UTOPIA level 2, the PHY layer devices acquire the right to transfer cells to the other PHY layer devices. 2 cell transfer right acquisition means, and when the PHY layer device wants to transfer a cell to another PHY layer device, the second cell transfer right acquisition means acquires the right to transfer the cell and immediately It is characterized in that the cell is transferred.
[0046]
Further, the second self-address output signal line is composed of arbitrary N + 1 bits, and there is no upper limit to the number of the PHY layer devices that can be subordinate to the ATM layer device.
[0047]
Furthermore, when the plurality of PHY layer devices try to acquire the right to transfer cells simultaneously, the second cell transfer right acquisition unit gives higher priority to the PHY layer device having a small address of the PHY layer device. It is characterized by giving a ranking.
[0048]
The PHY layer device has a second cell transfer request unit that outputs a transmission / reception cell signal when a cell to be received by another PHY layer device is held, and a second cell when the transmission / reception cell signal is input. A cell transmission / reception control unit that outputs a transfer acquisition request signal, and when the second cell transfer acquisition request signal is input, the second cell transfer right acquisition means acquires a right to transfer the cell and transfers the cell And a second arbitration unit that outputs a second cell transfer acquisition signal to the cell transmission / reception control unit when a right to acquire is acquired.
[0049]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0050]
FIG. 1 is a block diagram showing an embodiment of the ATM cell transfer system of the present invention. Note that this embodiment provides an improved interface method for connecting one ATM layer device and a plurality of PHY layer devices. In this embodiment, one ATM layer device is referred to as a master X. A plurality of PHY layer devices subordinate to the master X will be referred to as a slave Y, and one of the plurality of slaves Y will be described as a slave Y1 and the other one as a slave Y2.
[0051]
Referring to FIG. 1, there is shown an overall block diagram and signal structure as an embodiment of the present invention. That is, it is composed of a master X that is one ATM layer device and a slave Y that is a plurality of PHY layer devices, one of the plurality of slaves Y being a slave Y1, and the other being a slave Y2. The entire block is configured as follows. The master X and the slave Y (slave Y1, slave Y2) are connected by a signal line having a bus connection form as shown in FIG. Signals transmitted and received between the master X and the slave Y will be described with reference to FIG.
[0052]
FIG. 2 is a diagram for explaining the signal lines of the present embodiment. In FIG. 2, the master X is simply referred to as a master, and the slave Y is simply referred to as a slave.
[0053]
In FIG. 2, (A) shows signals used when the master transmits a cell (ATM cell) to the slave (Tx), and (B) shows when the master receives a cell from the slave (Rx). The signal used for is shown.
[0054]
The signal of FIG. 2A is the same as the signal line of the conventional UTOPIA level 2 interface shown in FIG. 17A, but the transmission address signal of TxAddr [N..0] becomes N + 1 bits. Only where they are. This will be described in detail below.
[0055]
TxClk in FIG. 2A is a transmission clock signal transmitted from the master to the slave, and the slave performs a signal transmission / reception operation in synchronization with the transmission clock signal.
[0056]
TxAddr [N..0] is an N + 1-bit transmission address signal for selecting a cell transmission destination slave, and is transmitted from the master to the slave. Since TxAddr is N + 1 bits, there is no upper limit on the number of slaves that can be connected to one master.
[0057]
TxData [M..0] is a cell transmission data signal transmitted from the master to the slave. In the 8-bit mode with M value of 7, TxData [7..0] uses 8 transmission data buses. However, in the 16-bit mode where the value of M is 15, an expansion bus of TxData [15..8] is used.
[0058]
TxClav is a signal indicating the state of the cell storage buffer of the slave, and is transmitted from the slave to the master when the cell storage buffer is available in an empty state, that is, when a cell transmitted from the master can be received.
[0059]
TxEnb * is a signal indicating cell transmission data transfer enable, and is transmitted from the master to the slave. Note that “*” after the signal name indicates negative logic, is low active, and the same applies to the following signals.
[0060]
TxSOC is a signal indicating the head of a cell to be transmitted, and is transmitted from the master to the slave.
[0061]
The signal of FIG. 2B is almost the same as the signal line of the conventional UTOPIA level 2 interface shown in FIG. 17B, but instead of the RxAddr [4..0] signal, RxReqA [N. 0], and the difference is that the RxAcq * signal is used instead of the RxClav signal. This will be described in detail below.
[0062]
RxClk in FIG. 2B is a reception clock signal transmitted from the master to the slave, and the slave performs a signal transmission / reception operation in synchronization with this reception clock signal.
[0063]
RxReqA [N..0] is a signal line from which a slave who wants to transmit a cell to the master outputs his / her address in order to acquire the right of cell transfer, and is composed of N + 1 bits. Since RxReqA [N..0] is N + 1 bits, the upper limit on the number of slaves that can be connected to one master is not limited, as described for TxAddr in FIG. The signal name of RxReqA is named from the meaning of outputting a slave address (A: Address) in order to request acquisition of a cell transfer right (Req: Request). Also, RxReqA [N..0] outputs the address of the slave to be permitted even when the master permits cell transfer to the slave. There are cases where the data is transmitted to the master and data is transmitted from the master to the slave.
[0064]
RxData [M..0] is the received data signal of the cell that the master receives from the slave. In the 8-bit mode with M value of 7, RxData [7..0] uses 8 received data buses. However, in the 16-bit mode where the value of M is 15, an expansion bus of RxData [15..8] is used.
[0065]
RxAcq * is a signal that is output from the slave to the master and other slaves when a certain slave acquires the transfer right of the cell. The signal name of RxAcq * is named from the meaning of a response (Acq: Acknowledge) to the acquisition of the cell transfer right.
[0066]
RxEnb * is a signal indicating cell receive data transfer enable, and is sent from the master to the slave.
[0067]
RxSOC is a signal indicating the head of the cell to be received, and is transmitted from the slave to the master.
[0068]
The signal line of the present embodiment has been described above with reference to FIG. 2, but the signal configuration and operation on the transmission side of the master X, that is, the reception side of the slave Y, are the same as those in the conventional UTOPIA level 2 master shown in FIG. This is similar to the case of transmitting a cell from an (ATM layer device) to a slave (PHY layer device), and since it is not directly related to the present invention, its detailed configuration and operation will be omitted in the following description. To do.
[0069]
Next, the configuration on the transmission side of the slave Y will be described with reference to FIG.
[0070]
FIG. 3 is a detailed block diagram showing the configuration of the transmission side of the slave (PHY layer device) in the present embodiment.
[0071]
In FIG. 3, the transmission side (reception side viewed from the master X) in the slave Y includes a cell transfer control unit 10, an arbitration unit 11, and a cell transfer request unit 12.
[0072]
Then, the slave Y inputs the RxClk signal in the cell transfer control unit 10 and the arbitration unit 11 and uses it as a reference clock on the reception side as viewed from the master X. When the transfer cell signal 22 is sent from the cell transfer request unit 12 to the cell transfer control unit 10, the cell transfer control unit 10 outputs a cell transfer acquisition request signal 20 to the arbitration unit 11, and the cell transfer right (cell to master X) To get the right to receive).
[0073]
The arbitration unit 11 receiving the cell transfer acquisition request signal 20 outputs the address assigned to the slave to the RxReqA [N..0] signal in order to acquire the cell transfer right. At this time, the arbitration unit 11 in the slave Y always receives the RxReqA [N..0] signal. The arbitration unit 11 in the slave Y determines whether the cell transfer right has been acquired in the state of the input RxReqA [N..0] signal after outputting its own address to the RxReqA [N..0] signal.
[0074]
When the slave Y has acquired the right to transfer the cell to the master X, the arbitration unit 11 in the slave Y outputs “0” to the RxAcq * signal outside the slave Y. This informs the master X and other slaves Y that it has acquired the right to transfer cells to the master X. The arbitration unit 11 also outputs a cell transfer acquisition signal 21 to the cell transfer control unit 10 to inform the cell transfer control unit 10 that the cell transfer right has been acquired.
[0075]
Thereafter, when “0” is output from the master X to RxEnb * (meaning cell output permission), the cell transfer control unit 10 outputs a cell to the RxData [M..0] signal. At this time, "1" is output to RxSOC at the first byte of the cell.
[0076]
Next, the operation of the present embodiment will be described in detail with reference to FIG.
[0077]
FIG. 4 is a flowchart for explaining the operation of the present embodiment.
[0078]
In FIG. 4, the operation when it is assumed that there are two slaves Y, slave Y1 and slave Y2, subordinate to master X will be described.
[0079]
First, the branch 1 in FIG. 4 will be described. Consider a case where the slave Y1 has a cell to be received by the master X (step S11). At this time, the arbitration unit 11 in the slave Y1 confirms the state of the RxAcq * signal input from outside the slave Y1 (step S12) and is “1” (the slave Y2 has not acquired the cell transfer right). ) Confirm that. At this time, if the RxAcq * signal is "0" (slave Y2 has already acquired the cell transfer right), the process waits until the RxAcq * signal becomes "1" (RxAcq * = "0" in step S12). ). When the RxAcq * signal is “1” (RxAcq * = “1” in step S12), the arbitration unit 11 in the slave Y1 outputs the address assigned to the RxReqA [N..0] signal. (Step S13). The slave Y1 outputs the address assigned to it to the RxReqA [N..0] signal, and at the same time inputs the state of the RxReqA [N..0] signal outside the slave Y1 (step S14) and confirms it. (Step S15).
[0080]
If the address input from the RxReqA [N..0] signal outside the slave Y1 is the own address (Yes in step S15), “0” is output to the RxAcq * signal to acquire the transfer right (step S16). ). If it is other than its own address (slave Y2 is also trying to acquire the right to transfer cells to master X) (No in step S15), the process proceeds to step S21 of branch 2 (branch 2 will be described later).
[0081]
The master X confirms the state of the RxReqA [N..0] signal when the RxAcq * signal becomes “0”, and recognizes the slave Y transferring the cell. The master X that recognizes the slave Y that transfers the cell outputs “0” (transfer permission) to the RxEnb * signal and waits for the cell to be output from the slave Y. The cell transfer control unit 10 of the slave Y1 confirms the state of the RxEnb * signal (step S17). When RxEnb * = "0" (RxEnb * = "0" in step S17), RxData [M. .0] and when outputting the head data of the cell, "1" is output to RxSOC (step S18). The cell output from the slave Y1 to RxData [M..0] in step S18 is received by the master X.
[0082]
Next, the branch 2 shown in FIG. 4 will be described.
[0083]
When the branch Y2 is entered, the slave Y1 confirms whether the address input from the RxReqA [N..0] signal is “0” being output in a higher bit than the self address (step S21). If “0” is output in the upper bits (Yes in step S21), the slave Y1 determines that the right to acquire cell transfer is lower than the slave Y2, stops output of the address, and performs one bus cycle (1 After waiting (cell transfer time) (step S23), the process proceeds to step S12 of branch 1.
[0084]
If there is no “0” in the upper bits of its own address, it is determined that the slave Y1 has a higher right to acquire cell transfer than the slave Y2 (No in step S21), and then one clock of the reference clock (RxClk). Waits for as many minutes as possible while outputting its own address. After outputting for another clock, the RxReqA [N..0] signal is confirmed again (step S22). If an address other than its own address has been output to the RxReqA [N..0] signal (No in step S22), the process proceeds to step S31 of branch 3 to perform the final right acquisition operation (branch 3 Will be described later). If the address output in the RxReqA [N..0] signal is the self address (Yes in step S22), the process proceeds to step S16 of branch 1, and thereafter the same operation in branch 1 as described above is performed. Do.
[0085]
Next, the branch 3 in FIG. 4 will be described.
[0086]
When the process proceeds to branch 3, the slave Y1 determines that it is necessary to perform a final right acquisition operation with the slave Y2. The slave Y1 searches for a bit in which “0” is output among the addresses output in the RxReqA [N..0] signal. The slave Y1 is an address input from the RxReqA [N..0] signal, and the bits to which “0” is output are numbered 1, 2, 3,. After the numbering is completed, the slave Y1 compares the input address with its own address, and searches for a “0” bit that is different from the own address (step S31).
[0087]
The slave Y1 searches for the most significant bit with the different bits, and confirms the numbering of the numbering performed earlier (step S32). The slave Y1 confirming the number stops address output and waits for the reference clock (RxClk) equivalent to the number (step S33). Thereafter, the process returns to step S12 of branch 1 in FIG. 4 again, and a cell transfer right acquisition operation in branch 1 is performed. From this, the slave Y1 can output an address earlier if the bit number of “0”, which was different from the slave Y2, is smaller (the smaller the address value), the more the slave Y2 than the slave Y2. It is possible to acquire the cell transfer right quickly.
[0088]
4 and FIG. 4 using FIG. 7 and FIG. 8, and FIG. 4 using FIG. 9 and FIG. The branch 3 will be described in detail with a specific example. 5 to 12, it is assumed that the value of N of the RxReqA [N..0] signal is 5 (the address signal is 6 bits). Then, the 0th bit of the RxReqA [N..0] signal is displayed as RxReqA0, and the fifth bit of the RxReqA [N..0] signal is displayed as RxReqA5 in the same manner.
[0089]
5 and 6 are diagrams for explaining the operation of the branch 1 in FIG. 4, FIG. 5 is a configuration diagram for explaining the branch 1 in FIG. 4, and FIG. 6 is a timing diagram for explaining the branch 1 in FIG. is there.
[0090]
In FIG. 5, it is assumed that the address of the slave Y1 is assigned as “2Fh” and the address of the slave Y2 is assigned as “1Fh”. 5 that correspond to the components shown in FIG. 1 are denoted by the same reference numerals or symbols, and the description thereof is omitted.
[0091]
FIG. 6 is a timing chart when only the slave Y2 has a cell that the master X wants to receive. The slave Y2 first checks the state of the RxAcq * signal (at time t1 in FIG. 6). The slave Y2 confirming that the RxAcq * signal is “1” outputs its own address “1FH” to the RxReqA [5..0] signal in order to acquire the cell transfer right (at time t2 in FIG. 6). At this time, since the address of the input RxReqA [5..0] signal is “1Fh”, the slave Y2 recognizes that the slave Y1 is not performing the operation of acquiring the cell transfer right (( A)). After recognizing that the slave Y1 has not acquired the cell transfer right, "0" is output to the RxAcq * signal (at time t3 in FIG. 6), and the master X and the slave Y2 have acquired the cell transfer right. Inform slave Y1.
[0092]
Slave Y2 outputs “0” to the RxAcq * signal, and then outputs “0” to RxEnb * from the master X (at time t4 in FIG. 6), and outputs a cell to the RxData [M..0] signal. (At time t5 in FIG. 6B). The slave Y2 outputs “1” to the RxSOC signal at the start of cell output (time t5 in FIG. 6). After the time t5 in FIG. 6, the first header H1 (t5 in FIG. 6), the second header H2 (t6 in FIG. 6), RxData [M..0] signal as the cell data signal, The fifth header H5 (t9 in FIG. 6), the first payload P1 (t10 in FIG. 6), and the 48th payload P48 (t57 in FIG. 6) are continuously output.
[0093]
FIGS. 7 and 8 are diagrams for explaining the operation of branch 2 in FIG. 4, that is, the operations when the slaves Y1 and Y2 try to acquire the right to transfer the cell to the master X at the same time. FIG. 8 is a block diagram for explaining the branch 2, and FIG. 8 is a timing chart for explaining the branch 2 in FIG.
[0094]
In FIG. 7, it is assumed that the address of the slave Y1 is assigned as “20h” and the address of the slave Y2 is assigned as “10h”. 7 that correspond to the components shown in FIG. 1 are denoted by the same reference numerals or symbols, and the description thereof is omitted.
[0095]
FIG. 8 is a timing chart when the slaves Y1 and Y2 try to acquire the cell transfer right to the master X at the same time. Since the slaves Y1 and Y2 tried to acquire the cell transfer right at the same time, after confirming that the RxAcq * signal is “1” (at the time t1 in FIG. 8), each of the slaves Y1 and Y2 sets their own address to RxReqA [5..0]. The signal is output (at time t2 in FIG. 8B). In such a case, the address output to the RxReqA [5..0] signal is “00H” (assuming that “0” is stronger than “1”). The slaves Y1 and Y2 know that the address inputted from the RxReqA [5..0] signal is “00h”, so that the slave Y1 and the slave Y2 are trying to acquire the cell transfer right at the same time. Therefore, the slaves Y1 and Y2 compare their own address with the address ("00h") input from the RxReqA [5..0] signal, and confirm that "0" is output in the higher bits than the own address. To do.
[0096]
Considering the slave Y1, since the slave Y1 has its own address "20h", the address "00h" input from the RxReqA [5..0] signal is output with "0" in the higher bits than the own address. Know that you are. Recognizing that “0” is output in the upper bits of its own address, slave Y1 determines that the right to transfer the cell is lower than slave Y2, and outputs it to the RxReqA [5..0] signal. The address output is stopped and the next cell transfer cycle (for one bus cycle until the slave Y2 finishes transferring one cell) is waited ((B) in FIG. 8).
[0097]
On the other hand, the slave Y2 recognizes that "0" is not output in the higher bits of its own address, so it outputs its own address following RxReqA [5..0] for one more reference clock (RxClk). (Time point t3 in FIG. 8B). Slave Y2 recognizes that the cell transfer right has been acquired because the address output to the RxReqA [5..0] signal coincides with its own address (at time t3 in FIG. 8), and changes the state of the RxAcq * signal again. Confirm (time t3 in FIG. 8). As a result, since the RxAcq * signal is “1”, the slave Y2 outputs “0” to the RxAcq * signal (at time t4 in FIG. 8), indicating that the slave Y1 has acquired the cell transfer right. And inform the master X. The subsequent operation (after time t5 in FIG. 8) is the same operation as that of the above-described branch 1, and the slave Y2 assigns its own cell from the first header H1 to 48 after time t6 in FIG. The data is continuously output up to the first payload P48.
[0098]
FIGS. 9 and 10 show the operation of branch 3 in FIG. 4, that is, when slaves Y1 and Y2 try to acquire the cell transfer right to master X at the same time. FIG. 9 is a block diagram for explaining the branch 3 in FIG. 4, and FIG. 10 is for explaining the branch 3 in FIG. It is a timing diagram.
[0099]
In FIG. 9, it is assumed that the address of the slave Y1 is “25h” and the address of the slave Y2 is “2Bh”. 9 that correspond to the components shown in FIG. 1 are assigned the same reference numerals or symbols, and descriptions thereof are omitted.
[0100]
FIG. 10 shows a case where slaves Y1 and Y2 try to acquire a cell transfer right to master X at the same time, and the address is output again after one clock in branch 2, but the input address does not match the address. FIG. 5 is a timing chart for explaining the operation in the case (in the case of No in step S22 of FIG. 4). First, the operation up to branch 2 in FIG. 4 is the same as described above, and slaves Y1 and Y2 simultaneously output their own addresses to the RxReqA [5..0] signal at time t2 in FIG. The local address is output again at time t3. When the address output again in step S22 of branch 2 in FIG. 4 is other than its own address (at time t3 in FIG. 10), slave Y1 and slave Y2 receive the input RxReqA [5..0] signal. Search for the bit that is output "0" at the address of. In FIG. 10, "0" is output to RxReqA1, RxReqA2, RxReqA3, and RxReqA4, and this state is particularly shown in FIG.
[0101]
The slaves Y1 and Y2 number the “0” bits output to the RxReqA [5..0] signal from the lower bits. In FIG. 10A, “1” is assigned to RxReqA1, “2” is assigned to RxReqA2, “3” is assigned to RxReqA3, and “4” is assigned to RxReqA4. After numbering, the slaves Y1 and Y2 compare with their own addresses and search for different bits. As a result of the search, the second bit is different in the slave Y1 ((b) in FIG. 10), and the first and third bits are different in the slave Y2 ((c) in FIG. 10). Prove. The slaves Y1 and Y2 check which number of the different "0" bits the numbering of which has been performed earlier is the most significant bit. It turns out that the second is the most significant bit in the slave Y1 ((b) in FIG. 10), and the third is the most significant bit in the slave Y2 ((c) in FIG. 10).
[0102]
The slaves Y1 and Y2 whose number is confirmed stop the address that was once output, and start outputting their own address again at RxReqA [5..0] at the reference clock (RxClk) of their confirmed number. . The subsequent operation returns to step S12 of branch 1 in FIG. In FIG. 10, since the second bit of the slave Y1 is different, the slave Y1 tries to output an address again at the second clock of the reference clock (RxClk) (at time t5 in FIG. 10, RxReqA [5..0] The address "25h" of slave Y1 is output to The slave Y2 is different in the first and third bits, but since the most significant bit is third, the slave Y2 outputs its own address again at the third clock of the reference clock (RxClk) (at time t6 in FIG. 10). , The address “2Bh” of slave Y2 is output to RxReqA [5..0].
[0103]
When the slave Y1 outputs its own address again (that is, at time t5 in FIG. 10), the RxAcq * signal is "1" and the state of RxReqA [5..0] outside the slave Y1 matches the own address. Transfer right can be acquired. However, when the slave Y2 sends its own address again (that is, at time t6 in FIG. 10), the slave Y1 has already acquired the cell transfer right (the RxAcq * signal is “0”). Therefore, the cell transfer right acquisition operation is stopped.
[0104]
Next, with reference to FIGS. 11 and 12, the branch 3 in FIG. 4 will be described with another example.
[0105]
11 and 12 are second diagrams for explaining the operation of the branch 3 in FIG. 4, FIG. 11 is a second configuration diagram for explaining the branch 3 in FIG. 4, and FIG. 12 is a diagram of the branch 3 in FIG. FIG. 6 is a second timing diagram illustrating the above.
[0106]
In FIG. 11, it is assumed that the address of the slave Y1 is assigned as “01h” and the address of the slave Y2 is assigned as “02h”. In FIG. 11, components corresponding to those shown in FIG. 1 are denoted by the same reference numerals or symbols, and description thereof is omitted.
[0107]
FIG. 12 is a second timing diagram illustrating branch 3 of FIG. First, the operation up to branch 2 in FIG. 4 is the same as described above, and slaves Y1 and Y2 simultaneously output their own addresses to the RxReqA [5..0] signal at time t2 in FIG. The local address is output again at time t3. If the address output again in step S22 of branch 2 in FIG. 4 is other than its own address (at time t3 in FIG. 12), slave Y1 and slave Y2 receive the input RxReqA [5..0] signal. Search for the bit that is output "0" at the address of. In FIG. 12, “0” is output to all of RxReqA0, RxReqA1, RxReqA2, RxReqA3, RxReqA4, and RxReqA5, and this state is particularly shown in FIG.
[0108]
The slaves Y1 and Y2 number the “0” bits output to the RxReqA [5..0] signal from the lower bits. In FIG. 12 (a), RxReqA0 is numbered “1”, RxReqA1 is “2”, RxReqA2 is “3”, RxReqA3 is “4”, RxReqA4 is “5”, and RxReqA5 is “6”. After numbering, the slaves Y1 and Y2 compare with their own addresses and search for different bits. As a result of the search, it is found that the first bit is different in the slave Y1 ((b) in FIG. 12), and the second bit is different in the slave Y2 ((c) in FIG. 12). The slaves Y1 and Y2 check the highest bit among the different "0" bits among the numbering performed earlier. Since only the first is different in the slave Y1, the first is the most significant bit ((b) in FIG. 12), and since only the second is different in the slave Y2, the second is the most significant bit ( (C) in FIG. 12 is found.
[0109]
The slaves Y1 and Y2 whose number has been confirmed temporarily stop the address that has been output, and start outputting their own address again at RxReqA [5..0] at the reference clock (RxClk) of that number. Since the first bit is the most significant bit, the slave Y1 outputs its own address at the first clock (time t4 in FIG. 12). The subsequent operation returns to step S12 of branch 1 in FIG. However, since the second bit is the most significant bit, the slave Y2 stops the output address and outputs its own address again at the second clock (time t5 in FIG. 12). Since the transfer right has been acquired (RxAcq * signal is "0"), the cell transfer right acquisition operation is stopped.
[0110]
As described above in detail, according to the ATM cell transfer system of the present invention, when each slave Y tries to acquire the cell transfer right at the same time, the priority order that can be acquired is determined by the address of each slave Y.
00h>01h>02h> ... 3Eh> 3Fh (assuming N of RxReqA [N..0] is 5 (when the address is 6 bits)) Get higher.
[0111]
Next, a second embodiment of the present invention will be described with reference to FIG. 13, FIG. 14, and FIG.
[0112]
FIG. 13 is a block diagram showing a second embodiment of the ATM cell transfer system of the present invention. The second embodiment provides a further improved interface method for connecting one ATM layer device and a plurality of PHY layer devices. In the second embodiment, one ATM layer device is provided. Will be referred to as clock master XX, a plurality of PHY layer devices subordinate to clock master XX will be referred to as slave Z, one of the plurality of slaves Z will be described as slave Z1, and the other one will be described as slave Z2.
[0113]
Referring to FIG. 13, there is shown an overall block diagram and signal configuration as a second embodiment of the present invention. That is, it is composed of a clock master XX that is one ATM layer device and a slave Z that is a plurality of PHY layer devices, one of the plurality of slaves Z being a slave Z1, and the other one being a slave. The entire block is configured as Z2. The clock master XX and the slave Z (slave Z1, slave Z2) are connected by a signal line having a bus connection form as shown in FIG.
[0114]
In the second embodiment, the clock master XX has a function of only supplying a clock for cell transmission / reception to each slave Z. Each slave Z has a function of transmitting and receiving cells between the slaves Z. That is, in the first embodiment, a method of transmitting and receiving cells between a master (ATM layer device) and a slave (PHY layer device) is provided, but in the second embodiment, between a slave (PHY layer device). Only a method for transmitting and receiving cells is provided. Accordingly, each signal name shown in FIG. 13 is a signal name prefixed with “TRx” in the sense that it is a signal for transmission and reception. Signals transmitted and received between the clock master XX and the slave Z will be described with reference to FIG.
[0115]
FIG. 14 is a diagram illustrating a signal line according to the second embodiment. In FIG. 14, the clock master XX is simply referred to as a master, and the slave Z is simply referred to as a slave.
[0116]
In FIG. 14, since each signal is a signal for cell transmission / reception, there is no distinction between transmission and reception.
[0117]
The signal in FIG. 14 is substantially the same as the signal line of the interface of the first embodiment shown in FIG. 2B, except that the RxEnb * signal is deleted. This will be described in detail below.
[0118]
TRxClk in FIG. 14 is a transmission / reception clock signal transmitted from the master to the slave, and the slave performs a signal transmission / reception operation in synchronization with the transmission / reception clock signal.
[0119]
TRxReqA [N..0] is a signal line from which a slave that wants to transmit a cell to another slave outputs its own address in order to acquire the right to transfer the cell, and is composed of N + 1 bits. Since TRxReqA [N..0] is N + 1 bits, there is no limit on the upper limit of the number of slaves that can be connected to one master, as described for RxReqA [N..0] in FIG. It becomes. TRxReqA [N..0] is sent from one slave to another.
[0120]
TRxData [M..0] is a cell transmission / reception data signal that the slave transmits / receives to / from other slaves. In the 8-bit mode with M value of 7, TRxData [7..0] 8 transmission / reception data buses In the 16-bit mode where the value of M is 15, the expansion bus of TRxData [15..8] is used.
[0121]
TRxAcq * is a signal that is output from a slave to another slave when a certain slave acquires the transfer right of the cell.
[0122]
TRxSOC is a signal indicating the head of a cell to be transmitted / received, and is transmitted from a slave to another slave.
[0123]
Next, the configuration of the slave Z will be described with reference to FIG.
[0124]
FIG. 15 is a detailed block diagram illustrating a configuration of a slave (PHY layer device) in the second embodiment.
[0125]
In FIG. 15, the slave Z includes a cell transmission / reception control unit 50, an arbitration unit 51, and a cell transfer request unit 52.
[0126]
Then, the slave Z inputs the TRxClk signal from the clock master XX by the cell transmission / reception control unit 50 and the arbitration unit 51 and uses it as a reference clock for cell transmission / reception. When the cell transmission / reception cell signal 62 is sent from the cell transfer request unit 52 to the cell transmission / reception control unit 50, the cell transmission / reception control unit 50 outputs a cell transfer acquisition request signal 60 to the arbitration unit 51, and the cell transfer right (other slave Z To acquire the right to receive a cell).
[0127]
The arbitration unit 51 having received the cell transfer acquisition request signal 60 outputs the address assigned to the slave to the TRxReqA [N..0] signal to acquire the cell transfer right. At this time, the arbitration unit 51 in the slave Z always receives the TRxReqA [N..0] signal. The arbitration unit 51 in the slave Z outputs its own address to the TRxReqA [N..0] signal, and then determines whether the cell transfer right has been acquired in the state of the input TRxReqA [N..0] signal.
[0128]
When the slave Z has acquired the right to transfer cells to another slave Z, the arbitration unit 51 in the slave Z outputs “0” to the TRxAcq * signal outside the slave Z. This informs the other slave Z that it has acquired the right to transfer cells to the other slave Z. The arbitration unit 51 also outputs a cell transfer acquisition signal 61 to the cell transmission / reception control unit 50 to inform the cell transmission / reception control unit 50 that the cell transfer right has been acquired.
[0129]
Thereafter, the cell transmission / reception control unit 50 outputs the cell to the TRxData [M..0] signal. At this time, "1" is output to TRxSOC at the first byte of the cell.
[0130]
Next, the operation of the second embodiment will be described.
[0131]
Since the second embodiment provides a method for transferring cells from a certain slave Z (for example, slave Z1) to another slave Z (for example, slave Z2), the master (described in the first embodiment) There is no cell reception operation by the ATM layer device, and another slave Z (slave Z2) receives the cell instead. Therefore, the operation of the second embodiment is the same as step S17 described in the flowchart of FIG. 4 (when the master can receive a cell, “0” is output to the RxEnb * signal (permit cell transfer is permitted)). Only where there is no operation is different from the operation of the first embodiment. The operation for a certain slave Z (slave Z1) to acquire the cell transfer right is the same as that in FIG. 4 except for step S17. For this reason, the further description about the operation | movement of 2nd Embodiment is abbreviate | omitted.
[0132]
As described above, in the second embodiment of the present invention, the master X of the first embodiment is replaced with the clock master XX, and the clock master XX only outputs the reference clock for cell transmission / reception. Yes. When each slave Z wants to transmit a cell to another slave Z, the slave Z itself performs an operation of acquiring a cell transfer right. For this reason, there is no need to consider cell transmission and reception separately in the slave Z, it is possible to integrate transmission and reception, and the number of signal lines connected between the slaves Z can be greatly reduced. Has an effect.
[0133]
【The invention's effect】
As described above, in the ATM cell transfer system of the present invention, the RxReqA [N ..] signal is provided in place of the RxAddr [4..0] signal and the slave ( When the PHY layer device) wants the master (ATM layer device) to receive a cell, the slave (PHY layer device) can output its own address and acquire the cell transfer right, so that the cell transfer efficiency can be increased. Has the effect of.
[0134]
Even if the address signal of the slave (PHY layer device) specified in UTOPIA level 2 is increased from 5 bits to multiple bits, the slave (PHY layer device) itself acquires the cell transfer right. As a result, the cell transfer efficiency is not lowered.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an ATM cell transfer system of the present invention.
FIG. 2 is a diagram illustrating a signal line according to the present embodiment.
FIG. 3 is a detailed block diagram illustrating a configuration of a transmission side of a slave (PHY layer device) in the present embodiment.
FIG. 4 is a flowchart for explaining the operation of the embodiment.
FIG. 5 is a configuration diagram illustrating a branch 1 in FIG. 4;
FIG. 6 is a timing diagram illustrating branch 1 of FIG.
7 is a configuration diagram for explaining a branch 2 in FIG. 4; FIG.
FIG. 8 is a timing diagram for explaining a branch 2 in FIG. 4;
FIG. 9 is a configuration diagram illustrating a branch 3 in FIG. 4;
FIG. 10 is a timing chart for explaining branch 3 in FIG. 4;
11 is a second configuration diagram for explaining a branch 3 in FIG. 4; FIG.
12 is a second timing diagram illustrating branch 3 of FIG. 4; FIG.
FIG. 13 is a block diagram showing a second embodiment of the ATM cell transfer system of the present invention.
FIG. 14 is a diagram illustrating a signal line according to a second embodiment.
FIG. 15 is a detailed block diagram showing a configuration of a slave (PHY layer device) in the second embodiment.
FIG. 16 is a diagram showing a connection form of signal lines between one ATM layer device (master) and a plurality of PHY layer devices (slave) in the conventional UTOPIA level 2;
FIG. 17 is a diagram for explaining a signal line of a conventional UTOPIA level 2 interface;
FIG. 18 is a timing chart when a cell is transmitted from a master (ATM layer device) to a slave (PHY layer device).
FIG. 19 is a timing chart when a master (ATM layer device) receives a cell from a slave (PHY layer device).
FIG. 20 is a detailed block diagram illustrating a configuration of a transmission side of a slave (PHY layer device) in a conventional UTOPIA level 2;
[Explanation of symbols]
V master
W slave
X Master
XX Clock master
Y slave
Z slave
10 Cell transfer controller
11 Mediation Department
12 Cell transfer request section
20 Cell transfer acquisition request signal
21 Cell transfer acquisition signal
22 Transfer cell signal
50 cell transmission / reception controller
51 Mediation Department
52 Cell transfer request section
60 Cell transfer acquisition request signal
61 Cell transfer acquisition signal
62 Transmit / receive cell signal
110 Cell transfer control unit
111 Address control unit
112 Cell transfer request section
120 Transfer cell possession signal
121 Cell transfer enable signal
122 Transfer cell signal

Claims (8)

In ATM cell transfer method of a system ATM layer device and a plurality of PHY layer devices are connected by UTOPIA level 2, in order to acquire the right to the PHY layer device to each other to transfer the cell to the ATM layer device, the The PHY layer device includes cell transfer right acquisition means configured to include a self-address output signal line that outputs the self-address to the ATM layer device , and the PHY layer device includes the ATM layer device. When it is desired to transfer a cell, the cell transfer right acquisition means acquires the right to transfer the cell and immediately transfers the cell. 2. The ATM according to claim 1, wherein the self-address output signal line is composed of arbitrary N + 1 bits, and there is no upper limit to the number of the PHY layer devices that can be subordinate to the ATM layer device. Cell transfer method. The cell transfer right acquisition means gives a high priority to the PHY layer device having a small address of the PHY layer device when a plurality of PHY layer devices attempt to acquire a right to transfer a cell simultaneously. The ATM cell transfer system according to claim 1 , wherein the ATM cell transfer system is characterized by the following. The cell transmission side configuration of the PHY layer device includes a cell transfer request unit that outputs a transfer cell signal when a cell to be received by the ATM layer device is held, and a cell transfer acquisition request signal when the transfer cell signal is input. A cell transfer control unit for outputting a cell transfer right, and when the cell transfer acquisition request signal is input, the cell transfer right acquisition means acquires a right to transfer the cell, and acquires a cell transfer right when the right to transfer the cell is acquired. The ATM cell transfer system according to any one of claims 1 to 3 , further comprising: an arbitration unit that outputs a signal to the cell transfer control unit . In an ATM cell transfer system of a system in which an ATM layer device and a plurality of PHY layer devices are connected at UTOPIA level 2, the PHY layer devices acquire the right to transfer cells to the other PHY layer devices. The PHY layer device includes a second cell transfer right acquisition unit configured to include a second own address output signal line for outputting the own address to the other PHY layer device. When the PHY layer device wants to transfer a cell to another PHY layer device, it acquires the right to transfer the cell by the second cell transfer right acquisition means, and immediately transfers the cell. ATM cell transfer method that. 6. The second self-address output signal line is composed of arbitrary N + 1 bits, and there is no upper limit to the number of PHY layer devices that can be subordinate to the ATM layer device. The ATM cell transfer system described . The second cell transfer right acquisition means assigns a higher priority to the PHY layer device having a smaller address of the PHY layer device when a plurality of PHY layer devices attempt to acquire a right to transfer cells simultaneously. The ATM cell transfer system according to claim 5 , wherein the ATM cell transfer system is provided. The PHY layer device receives a second cell transfer request unit that outputs a transmission / reception cell signal when a cell to be received by another PHY layer device is held, and acquires a second cell transfer when the transmission / reception cell signal is input. A cell transmission / reception control unit that outputs a request signal, and a right to transfer the cell by the second cell transfer right acquisition means when the second cell transfer acquisition request signal is input, and the right to transfer the cell A second arbitration unit that outputs a second cell transfer acquisition signal to the cell transmission / reception control unit when acquiring the second cell transfer acquisition signal, according to any one of claims 5 to 7 , The ATM cell transfer system described.

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