JP3643270B2 - Data processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data processing apparatus capable of easily processing data in formats having different byte polarities.
[0002]
[Prior art]
When placing data on a memory where an address is assigned to each byte, and the bits in the byte are also numbered to indicate the order, the upper side of the data is placed on the larger address side of the memory or on the smaller address side. Many discussions have been made on whether to arrange them.
The method of placing the upper side of data at a large address in the memory and placing the lower side of data at a small address in the memory is called little endian. The upper side of data is placed at a small address in the memory, and the lower side of the data The method of arranging the memory at a large address in the memory is called big endian.
[0003]
In recent data processing apparatuses, the memory address is generally assigned to each byte with 8 bits as 1 byte. However, when handling a bit display with a bit length that is not an integer multiple of bytes, a bit address indicating the bit position is required in addition to the byte address, and the concept of little endian and big endian is attached to the bit address. Exists. The byte polarity indicating whether the byte and the bit are little endian or big endian and the bit polarity do not necessarily have to coincide with each other. D. Cohen, "On Holy Wars and a Plea for Peace," Computer, Vol. 14, NO.10, as to whether little endian or big endian is preferred , Oct. 1981, pp. 48-54.
[0004]
[Problems to be solved by the invention]
Little-endian and big-endian problems exist not only for byte and bit addresses in memory, but also for byte and bit positions on registers.
When data with a byte length and bit polarity both big endian is stored in a register with a byte length shorter than the byte length of the register, the data is stored closer to the smaller address as in the memory. An example of this is shown in FIG.
[0005]
In this case, the bit address indicating the bit position is the same regardless of the data size on the register, but when performing arithmetic operations such as addition between binary data having different data sizes stored in the two registers. This is a problem because the least significant bits of the data are not complete. Arithmetic operations require that the least significant bit of the data be aligned, and in this case, the shorter data is arithmetically shifted to the right to perform the operation after aligning the larger data with the least significant bit position. There is a need. If the hardware for performing this arithmetic shift is connected to the register input / output unit or the ALU input / output unit, the hardware of the data processing apparatus increases. Further, there is a problem that the operation speed is reduced if machine language instructions or microprograms are used.
[0006]
In the microprocessor MC68000 series manufactured by Motorola, USA, this problem is avoided by setting the byte polarity to little endian and the bit polarity to little endian as shown in FIG. However, in this case, since the bit polarity and the byte polarity are different, there is a problem that the burden of software design is heavy, for example, when the byte sequence and the bit sequence are handled, it is necessary to reverse the data address calculation order.
If both byte polarity and bit polarity are set to little endian, there is no problem with operations between different-size operands, but problems specific to little endian when handling BCD numbers and string data remain. The little endian-specific issues are detailed in the above D. Cohen paper.
[0007]
Further, when data processing devices having different byte polarities are incorporated in the same system, there is a problem that a coupling bus between these devices becomes complicated. A specific example of combining data processing devices having different byte polarities is described in H. Kirrmann, “Data Format and Bus Compatibility in Multiprocessors”, IEEE Micro August 1983, pp. 32-47.
[0008]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a data processing device that can easily handle data for other data processing devices that handle data with different byte-byte polarities. To do.
[0009]
[Means for Solving the Problems]
According to the data processing device of the present invention, 8N-bit data (N is an integer of 4 or more) representing one binary value, the N bytes to be concatenated are closer to the lower digit side of the data. Big endian placed at the large address of the memory addressed every time, and Little placed at the larger address of the memory addressed per byte as the N bytes are on the higher digit side of the data Handled by the byte polarity of either endian. A plurality of instructions decoded by the instruction decoding mechanism includes a source operand designation part for designating 8N-bit data representing one binary value, and a first opcode part for designating processing for reversing the byte order. byte reverse instructions having, and includes a first operand specified portion and a second operand specifying part which specifies the two registers, the addition instruction and a second opcode portion specifying a process for performing addition operation. The execution mechanism is connected to the register file including a plurality of registers each having a width of 8N bits, the first, second and third buses, and the first and second buses, and according to control information corresponding to the byte reverse instruction. The 8N-bit data designated by the byte reverse instruction is input via the first bus, and the process of reversing the arrangement order of the N bytes to be connected is executed. A byte order reversing circuit that is transferred through two buses and stored in one of a plurality of registers, and is connected to first to third buses, and is connected between the first and second buses. is connected in parallel with the byte order reversal circuit, in accordance with control information corresponding to the add instruction, the two read through the first and third bus from each of two registers specified by the add instruction 8 Adds reads bit data, having the ALU outputs the addition result to the second bus. The two registers designated by the addition instruction are in the register file, and the addition instruction can designate a register in which inverted 8N-bit data is stored as one of the two designated registers.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The device of the present invention is described in detail in the name of the invention “data processing device” (Japanese Patent Application No. 62-247418) according to the application of the present applicant.
[0011]
First, the data processing apparatus of the present invention employs big endian for both the byte polarity and bit polarity of data. As shown in Fig. 1, when data with a byte length smaller than the register byte length is placed on the register, the bit number on the register of the data is shifted, and the least significant bit is set regardless of the size. Store the data in alignment. When the bit position of data on the register is indicated, the bit position for the data on the register is set to 8 bits in size n smaller than bit number 8 based on the data size and bit number indicated by the instruction. The same register bit position is determined when the size is 16 bits and the bit number is n + 8, and when the size is 32 bits and the bit number is n + 24.
[0012]
FIG. 4 is a block diagram showing the overall configuration of the data processing apparatus according to the present invention.
In FIG. 4, (1) is an instruction fetch unit which sends an address to the memory (10) through the address bus (8) and fetches an instruction from the memory (10) through the data bus (9).
(2) is an instruction decode unit that receives an instruction from the instruction fetch unit (1), decodes it, and outputs information necessary for executing the instruction.
[0013]
(3) is stored in the micro ROM (7) based on information such as the microprogram entry address or general-purpose register number, operand, and data size output from the instruction decode unit (2) and executes the instruction. A microprogram entry address indicating the start address of the program is output to the microprogram counter (6), and the microinstruction and instruction decode unit output from the microROM (7) according to the addresses sequentially designated by the microprogram counter (6) The instruction execution control unit executes the instruction by controlling the instruction execution unit (5) based on the other information output from (2).
(4) When an operand required for instruction execution is in the memory (10), the address is output to the address bus (8) and the operand is fetched through the data bus (9), or the operand is stored in the memory (10). Is an operand access unit that outputs the address to the address bus (8) and outputs the operand to the data bus (9).
[0014]
FIG. 5 is a block diagram showing details of the instruction execution unit (5) shown in FIG.
(11) is a register file for storing operand data.
(12), (13), (14), and (15) are arithmetic units, respectively. Note that (12) is an ALU that performs arithmetic operations such as addition of two binary numbers and logical operations such as logical product of two bit strings.
(16) and (17) are expansion circuits that zero-extend or sign-extend the data size to the data size handled by ALU (12) when data smaller than that of ALU (12) is input to ALU. .
(13) is a barrel shifter that shifts data to the right or left multiple bits at a time.
(14) is a byte forward reversing circuit for reversing the byte sequence of the byte string, and (15) is a bit forward reversing circuit for reversing the bit order of the bit string.
(18), (19), and (20) are the S1 bus, S2 bus, and D bus, respectively, which connect the register file (11) and the arithmetic units (12), (13), (14), and (15). is there.
Register file (11) is connected in parallel to arithmetic units (12), (13), (14), (15) such as ALU (12) via buses (18), (19), (20) in 32-bit parallel doing. There is a one-to-one correspondence between the bit storage position of the register file (11) and the input / output bit position of the ALU (12).
[0015]
FIG. 6 is a block diagram showing a detailed structure of the register file (11) shown in FIG.
(21), (22), and (23) are circuits for storing data in bit positions 0 to 15, 16 to 23, and 24 to 31, respectively.
A register input control circuit (24) stores data by controlling an input circuit of a necessary data storage position according to the size of data to be input to the register file (11) and the register number of the register to be input.
(25) inputs the register number of the register that stores the data to be output for each bus from the register file (11) and controls the output of the data in the register to the S1 bus (18) and S2 bus (19) It is a register output control circuit.
[0016]
Note that there are 32 portions (26) surrounded by a broken line in FIG. 6 in the register file (11), and each can be distinguished from R0 to R31 in the microprogram of the data processing apparatus of the present invention.
[0017]
FIG. 7 is a block diagram showing a detailed configuration of the byte forward reversing circuit (14) shown in FIG.
In this circuit, the 4-byte data input from the S2 bus (19) is put into the BYI register RBYI, and the data in which the array order of the bytes is reversed by the wiring that intersects 8 pieces at a time is transferred to the BYO register RBY0. The value of RBYO is output to D bus (20).
[0018]
FIG. 8 is a block diagram showing a detailed configuration of the bit forward inversion circuit (15) shown in FIG.
In this circuit, the 4-byte data input from the S2 bus (19) is put into the BII register RBII, the data whose bit order is reversed by crossing wiring is transferred to the BIO register RBI0, and the value of the BIO register RBIO is transferred to the D bus ( Output to 20).
[0019]
FIG. 9 is a block diagram showing a configuration of a part of circuits included in the instruction execution control unit (3) of FIG.
(27) is a bit position number output circuit for outputting a number indicating the bit position on the register to the S1 bus (18) based on the size information and bit number of the operand designated by the instruction. (28) is a circuit for outputting the constant 1 to the S2 bus (19), and outputs "1" to the least significant bit of the S2 bus (19) and "0" to all other bits.
[0020]
The operation of the data processing apparatus of the present invention will be described below.
Signed addition instruction that adds the 32-bit signed binary number stored in register R0 and the 8-bit signed binary number stored in register R1 to store in register R1 as an 8-bit signed binary number (In the data processing apparatus of the present invention, it is expressed as “ADD R0.W R1.B” and the bit pattern of the instruction code is as shown in FIG. 10). An operation for performing an operation between different size operands will be described.
[0021]
The instruction is fetched from the memory (10) by the instruction fetch unit (1) shown in FIG. 4, decoded by the decode unit (2), and the decode result is passed to the instruction execution control unit (3). The instruction execution control unit (3) uses the two register addresses indicating the register R0 and the register R1, the size of the operand stored in the register R0, and the size of the operand stored in the register R1 as parameters. The entry address of the signed addition program routine stored in is set in the microprogram counter (6), the microinstruction is read, and the signed addition instruction is executed.
[0022]
FIG. 11 is a flowchart showing the execution sequence of the signed addition instruction in the instruction execution control unit (3).
The two register numbers are input to the register output control circuit (25) independently of the microprogram, the data in the register R0 is transferred to the ALU (12) through the S1 bus (18), and the data in the R1 is transferred to the S2 bus. It is transferred to ALU (12) through (19). At this time, all 32 bits of the contents of register R1 are output to the S2 bus (19), but the lower 8 bits of the S2 bus (19) are sign-extended by the expansion circuit (17) and input to the ALU (12). Is done. In ALU (12), a signed addition of two 32-bit binary numbers is performed and a 32-bit signed binary number is output. At this time, the ALU (12) is simultaneously instructed that the register size for storing the signed addition result is 8 bits, and whether the addition result can be expressed by a binary number within 8 bits, or the addition result. Various control flags are set according to whether is positive, negative or zero.
The 32-bit output of ALU (12) is transferred to register R1 through D bus (20). The 32-bit data transferred on the D bus (20) is stored in the register R1 selected by the register input control circuit (24) only in the lower 8 bits in the bit positions 24 to 31, which are the lower 8 bits. Is done.
[0023]
Next, the actual operation of the embodiment will be described by taking as an example a bit set instruction that sets '1' to the bit corresponding to bit position 3 of the operand in register R0.
In the data processing device of the present invention, the bit set instruction has the bit pattern of the instruction code as shown in FIG. In the data processing apparatus of the present invention, the bit position on the register is as shown in FIG. 1. Therefore, depending on whether the operand size is 1 byte, 2 bytes or 4 bytes, this bit set instruction is “BSET # 3”. R0.B, BSET # 11 R0.H, BSET # 27R0.W ”. The flowchart of FIG. 13 shows the execution sequence of the bit set instruction in the instruction execution control unit (3).
[0024]
In the bit set instruction, the bit position number output circuit (27) of FIG. 14 is used to obtain a number indicating the bit position of the register. The instruction execution control unit (3) inputs the operand size and bit number to the bit position number output circuit (27) and outputs the bit position number to the S2 bus (19). The bit position number output circuit (27) outputs (bit number 3 + 24 = 27) to the S1 bus (18) when the size information is 1 byte, and (bit number 11 + 16 = 27) when the size information is 2 bytes. Output to S1 bus (18). When the size information is 4 bytes, the bit number 27 is output as it is to the S1 bus (18).
[0025]
The bit position number output from the bit position number output circuit (27) is input as shift number designation data of the barrel shifter (13) through the S1 bus (18). At the same time, the constant “1” is input to the barrel shifter (13) as the shifted number through the S2 bus (19). As a result, the barrel shifter 13 outputs a 32-bit bit pattern in which only bit number 27 is “1” and all other bits are “0”. This bit pattern is once stored in the register R16 which is a working register. Next, the logical sum operation of the contents of the registers R0 and R16 is performed by the ALU (12). At this time, the extension circuit (17) and the register input control circuit (24) operate in the same manner as in the case of execution of the signed addition instruction depending on the byte length of the operand in the register R0.
[0026]
Next, the operation of a byte reverse instruction for reversing the arrangement order of the 32-bit data bytes in the register R0 and transferring it to the register R1 will be described.
The instruction code bit patterns byte reverse instruction shown in Figure 15. FIG. 16 is a flowchart showing an execution sequence of the byte reverse instruction in the instruction execution control unit (3).
The 32-bit data in the register R0 is sent to the BYI register RBYI of the byte order reversing circuit (14) through the S2 bus (19), and the 32-bit data in which the byte arrangement order is reversed is transferred from the BY0 register RBY0 to the D bus ( 20) through register R1 .
[0027]
Next, the operation of a bit reverse instruction for reversing the bit order of 32-bit data in the register R0 and transferring it to the register R1 will be described. The instruction code bit patterns of the bit reverse instruction shown in FIG. 17. FIG. 18 shows a flowchart of the execution sequence of the bit reverse instruction in the instruction execution control unit (3).
The 32-bit data in the register R0 is sent to the BII register RBII of the bit order reversing circuit (15) through the S2 bus (19), and the 32-bit data whose bit order is reversed is transferred from the BI0 register RBI0 to the D bus (20). Through the register R1 .
[0028]
In the above embodiment, an example is shown in which hardware is used to determine the bit position number in the register. However, a microprogram is prepared separately for each byte length of the operand, and the bit number is corrected by the microprogram to correct the bit number. The position may be obtained.
[0029]
In the above embodiment, an arithmetic function between operands of different sizes is described using a signed addition instruction between operands on a register as an example, but other arithmetic operations of addition, subtraction, multiplication, and division are used in the same way for all other arithmetic operations. Can be calculated.
[0030]
Also, have been described and byte reverse instruction and the bit reverse instruction for 32-bit data only in the above embodiments, the operation of the byte order reversal circuit of the above embodiment (14) or the bit order reversing circuits (15) a barrel shifter When combined with the operation of (13), a byte reverse instruction and a bit reverse instruction can be executed for data of other sizes by a microprogram. The same effect can be obtained by executing these two instructions by a microprogram using only the ALU (12) or barrel shifter (13) and the working register.
[0031]
【The invention's effect】
As described above, in the data processing apparatus of the present invention, the byte reverse instruction is executed to reverse the array order of N bytes to which 8 N-bit data representing one binary value is connected, before conversion. Is converted into data that can be handled with a byte polarity different from the byte polarity of the data processing device itself. Addition is executed by the add instruction, but since the add instruction can specify a register in which data converted by the byte reverse instruction is stored as one of the two registers specified as the operand, the data processor itself When the addition is performed using data defined by a byte polarity different from the byte polarity, the addition can be executed after converting to a correct value. In particular, since the program designer can convert data expressing a correct value with one instruction and thus does not put a burden on the design of the program, a data processing apparatus capable of reducing the cost of software development can be realized.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing storage positions and bit numbers of data when 1-byte, 2-byte, and 4-byte data are stored on a 4-byte byte length register of the data processing apparatus of the present invention. .
FIG. 2 is a schematic diagram showing an example in which data having a byte length shorter than the register byte length is stored in the register in a data processing apparatus in which both the byte polarity and the bit polarity are big endian, and stored closer to the smaller address side. FIG.
FIG. 3 is a schematic diagram when the byte polarity is set to big endian and the bit polarity is set to little endian.
FIG. 4 is a block diagram showing the overall configuration of the device of the present invention.
FIG. 5 is a block diagram illustrating a configuration of an instruction execution unit.
FIG. 6 is a block diagram illustrating a configuration of a register file.
FIG. 7 is a block diagram showing a configuration of a byte forward reversing circuit.
FIG. 8 is a block diagram showing a configuration of a bit forward reversing circuit.
FIG. 9 is a block diagram illustrating a partial configuration of an instruction execution control unit.
FIG. 10 is a schematic diagram showing a bit pattern of a signed addition instruction of the device of the present invention.
FIG. 11 is a flowchart showing an execution sequence of a signed addition instruction.
FIG. 12 is a schematic diagram of a bit pattern of an instruction code.
FIG. 13 is a flowchart showing an execution sequence of a bit set instruction.
FIG. 14 is a circuit diagram showing a configuration of a bit position number output circuit.
FIG. 15 is a schematic diagram showing an instruction code bit pattern of a byte reverse instruction.
FIG. 16 is a flowchart showing an execution sequence of a byte reverse instruction.
FIG. 17 is a schematic diagram showing an instruction code bit pattern of a bit reverse instruction.
FIG. 18 is a flowchart showing an execution sequence of a bit reverse instruction.
[Explanation of symbols]
RBYI ·· BYI register, RBYO ·· BYO register, RBII ·· BII register, RBIO ·· BIO register, 1 ·· Instruction fetch unit, 2 ·· Instruction access unit, 3 ·· Instruction execution control unit, 4 · Operan Access unit, 5 ... Instruction execution unit, 6 ... Micro program counter, 7 ... Micro ROM, 11 ... Register file, 12 ... ALU, 13 ... Barrel shifter, 14 ... Byte forward reversal circuit, 15 ... Bit forward reversing circuit In the figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

1. An 8N-bit data (N is an integer of 4 or more) representing one binary value, and the address of each byte is such that the N bytes to be concatenated are on the lower digit side of the data. Either a big endian placed at a large address of the attached memory, or a little endian placed at a large address of the memory addressed for each byte so that the N bytes are on the higher digit side of the data A data processing device handled by the byte polarity of one of them,
An instruction decoding mechanism for decoding each of a plurality of encoded instructions and outputting control information corresponding to each instruction;
An operation mechanism that performs an operation according to control information from the instruction decode mechanism and executes processing specified by each of the plurality of instructions;
The plurality of instructions includes a byte reverse instruction having a source operand designating part for designating 8N-bit data representing one binary value and a first opcode part for designating a process for reversing the order of bytes . And an add instruction having a first operand designating part and a second operand designating part for designating two registers, and a second opcode part for designating processing for performing an addition operation,
The execution mechanism is:
A register file containing a plurality of registers each 8 N bits wide;
First, second and third buses;
This is connected to the first and second bus, in accordance with control information corresponding to the byte reverse instruction, enter the 8N-bit data specified by the byte reverse command through the first bus and the coupling A byte order reversing circuit that performs a process of reversing the arrangement order of N bytes, and the inverted 8N-bit data is transferred via the second bus and stored in one of the plurality of registers. When,
It is connected to the first to third bus, between the first and second bus is connected in parallel with the byte order reversal circuit in accordance with the control information corresponding to the add instruction, designated by the addition instruction ALU for reading out and adding two 8N-bit data read from the two registers through the first and third buses respectively, and outputting the addition result to the second bus,
The two registers designated by the addition instruction are in the register file, and the addition instruction designates a register in which the inverted bit data is stored as one of the two designated registers. Data processing device that can.
2. The byte reverse instruction designates one register in a register file as 8N bit data representing one binary value, and the 8N bit data inputted to the byte order reversing circuit is: The data processing device according to claim 1, wherein the data processing device is stored in a register designated by the byte reverse instruction.
3. The data processing apparatus according to claim 1, wherein N is four.

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