JP3645792B2 - Signal waveform shaping circuit and shaping method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal waveform shaping circuit and a shaping method thereof, and more particularly to a signal waveform shaping circuit of a MIL-STD-1553B data bus signal and a shaping method thereof.
[0002]
[Prior art]
The MIL-STD-1553B data bus uses a biphase code,
An example of prior art related to bi-phase code waveform shaping JP No. 63-148743 (hereinafter referred to as prior art). FIG. 13 is a block diagram of the waveform shaping device disclosed in this prior art. Referring to the figure, first, the biphase code signal 101 is waveform-shaped by the comparator 102, the edge is detected by the edge detection circuit 103, and is taken into the CPU 104. The CPU 104 starts counting with a clock of 16 times the bit rate with the first edge signal as the start of sampling. When the next edge is detected, if the count value is a specified value, an output operation is performed. However, when the value is not a specified value, it is recognized that the phase is shifted, that is, the signal waveform is distorted, the difference is calculated, and the timing of the output operation is moved back and forth according to the value.
[0003]
Next, the biphase code will be described. FIG. 14 is a waveform diagram of an example of a biphase code. Referring to FIG. 14, when the code shown in FIG. 14A is biphase modulated, the edge rises when “0” and the edge falls when “1”, resulting in a waveform as shown in FIG. . On the other hand, if the code difference (exclusive-exclusive OR of adjacent bits) in FIG. The waveform shown in FIG. 6B corresponding to the code shown in FIG. 6C is a waveform obtained by differential biphase modulation.
[0004]
[Problems to be solved by the invention]
The first problem is effective when the biphase code signal is in a single stream format (a signal having a binary value of 0 or E (E is a positive real number)) in the prior art, but the MIL-STD1553B bus In the case of the double flow format (a signal having three values of -E, 0, + E), there is a drawback that it cannot be ternary.
[0005]
The reason is that the comparator can only output a binary value by the threshold voltage and cannot encode a signal having a ternary value.
[0006]
The second problem is that the conventional technique is effective when waveform distortion occurs in the middle of the received signal, but if the first edge is around the original timing, the sampling timing is shifted. There is a drawback that accurate signal reproduction cannot be performed. In particular, the MIL-STD-1553B data bus signal is composed of SYNC (synchronization) bits + data bits, but the allowable value of the signal width variation of the first 1.5 bits of the SYNC bit is not strictly specified. Therefore, there is a risk of erroneous data bit sampling in the conventional method.
[0007]
This is because the conventional technique uses the first edge signal as a reference signal for the subsequent processing, and therefore the subsequent processing timings are all shifted when the first edge signal generation timing is shifted. In particular, since the first edge (SYNC bit) of the signal on the MIL-STD-1553B data bus fluctuates, there is a disadvantage that accurate sampling cannot be performed.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to provide a signal waveform shaping circuit capable of absorbing fluctuations in the signal width of a double flow type biphase code signal, particularly a MIL-STD-1553B data bus signal, and a shaping method thereof. .
[0009]
[Means for Solving the Problems]
To solve the above-mentioned problems, the present invention The signal waveform shaping circuit by , A signal waveform shaping circuit for shaping an input signal that takes three values and takes an intermediate value only before the start of data and after the end of data. Input signal the first First storage means for storing data at a fixed period starting from the rising time; the first Continues at the rise the first Second storage means for storing data stored in the first storage means at a fixed period starting from the rising time, and the data stored in the second storage means is output in time series Features.
[0010]
Also according to the present invention The signal waveform shaping method is a signal waveform shaping method for shaping an input signal that takes three values and takes an intermediate value only before the start of data and after the end of data. Input signal the first A first step of storing data in the first storage unit at a fixed period starting from the rising time; the first Continues at the rise the first A second step of storing the data stored in the first storage unit in the second storage unit at a fixed period starting from the rising time, and the data stored in the second storage unit is output in time series It is characterized by that.
[0011]
According to the present invention By using the first and second storage means and shifting the timing at which the input signal is stored in the storage means, it becomes possible to absorb the fluctuation of the signal width of the input signal. Further, the input signal is stored in the first storage means starting from the rising edge of the input signal, and the input signal from the first storage means is stored in the second storage means starting from the falling edge of the input signal. Therefore, even when the first edge of the input signal is around the original timing, it is possible to absorb the fluctuation of the signal width of the input signal. Furthermore, since it is possible to provide signal conversion means for converting a ternary signal into a binary signal, the present invention can be applied to a double-flow signal such as a MIL-STD1553B bus.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
First, an outline of the present invention will be described. Referring to FIG. 1, the above-described problems are a receiver 1 that performs logical level conversion (converting three values into two values), a transmitter 6 that performs logical level conversion (converting two values into three values), and signal edges. Edge detection circuit 2 that performs detection, sample timing generation circuit 3 that generates a data capture signal, primary storage circuit 4 and secondary storage circuit 5 that store sampled data, and bit rate of the input biphase code signal This is solved by a clock signal generator 7 which generates a frequency 16 times that of the clock signal generator 7.
[0013]
The input MIL-STD-1553B data bus signal is decoded with a threshold voltage of + V (V is a positive real number) and a threshold voltage of −V, and is converted into a ternary value by a combination of the outputs. The output of the receiver 1 is input to the edge detection circuit 2. The edge detection circuit 2 detects the rise and fall and notifies the sample timing generation circuit 3 of the signal. The sample timing generation circuit 3 outputs a take-in signal to the primary storage circuit 4 and the secondary storage circuit 5 from the first rise from the edge detection circuit 2 and the fall that occurs after the first rise (first fall). The primary storage circuit 4 and the secondary storage circuit 5 perform sampling only when the above-described capture signal arrives. The generation timing of the capture signal differs depending on which part of the currently arriving signal is currently input, and is divided into three types (first, middle and last). The timing of this operation is changed according to the following three characteristics of the signal waveform of the MIL-STD-1553B data bus.
[0014]
(1) The signal width of the head part (SYNC bit) varies depending on the load.
(2) The signal width of the intermediate part is constant.
(3) The signal width of the tail part (parity bit) is increased.
[0015]
In consideration of the above characteristics, the fluctuation of the signal width is absorbed by shifting the timing of the sample in the primary storage circuit 4 and the sample in the secondary storage circuit 5. Then, after the waveform is shaped to a predetermined signal width at the output of the secondary storage circuit 5, it is converted into a signal level of the MIL-STD-1553B data bus by the transmitter 6 and transmitted.
[0016]
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a preferred embodiment of a signal waveform shaping circuit according to the present invention. Referring to the figure, the signal waveform shaping circuit includes a receiver 1 that performs logical level conversion (converting three values into two values), a transmitter 6 that performs logical level conversion (converting two values into three values), and signal edges. Edge detection circuit 2 that performs detection, sample timing generation circuit 3 that generates a data capture signal, primary storage circuit 4 and secondary storage circuit 5 that store sampled data, and bit rate of the input biphase code signal And a clock signal generator 7 for generating a frequency 16 times as high as the above.
[0017]
First, the signal format of the MIL-STD-1553B data bus will be described. FIG. 2 is a schematic diagram showing a signal format of the MIL-STD-1553B data bus. Referring to the figure, all signals transferred on the MIL-STD-1553B data bus are SYNC bit (3 bits) + data bit (16 bits) + parity bit (1 bit) as shown in FIG. ) Of 20 bits is defined as one word, and a plurality of words of up to 32 words can be transferred as shown in FIG. The MIL-STD-1553B data bus has a signal level of 0 V when there is no signal and + E or -E when there is a signal, as shown in FIG.
[0018]
FIG. 3 is a waveform diagram of one word. As shown in the figure, the SYNC bit has a 1.5-bit period + E, and the next 1.5-bit period has a voltage level of -E. The data bits and parity bits employ biphase codes, and logical levels “1” and “0” are defined as shown in FIG. FIG. 4 is a waveform diagram showing the definition of the logic level. That is, referring to the figure, when the first half bit of the 1-bit width is + E and the latter half bit is −E, the logic level is “1”, the first half bit is −E, and the latter half 1 / bit. When 2 bits are + E, the logic level is “0”.
[0019]
Next, the present invention will be described. When the signal of the MIL-STD-1553B data bus shown in FIGS. 2 to 4 is digitally processed and input to the receiver 1 having the threshold voltages of + V and −V, the receiver 1 shows in FIG. Such an output is obtained. FIG. 5 is a diagram showing an input waveform and an output waveform of the receiver 1. FIG. 1A shows an input waveform, and FIG. 2B shows an output waveform.
[0020]
By performing this processing, the receiver 1 converts the signal of the MIL-STD-1553B data bus having three values of + E, 0, and -E into a binary value having a 2-bit width, thereby enabling digital processing. In the example of FIG. 5, when the signal level of MIL-STD-1553B is + E, digital data 1 and digital data 2 are (1, 0), -E is (0, 1), and 0v (no signal). It turns out that becomes (0,0).
[0021]
Note that the digital data 1 and the digital data 2 in FIG. 5B correspond to the digital data 1 and the digital data 2 (output of the receiver 1) in FIG. Digital data 1 and 2 are sent to an edge detection circuit 2, a sample timing generation circuit 3 and a primary storage circuit 4.
[0022]
The edge detection circuit 2 detects rising and falling. As shown in FIG. 5, when the MIL-STD-1553B data bus is in the no-signal state, the digital data 1 and 2 are (0, 0). When the signal arrives, the SYNC bit is input first, so that the digital data 1 and 2 change to (1, 0). The edge detection circuit 2 detects this signal change and outputs a rising signal to the sampling timing generation circuit 3. Subsequently, when the latter half 1.5 bits of the SYNC bit arrive, the digital data 2 changes from (1, 0) to (0, 1). Data bits after the SYNC bit change in the same manner. The edge detection circuit 2 detects the signal change described above and outputs a rising signal and a falling signal to the sample timing generation circuit 3.
[0023]
Here, the characteristics of the MIL-STD-1553B data bus will be described. FIG. 6 is a signal waveform diagram showing characteristics of the MIL-STD-1553B data bus. When the MIL-STD-1553B data bus is ideal, the SYNC signal width is 3 bits (1.5 bits + E and 1.5 bits -E) and the parity bit is 1 bit as shown in FIG. Should be.
[0024]
However, actually, as shown in FIG. 6 (2), the signal width of the first half of the SYNC bit of the first word (+ E SYNC bit) and the latter half of the parity bit of the last word when no signal is changed to a presence signal, It becomes larger than the signal width of other bits. The reason is that the intermediate bits (bits other than the first half of the SYNC bit and the second half of the parity bit) transition from -E to + E or + E to -E, while the first SYNC bit transitions from 0 to + E. Therefore, a difference in signal width occurs due to a difference in rising / falling characteristics.
[0025]
In particular, in the latter half of the parity bit, when + E or −E changes to 0, the charge remaining on the data bus is discharged by the load capacitance, and the potential decreases with a time constant. It gets bigger. However, since the signal width of intermediate bits is defined by the MIL-STD-1553B data bus standard, the signal width does not increase. As described above, the MIL-STD-1553B data bus signal has the following three characteristics depending on the bit position.
[0026]
(1) The signal width of the first half portion of the SYNC bit when a non-signal becomes a presence signal becomes large.
{Circle around (2)} The signal width of the latter half of the parity bit when a signal is changed to no signal is increased.
(3) The signal width of the portion other than (1) and (2) is not increased.
[0027]
Considering the above characteristics, the sampling timing generation circuit 3 needs to generate the data capture signals 1 and 2.
[0028]
Next, the operation of the sample timing generation circuit 3 will be described. The sample timing generation circuit 3 outputs data capture signals 1 and 2 from the rising and falling signals from the edge detection circuit 2 generated at the timing described above and the digital data 1 and 2 from the receiver 1. When the primary storage circuit 4 receives the data capture signal 1 and the secondary storage circuit 5 inputs the data capture signal 2, the input data is latched. That is, the above-described fluctuation in the signal width of MIL-STD-1553B is captured in the primary storage circuit 4 in conjunction with the generation timing of the capture signal in the sample timing generation circuit 3 and captured at a fixed timing in the secondary storage circuit 5. The waveform shaping function is realized by outputting.
[0029]
FIG. 7 is a configuration diagram of an example of the sample timing generation circuit 3. As shown in the figure, the sample timing generation circuit 3 includes a sequencer 11, a 1/2 bit counter 12, and a 1/2 bit width delay circuit 13. The sequencer 11 inputs the digital data 1 and 2, the rising signal and falling signal, and the count value of the ½ bit counter 12, and outputs the data capture signal 1.
[0030]
The 1/2 bit counter 12 receives the data capture signal 1 and outputs a count value to the sequencer 11. The 1/2 bit counter 12 counts the pulse of the data capture signal 1 generated every 1/2 bit. The count range is from 1 to 40, and the last 0.5 bits in one word (of the parity bit). The timing is set to indicate 40 when the second half part) is received. Therefore, when one word is continuous as in the case of transferring a plurality of words, the count value becomes 1 at the head of the next word (SYNC part).
[0031]
FIG. 8 is a schematic diagram showing the relationship between the waveform of the digital data 1 and 2 and the count value. FIG. 2A shows the relationship between the waveform of the normal digital data 1 and 2 and the count value, and FIG. 2B shows the waveform and the count value of the abnormal digital data 1 and 2 with the end waveform extended. Shows the relationship.
[0032]
As shown in FIG. 1A, the normal digital data 1 and 2 waveforms are numbered (count values) from 0 to 39 in order. On the other hand, numbers (count values) from 0 to 40 are attached to the waveforms of abnormal digital data 1 and 2 as shown in FIG. That is, the 1/2 bit counter 12 according to the present invention counts from 1 to 40 on the assumption that the waveform at the end extends.
[0033]
The 1/2 bit width delay circuit 13 delays the signal of the data capture signal 1 by a 1/2 bit width and outputs the signal as the data capture signal 2.
[0034]
Next, the operation of the sample timing generation circuit 3 will be described. FIG. 9 is a flowchart showing the operation of the sample timing generation circuit 3, and FIGS. 10 to 12 are timing charts of the circuit.
[0035]
First, when the MIL-STD-1553B data bus is in the no-signal state, the signal level is 0 V, so the digital data 1 and 2 are (0, 0), and therefore A → S1 (no signal) in FIG. → Go around the loop of A. The sequencer 11 performs the determination of no signal and presence signal. When the digital data 1 and 2 are (0, 0) or (1, 1), there is no signal, and (1, 0) or (0, 1 ) Is a signal.
[0036]
Next, when a signal is input from the MIL-STD-1553B data bus, since the SYNC signal is input first, the digital data 1 and 2 become (1, 0). The edge detection circuit 2 outputs a rising signal P1 (see P1 in FIG. 10).
[0037]
The sequencer 11 transitions from the above-described digital data 1 and 2 and the rising signal P1 to A → S1 → S2 → S3 → S4 in FIG. Here, after the lapse of the 1/4 bit width of S3, whether the signal detected data is noise or normal is the transition to the S4 no signal / present signal determination sequence again. It is provided for determination (in the present invention, a signal having a signal width of 1/4 bit width or more is determined as a normal signal).
[0038]
If it is determined in S4 that the signal is a signal, the sequencer 11 outputs a data capture signal 1 (P2) in S5 (see P2 in FIG. 10), and the primary storage circuit 4 outputs the digital data 1 and 2 at that time, That is, (1, 0) is stored as a sample.
[0039]
After one sample of the SYNC signal is performed by the data capture signal 1, the sequencer 11 transitions to B and determines whether or not the falling signal from the edge detection circuit 2 is input (S7). If no falling signal is input (in the case of NO in S7), in S8, the process transits from S8 to B until the time of 1/2 bit width elapses after the data capture signal 1 of S5 is output, When the ½ bit width elapses, a transition is made from S8 to S9 to B, and the second data capture signal 1 (P3) is output (see P3 in FIG. 10).
[0040]
Such a transition is performed up to the first 1.5 bits of the SYNC signal. Since the MIL-STD-1553B data bus has 1.5 bits in the first half of the SYNC signal, it should theoretically be sampled once in S5 and twice in S9 (three times in total). However, because of the characteristics of MIL-STD-1553B, the signal width of the first half of the SYNC signal is increased, so in practice it is performed a total of four times as indicated by P2 to P5 in FIG. 10 until a falling signal arrives.
[0041]
The sampling operation performed four times will be specifically described. In FIG. 10, since the output of P2 and P3 of the data capture signal 1 has been described, a description thereof will be omitted. Referring to FIG. 9, when data capture signal 1 (P3) is output (S9), it is determined whether or not a falling signal has arrived (S7). Referring to FIG. Has not arrived (NO in S7), the data capture signal 1 (P4) is output after 1/2 bit has elapsed (S8, S9). At this time, digital data 1 and 2 (1, 0) are stored in the temporary storage circuit 4.
[0042]
Next, when the data capture signal 1 (P4) is output (S9), it is determined whether or not a falling signal has arrived (S7). With reference to FIG. 10, the falling signal still arrives at this time. (NO in S7), the data capture signal 1 (P5) is output after 1/2 bit has elapsed (S8, S9). Whether or not the falling signal has arrived is determined by the fact that the falling signal has arrived when the digital data 2 changes from 0 to 1 after the digital data 1 changes from 1 to 0. On the other hand, referring to FIG. 10, the digital data 1 changes from 1 to 0 at the time when the data capture signal 1 (P5) is output. Accordingly, digital data 1 and 2 (0, 0) are stored in the primary storage circuit 4.
[0043]
Next, when the data capture signal 1 (P5) is output (S9), it is determined whether or not a falling signal has arrived (S7). Referring to FIG. 10, the falling signals (0 and 1 have arrived) Therefore (YES in S7), after falling signal P6 is output and 1/4 bit width elapses (S10), it is determined whether there is no signal / present signal (S11), and since it is a present signal (present signal in S11), data Capture signal 1 (P7) is output.
[0044]
At this time, digital data 1 and 2 (0, 1) are stored in the primary storage circuit 4. That is, after the digital data 1 and 2 (0, 0) are stored in the primary storage circuit 4, the data stored in the temporary storage circuit 4 before the ½ bit width has elapsed is written to (0, 1). It is replaced.
[0045]
Therefore, (1,0) is written in the secondary storage circuit 5 by the data capture signal 2 (P51) output after the 1/2 bit width has elapsed since the data capture signal 1 (P4) was output. Instead of (0,0), (0,1) is written to the secondary storage circuit 5 by the data capture signal 2 (P52) output after the 1/2 bit width has elapsed since the capture signal 1 (P5) was output. It is. As a result, the data in the first half of the SYNC output from the secondary storage circuit 5 is exactly 1.5 bits of data.
[0046]
Next, the operation after the falling signal arrives will be described with reference to FIG. When the latter half of the SYNC signal is input, the edge detection circuit 2 outputs a falling signal (see P6 in FIG. 10), and the signal is input to the sequencer 11. Then, the sequencer 11 makes a transition from S7 to C in FIG. 9, and after a lapse of 1/4 bit width in S10, the determination of no signal / presence signal in S11 is made. The signal 1 (see P7 in FIG. 10) is output, and “3” is set in the ½ bit counter 12 in S13 (see P15 in FIG. 10), and then transitions to D.
[0047]
When the subsequent signals are input, a loop of D.fwdarw.S14.fwdarw.S15.fwdarw.S16.fwdarw.S17.fwdarw.S18.fwdarw.D is followed, and the data capture signal 1 is generated every 1/2 bit signal width (FIG. 9). (See P7 and P8).
[0048]
The 1 / 2-bit counter counts up in S18 (see P15 to P22 in FIG. 9), and the counter count value is 40, that is, D → S14 → S15 → until the last bit in the word (the second half of the parity bit). A transition of S16 → S17 → S18 → D is performed (see P28 in FIG. 10). In this operation, sampling is performed every 1/2 bit from the detection of the falling edge in S7 to the latter half of the last bit in one word (see P24 to P27 in FIG. 11).
[0049]
In other words, what was initially sampled every 1/2 bit with respect to the rising edge means that sampling is performed with reference to the falling edge. This is an operation considering that the signal width of the first half of the SYNC of the MIL-STD-1553B data bus is different from the subsequent signal width.
[0050]
When the last 0.5 bits in one word are input, the ½ bit counter 12 is changed from 40 to 0 by S18 in FIG. 9 (see P28 and P29 in FIG. 11). Then, the sequencer 11 transitions from S18 → D → S14 → S15. Since the count value is “0” in S16, the “YES” loop in S16 is followed and the process proceeds to S19.
[0051]
In S19, after a delay of a predetermined time has elapsed, the data capture signal 1 is output (S20) (see P30 in FIG. 11). This operation takes into account that the signal width of the latter half of the parity bit is extended. In other words, in the 1-word transfer, since the signal width is extended in the second half of the parity bit, the determination result of no signal / presence signal in S14 becomes a signal even though the next word does not continue (no signal). (Refer to P31 in FIG. 11). Therefore, the data capture signal 1 is delayed by the delay operation of S19, that is, the digital data 1 and 2 are output to the primary storage circuit 4 at the timing when the digital data 1 and 2 become (0, 0) (see P32 in FIG. 11). It acquires state information.
[0052]
In this way, it is possible to avoid sampling the last half of the last bit extending the signal width twice. In multi-word transfer, only the sample of the beginning of the next word (SYNC signal of the next word) is delayed by S20 (see P33 in FIG. 12), but the SYNC signal is 1.5 bits long and level. Therefore, as long as the delay time of S19 is not increased, the next sample is possible (see P34 in FIG. 12). However, the sample timing is delayed only in the first sample of the next word (the sample of P33 in FIG. 12), and the subsequent samples are performed at the previous timing (see P35 to P40 in FIG. 12). ).
[0053]
That is, in the case of multiple word transfer, the transition from the last half of the last bit of one word to the next word is D → S14 → S15 → S16 → S17 → S18 → D → S14 → S15 → S16 → S19 → S20 → S21. → S14 → S15 → S16 → S17 → S18 → D The loop is followed. The sample of the last half of the last word last bit in which the signal width increases follows D → S14 → S15 → S16 → S17 → S18 → D → S14 → A.
[0054]
As described above, the output timing of the data capture signal 1 of the sample timing generation circuit 3 follows the difference in signal width.
[0055]
Next, operations of the primary storage circuit 4 and the secondary storage circuit 5 will be described. The primary storage circuit 4 captures the digital data 1 and 2 at the timing when the data capture signal 1 is input (see P2 in FIG. 10). The secondary storage circuit 5 captures output data from the primary storage circuit 4 at the timing when the data capture signal 2 is input (see P41 in FIG. 10).
[0056]
The data is first taken in by the primary storage circuit 4 at the timing of S5 in FIG. The sample timing generation circuit 3 outputs the first data capture signal 2 after a ½ bit width has elapsed since the first data capture signal 1 is output (see P41 in FIG. 10), and thereafter the ½ bit width. It is output every time (see P42 to P44 in FIG. 10). The secondary storage circuit 5 samples the output data of the primary storage circuit 4 at the timing when the data capture signal 2 is input, and outputs the sampled data to the transmitter 6.
[0057]
By using the data capture signal 1 and the data capture signal 2 delayed by ½ bit width in this way, it is possible to absorb the spread of the signal width and thus shape it into a normal waveform. The transmitter 6 converts and outputs a signal from the secondary storage circuit 5 to a specified voltage of the MIL-STD-1553B data bus.
[0058]
【The invention's effect】
According to the present invention, the first storage means for storing data at a constant cycle starting from the rising edge of the input signal, and the first storage means for storing data at a fixed period starting from the rising edge following the rising edge. And the second storage means for storing data, and the data stored in the second storage means is output in time series, so that it is possible to absorb fluctuations in the signal width of the input signal. . Furthermore, even when the first edge of the input signal is around the original timing, it is possible to absorb the fluctuation of the signal width of the input signal. Furthermore, since it is possible to provide signal conversion means for converting a ternary signal into a binary signal, the present invention can be applied to a double-flow signal such as a MIL-STD1553B bus.
[0059]
According to another aspect of the present invention, the first step of storing data in the first storage unit at a fixed period starting from the rising edge of the input signal, and the constant time starting from the rising edge following the rising edge. And a second step of storing the data stored in the first storage unit in the second storage unit, and the data stored in the second storage unit is output in time series. Has the same effect as.
[0060]
Specifically, the first effect can absorb fluctuations in the signal width of the SYNC bit and parity bit waveform of the MIL-STD-1553B data bus. The reason is as follows. The first 1.5 bits of the SYNC bit and the parity bit having a large signal width variation are sampled in consideration of the variation width, and the other bits are sampled at different timings. This is because the sampled data is temporarily stored in a common storage device, and the sampling data is sampled again at a unified timing, so that the sampling timing shift can be buffered.
[0061]
The second effect is that a transmission line extension function can be realized. The reason is that since the signal waveform is shaped, distortion during transmission can be removed and the signal waveform can be reproduced. Therefore, the transmission path can be extended.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a preferred embodiment of a signal waveform shaping circuit according to the present invention.
FIG. 2 is a schematic diagram showing a signal format of a MIL-STD-1553B data bus.
FIG. 3 is a waveform diagram of one word.
FIG. 4 is a waveform diagram showing the definition of logic levels.
5 is a diagram showing an input waveform and an output waveform of the receiver 1. FIG.
FIG. 6 is a signal waveform diagram showing characteristics of a MIL-STD-1553B data bus.
7 is a configuration diagram of an example of a sample timing generation circuit 3. FIG.
FIG. 8 is a schematic diagram showing a relationship between waveforms of digital data 1 and 2 and a count value.
FIG. 9 is a flowchart showing the operation of the sample timing generation circuit 3;
10 is a timing chart of the sample timing generation circuit 3. FIG.
11 is a timing chart of the sample timing generation circuit 3. FIG.
12 is a timing chart of the sample timing generation circuit 3. FIG.
FIG. 13 is a configuration diagram of a waveform shaping device disclosed in the prior art.
FIG. 14 is a waveform diagram of an example of a biphase code.
[Explanation of symbols]
1 Receiver
2 Edge detection circuit
3 Sample timing generator
4 Primary memory circuit
5 Secondary memory circuit
6 Transmitter
7 Clock signal generator
11 Sequencer
12 1/2 bit counter
13 1/2 bit width delay circuit

Claims (16)

A signal waveform shaping circuit for shaping an input signal that takes three values and takes an intermediate value only before and after the start of data,
Is stored in the first and first storage means for data at a fixed period starting when rising is stored, said first storing means at a predetermined period starting from the time of the first falling subsequent to when the first rising of the input signal And a second storage means for storing the data, wherein the data stored in the second storage means is output in time series. Counting means for counting up each time data is stored in the first storage means, and a timing at which data is stored in the first storage means when the count value of the counting means reaches a preset numerical value. 2. The signal waveform shaping circuit according to claim 1, further comprising delay means for delaying. 3. The signal waveform shaping circuit according to claim 2, wherein when the count value reaches a preset numerical value, the count value is reset next time. 4. The signal waveform shaping circuit according to claim 2, wherein the preset numerical value is a numerical value obtained by adding 1 to a count value of a signal for one word having no phase shift. The second data capture signal for determining the timing for storing data in the second storage means is output with a predetermined time delay from the first data capture signal for determining the timing for storing data in the first storage means. The signal waveform shaping circuit according to claim 1, wherein: 6. The signal waveform shaping circuit according to claim 1, further comprising signal conversion means for converting a ternary signal into a binary signal, wherein the binary signal is stored in the first storage means. . 7. The signal waveform shaping circuit according to claim 1, wherein the input signal is a biphase signal. 8. The signal waveform shaping circuit according to claim 1, wherein the input signal is composed of a signal having a SYNC bit at the head, followed by a data bit, and a parity bit at the end. A signal waveform shaping method for shaping an input signal that takes three values and takes an intermediate value only before data start and after data end,
The first data at a predetermined period starting from the time the rising and first storing in the first storage unit, the first storage unit at a predetermined cycle during the first falling subsequent to when the first rising as a starting point of the input signal And a second step of storing the data stored in the second storage unit, wherein the data stored in the second storage unit is output in time series. A third step of counting up each time data is stored in the first storage step, and when the count value in the third step reaches a preset numerical value, the data in the first step 10. The signal waveform shaping method according to claim 9, further comprising delay means for delaying a timing stored in one storage unit. 11. The signal waveform shaping method according to claim 10, wherein when the count value reaches a preset numerical value, the count value is reset next time. 12. The signal waveform shaping method according to claim 10, wherein the preset numerical value is a numerical value obtained by adding 1 to a count value of a signal for one word having no phase shift. The second data capture signal for determining the timing for storing data in the second storage unit is output after a predetermined time delay from the first data capture signal for determining the timing for storing data in the first storage unit. The signal waveform shaping method according to any one of claims 9 to 12. The signal waveform shaping method according to claim 9, further comprising a fourth step of converting a ternary signal into a binary signal, wherein the binary signal is stored in the first storage unit. . 15. The signal waveform shaping method according to claim 9, wherein the input signal is a biphase signal. 16. The signal waveform shaping method according to claim 9, wherein the input signal is composed of a signal having a SYNC bit at the beginning, followed by a data bit, and a parity bit at the end.

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