JP3655775B2 - ATM cell output control system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an ATM (Asynchronous Transfer Mode) cell output control system, and more particularly to an ATM cell output control system in an ATM communication system.
[0002]
[Prior art]
When communicating with a partner communication device via a transmission line, a system using an ATM method as a communication method has become widespread. The present invention relates to an ATM cell output control system for reading out ATM cells from an ATM switch unit in such an ATM communication (exchange) apparatus and outputting the ATM cells to a plurality of transmission paths in such an ATM communication (exchange) apparatus.
[0003]
FIG. 5 shows a block diagram of an ATM cell output control system in an ATM communication apparatus to which the present invention relates. 5, input units 31 to 3n to which inputs # 1 to # 2n from the transmission line are input, ATM switch (exchange) unit 1, and output units 21 to 2n to output outputs # 1 to # 2n to the transmission line. Is provided.
[0004]
Input signals # 1 to # 2n from the transmission line enter the input units 31 to 3n, and terminate the frame bits included in each transmission line. Further, the ATM cells in the input signals # 1 to # 2n are extracted, and the ATM cells of the transmission line inputs # 2n-1 and # 2n are multiplexed. This multiplexing is generally necessary because the number of physical ports at the input of the ATM switch unit 1 is finite, and FIG. 5 shows a case of two multiplexing as an example.
[0005]
The ATM switch unit 1 has functions such as selection (routing) of an output route (transmission route). The routing determines the physical port number of the output by referring to the preset setting information according to the address information of the VPI (virtual path identifier) and VCI (virtual channel identifier) bytes in the ATM cell, The ATM cell is output to the port number.
[0006]
FIG. 6 shows the cell structure of the ATM cell. That is, an ATM cell is a fixed-length packet consisting of 53 bytes, the first 5 bytes are a header part containing address information such as VPI, VCI, and the rear 48 bytes contain information to be transmitted. Is the payload part. Therefore, one cell consists of 53 bytes × 8 bits = 424 bits. As a result, the setting information requires routing information for all VPIs and VCIs arriving from transmission line inputs # 1 to # 2n.
[0007]
Further, when routing occurs simultaneously from a plurality of input ports toward one output port, there arises a problem that ATM cells collide at the output port. In order to avoid this problem, ATM cells input from the input port are temporarily stored in a cell memory in the ATM switch 1 and output after controlling the output order. The output units 21 to 2n receive the ATM cell from the ATM switch unit 1, detect the VPI and VCI in the ATM cell, determine which transmission path # 1 to # 2n should be output, and then output the ATM cell. Sort cells. Further, a frame bit or the like specifying each of the transmission lines # 1 to # 2n is added to the distributed ATM cells, and the ATM cells are output to the transmission lines # 1 to # 2n.
[0008]
FIG. 7 shows a block diagram of a conventional cell output control unit. In FIG. 7, the conventional ATM communication apparatus includes an ATM switch unit 1 and an output unit 2 that outputs (d, e) to a transmission line. The output unit 2 includes a selection unit 13 for distributing ATM cells, transmission memory units 41 and 42 for temporarily storing ATM cells in the order of transmission, and transmission units 14 and 15 for outputting (d, e) ATM cells to a transmission path. It is comprised by.
[0009]
In the example shown in FIG. 7, since there are two transmission path outputs (d, e), the transmission memory units 41 and 42 and the transmission units 14 and 15 each have two circuits. The transmission units 14 and 15 prompt the transmission memory units 41 and 42 to output ATM cells via the control line (o). Furthermore, the transmission memory units 41 and 42 prompt the selection unit 13 for ATM cells via the control line p. Furthermore, the selection unit 13 prompts the ATM switch unit 1 to output ATM cells via the control line q.
[0010]
The ATM switch unit 1 has a routing function as described above, and outputs an ATM cell to the selection unit 13. The selection unit 13 detects the VPI and VCI in the ATM cell, determines whether the arrived ATM cell should be output to the transmission line output d or e based on preset setting information, and distributes the ATM cell. .
[0011]
The transmission memory units 41 and 42 are composed of first-in first-out (FIFO) memory elements, and the ATM cells of the selection unit 13 output 1 are sequentially written, and the ATM cells are output in accordance with the written order. It is memory. The necessity of this memory will be described later.
[0012]
The transmitters 14 and 15 input the ATM cell and output it d and e to the transmission line, but the so-called ATM layer such as insertion of empty cells (dummy cells when there is no ATM cell to be sent), cell scrambling, etc. Terminate. Further, since the transmission line outputs d and e are serial signals, they are converted from 8-bit byte signals to 1-bit serial signals (parallel / serial).
[0013]
Thereafter, a frame synchronization signal or the like according to the transmission path interface format is added and output. The transmission line interface has various interfaces in its speed system, but its output speed is strictly defined. Therefore, the transmission rate of the ATM cell k from the ATM switch unit 1 depends on this transmission rate. That is, the ATM cell transfer rate at the input m of the transmitters 14 and 15 cannot transfer the ATM cell at a rate higher than the rate (hereinafter referred to as the logical rate) excluding the frame synchronization signal from the transmission path interface.
[0014]
Cell request signals o, p, and q for prompting each preceding block to output ATM cells follow the logic speed. These cell request signals o, p, q are provided for each of the transmission units 14, 15. That is, since various transmission path interfaces exist as described above, the logical speed is not uniquely determined. Since the cell request signals o and p are simply signals for requesting cells, the cell request signal q is a binary signal. However, since the cell request signal q is multiplexed in the selector 13, the information on the transmission path outputs d and e is used. It has a cell request signal.
[0015]
By receiving the cell request signal q, the ATM switch unit 1 takes out an output cell to the transmission path from the cell memory unit in the ATM switch unit 1, and outputs the ATM cell to the signal line k. Through the series of operations described above, the transfer rate of the ATM cell transmitted from the ATM switch unit 1 coincides with the total value of the logical rates required by the transmission line outputs d and e.
[0016]
Next, multiplexing of the control signal p in the selection unit 13 will be described. When the control signals p for the transmission line outputs d and e are multiplexed, if the generation of cell requests for each control signal p is different in time, multiplexing is not a problem, but each control signal p is a cell in the same time zone. When making a request, it is necessary to select these request signals p one by one and output them as control signals q. This is because the transfer time of one ATM cell at the output k of the ATM switch unit 1 and the one cycle time of the cell request signal q need to match.
[0017]
Further, since the control signal p is a signal generated from the transmission line output signals d and e that cannot manage the phase of the ATM cell in terms of time, the generation of a cell request cannot be predicted in terms of time. Therefore, the multiplexing of the control signal p in the selection unit 13 is required to wait for the other when a cell request occurs simultaneously. Waiting for the multiplexing of the control signal p delays the cell transmission time of the ATM switch 1 output k as it is. This is output as a fluctuation of the ATM cell.
[0018]
On the other hand, ATM cells output d and e from the transmission units 14 and 15 to the transmission path are sent out at a constant speed, so that the ATM cells of the transmission units 14 and 15 input m are isochronous. The transmission memory units 41 and 42 are installed to absorb the above-described ATM cell fluctuation, and the required memory amount is the maximum fluctuation amount of the ATM cell of the input l. Further, the cell request signal p is configured to generate a cell request when the number of staying cells in the transmission memory units 41 and 42 falls below a certain value. This is to prevent the staying cells in the transmission memories 41 and 42 from becoming empty due to the fluctuation of the ATM cell at the input 1 of the transmission memory units 41 and 42.
[0019]
[Problems to be solved by the invention]
In the conventional ATM cell output control system shown in FIG. 7 described above, there is a problem that an ATM cell signal and a cell request signal indicating the logical speed of the output ATM cell are required in the opposite direction to the ATM cell signal. Furthermore, there is a problem that a transmission memory unit is required to absorb the cell fluctuation of the ATM switch unit due to the queuing that occurs when the cell request signal is multiplexed.
[0020]
An object of the present invention is to provide an ATM cell output control method that simplifies a complicated output method in an ATM cell output operation.
[0021]
[Means for Solving the Problems]
According to the present invention, there is provided an ATM cell output control system that reads ATM cells from a common memory of an ATM switch unit and distributes and outputs the ATM cells read to a plurality of transmission lines, and reads the ATM cells from the switch unit. An ATM cell output control system characterized in that rate setting means for setting a rate reading rate for output is provided in common for the plurality of transmission lines.
[0022]
The rate setting means calculates the ATM cell logical speed of each transmission path based on the rate setting information of each transmission path, and satisfies the ATM cell logical speed for each of the transmission paths. A cell read request signal, and a counter that divides the clock signal by a frequency division ratio set in advance based on the corresponding rate setting information provided corresponding to each of the transmission paths. Features. Further, the rate setting means has means for generating a cell read request signal in response to a rising (falling) timing of each output of the counter.
[0023]
The operation of the present invention is as follows. A rate setting unit for reading (ATM) cells from the switch unit is provided in common for a plurality of transmission lines, and this rate setting unit is operated by a clock and rate setting information. As a result, it is possible to eliminate the cell request signal that was previously in the output unit.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of an ATM cell output control system according to the present invention, and the same parts as those in FIG. 7 are denoted by the same reference numerals. In addition, the description which overlaps with the part of FIG. 7 shall be omitted. In FIG. 1, an ATM switch unit 1 and an output unit 2 for sending (d, e) ATM cells to a plurality of transmission paths are provided. The ATM switch unit 1 includes a switch unit 11 for routing ATM cells and a rate setting unit 12 for generating a cell request signal f. The output unit 2 includes a selection unit 13 that distributes ATM cells and transmission units 14 and 15 that generate transmission line outputs d and e, respectively.
[0025]
The switch unit 11 has basically the same function as the ATM switch unit 1 shown in FIG. 7, and the transmission units 14 and 15 have the same functions as those shown in FIG. 7 except that there is no cell request signal o. Yes.
[0026]
The operation of the embodiment of the present invention will be described. In FIG. 1, the switch unit 11 of the ATM switch unit 1 outputs (a) a cell to the selection unit 13 of the output unit 2. The selection unit 13 detects the VPI and VCI in the cell, determines to which transmission path an incoming cell should be output (d, e) based on preset setting information, and transmits the cell. Assigned to parts 14 and 15.
[0027]
Transmitters 14 and 15 receive cells as inputs (b and c) and output (d and e) to the transmission line, but insert empty cells (dummy cells when there are no cell inputs b and c), cell scrambling, etc. The so-called ATM layer is terminated. Since the normal transmission path is serial (signal) transmission, the 8-bit byte parallel signal is converted into a 1-bit serial signal. Thereafter, a frame synchronization signal or the like according to the transmission path interface format is added and output.
[0028]
Here, the logical speeds of the cells at the inputs b and c of the transmission units 14 and 15 will be described. Since the transmission path interface of the transmission units 14 and 15 is determined by the device or the communication system to which the device belongs, transmission is performed. The road interface speed is a constant value. Therefore, the logical speed is not a value that changes from moment to moment, but a fixed value.
[0029]
The present invention pays attention to this point, and the rate setting unit 12 generates a cell request signal f for requesting a cell from the switch unit 11. The rate setting unit 12 is effective for a plurality of transmission line outputs d and e (or # 1 to # 2n; see FIG. 5), calculates the logical speed of a plurality of cells as timing information, and then transmits these signals. The cell request signal f is created by multiplexing.
[0030]
In other words, a plurality of logical speeds are created in a unified manner, and a cell request signal f is created, so that waiting occurs when the cell request signal p is multiplexed in the selection unit 13 in FIG. The fluctuation of the cell of 1 output k does not occur. If the fluctuation of the cell does not occur, the transmission memory units 41 and 42 in FIG. 7 are unnecessary, and the output unit 2 can be simplified as shown in the figure.
[0031]
FIG. 2 is a block diagram showing the configuration of the rate setting unit 12. In FIG. 2, the rate setting unit 12 includes counters 16 and 17 that count a clock h based on setting information g, and a determination unit 18 that detects outputs i and j of the counters 16 and 17. The counters 16 and 17 are respectively installed corresponding to the transmission units 14 and 15 shown in FIG. 1. In FIG. 1, since the transmission units 14 and 15 are two circuits, the counters 16 and 17 shown in FIG. Although there are two circuits, it is obvious that a counter corresponding to that is provided in the case of three or more. Therefore, in the apparatus shown in FIG. 5, 2n counters are required corresponding to the transmission line outputs # 1 to # 2n.
[0032]
These counters 16 and 17 calculate the logical speeds of the cells of the inputs b and c of the transmission units 14 and 15 in FIG. 1 as timing information. Since the logical speed may be a fixed value as described above, the logical speeds i and j are output by dividing the clock signal h by the counters 16 and 17 by r. The setting information g sets the frequency dividing ratio r in the counters 16 and 17, and r1 is set in the counter 16 and r2 is set in the counter 17, respectively.
[0033]
The determination unit 18 generates the cell request signal f to the switch unit 11 by detecting the outputs i and j of the counters 16 and 17. The operation timing of the rate setting unit 12 is shown in FIG. In FIG. 3, each signal is the same as the signal shown in FIG. However, r1 is set to “12” and r2 is set to “8”, and the cell b of the transmission unit 14 is transmitted in the period A, and the cell c of the transmission unit 15 is transmitted in the period B, respectively.
[0034]
That is, in the example shown in FIG. 3, the logical speed in the direction of the transmission line output d is the clock signal h × 1/12, and the logical speed in the direction of the transmission line output e is the clock signal h × 1/8. The outputs i and j of the counters 16 and 17 are output as shown by the clock signal h and the frequency dividing numbers r1 and r2. The determiner 18 detects the rising timing (or may be the falling timing) of the outputs i and j of the counters 16 and 17 and outputs a cell request signal f. The switch unit 11 takes out the output cells b and c to the transmission line from the cell memory in the switch unit 11 in response to the cell request signal f, and outputs the cells at timings A and B as shown.
[0035]
The rate setting unit 12 according to the present invention includes a clock signal h and setting information g, and the counters 16 and 17 may have any internal configuration. An example is shown in FIG. 4. For example, the counter 16 is operated by the clock signal s and the counter 17 is operated by the clock signal t. Accordingly, the counters 16 and 17 count at the rising edge so that the outputs i and j of the counters 16 and 17 do not rise at the same time.
[0036]
Further, if one cycle time of the clock signals s and t is equal to the transfer time of one cell of the output a of the switch unit 11 shown in FIG. , J do not change at the same time, and it is possible to avoid waiting for multiplexing.
[0037]
【The invention's effect】
As described above, the present invention has an advantage that a rate setting unit is provided for each output unit in a one-to-one manner and is concentrated in the ATM switch unit for a plurality of transmission line outputs. is there. In addition, the hardware can be relatively simplified because it is only necessary to be provided in one central location. Further, as in the conventional output control unit, it is possible to avoid the problem of the asynchronous timing of the cell request due to the individual generation of the cell request signal from the transmission unit and the waiting problem when the cell request signal is multiplexed due to this. effective. Therefore, the present invention has an effect that the hardware configuration can be simplified by newly installing a rate setting unit and causing the rate setting unit to output cells from within the ATM switch unit.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a detailed block diagram of a rate setting unit.
FIG. 3 is an operation timing chart of the rate setting unit.
FIG. 4 is a timing chart showing an example of clock selection for a counter.
FIG. 5 is a block diagram of a related ATM communication system of the present invention.
FIG. 6 is a diagram illustrating the configuration of an (ATM) cell.
FIG. 7 is a block diagram of an example of a conventional ATM communication apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ATM switch part 2 Output part 11 Switch part 12 Rate setting part 13 Selection part 14,15 Transmission part

Claims (4)

An ATM cell output control system for reading ATM cells from a common memory of an ATM switch unit and distributing and outputting the ATM cells read to a plurality of transmission lines, wherein a rate read rate for reading the ATM cells from the switch unit An ATM cell output control system, characterized in that rate setting means for setting the number is provided in common for the plurality of transmission lines. The rate setting means calculates the logical speed of the ATM cell of each transmission path based on the rate setting information of each transmission path, and reads the cells so as to satisfy the logical speed of the ATM cell for each of the transmission paths. 2. The ATM cell output control system according to claim 1, wherein the request signal is generated. 3. The rate setting means includes a counter provided corresponding to each of the transmission lines and configured to divide a clock signal by a frequency division ratio set in advance based on corresponding rate setting information. ATM cell output control system. 4. The ATM cell output control system according to claim 3, wherein said rate setting means includes means for generating a cell read request signal in response to a rising (falling) timing of each output of said counter.

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