JP3661249B2 - Multiprocessor system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multiprocessor system configured using a plurality of processors to achieve high performance.
[0002]
[Prior art]
A method of realizing a shared memory multiprocessor system by combining a plurality of processor units, memory units, and input / output units using a single bus is well known.
[0003]
However, when connecting using a single bus, there is only one path for transferring data between connected units, so if you increase the number of processors to improve system performance, the bus becomes a bottleneck. Become.
[0004]
In order to solve this problem, a method using a bus for address transfer and using a crossbar switch for data transfer is described by Nicholson in "COMC 95 Proceedings of 1995" pages 102-109, "RISC system / 6000 SMP system" (James O.). Nicholson, “The RISC System / 6000 SMP System,” COMPCON 95 Proceedings, March 1995, pp. 102-109).
[0005]
[Problems to be solved by the invention]
However, although the above-described conventional method also eliminates the bus neck in terms of throughput, the number of processors cannot be increased so much at high frequencies due to electrical restrictions in transmitting signals.
[0006]
In order to solve this, the address can also be solved by connecting each unit and the crossbar switch in a one-to-one manner through the crossbar switch.
[0007]
At this time, in order to correctly operate the software operating on the bus connection, it is necessary to maintain the data coherency between the cache memory and the main memory even with the connection using the crossbar switch. Furthermore, in order to connect a processor made on the premise of bus connection via a crossbar switch, it is necessary to realize a general address snoop method on the crossbar switch as a method of maintaining data coherency by the bus method. .
[0008]
This address snoop is a method for maintaining the data coherency between the cache memory and the main memory, and there is no need to transfer the address to a memory unit having no data to be transferred or an input / output unit having no cache memory. For this reason, the transfer of the address necessary for maintaining the data coherency need only be performed to the unit that needs to participate in the address snoop, and means for performing the multicast that is the one-to-many data transfer. An efficient address snoop method can be realized by providing the system connection unit. A first problem of the present invention is to eliminate the bus neck by connecting processors that are made on the assumption that they are connected by a bus through a crossbar switch, and to increase the number of connectable processors. The purpose is to improve the performance of the processor system.
[0009]
A second object of the present invention is to enable operation in a system connected via a crossbar switch without changing software operating on a bus.
[0010]
The problem to be solved by the present invention is to achieve the above two problems at the same time, and the present invention also aims to solve the following two problems.
[0011]
A third object of the present invention is to provide an efficient address snoop system in a multiprocessor system connected by a crossbar switch.
[0012]
A fourth object of the present invention is to provide a multicast system that allows any unit of a processor unit, a memory unit, and an input / output unit to be connected to a port of a crossbar switch, thereby enabling a flexible system configuration.
[0013]
[Means for Solving the Problems]
The first object of the present invention is achieved by eliminating the conventional address bus introduced by the above-mentioned Nicholson, connecting the address to each unit and the crossbar switch on a one-to-one basis. .
[0014]
The second problem of the present invention is to provide a means for broadcasting addresses to all units connected to the crossbar switch in order to enable the address snoop method even in the crossbar switch, in order to maintain data coherency. In the case of the necessary address transfer, this is accomplished by controlling the system connection to transfer the address to all units.
[0015]
The third object of the present invention is to provide a means for multicasting the transfer of addresses necessary for maintaining data coherency only to units that need to participate in address snooping in the system connection unit, thereby maintaining data coherency. In the case of address forwarding necessary to do this, it is accomplished by controlling the system connection to forward addresses only to units that need to participate in address snoop.
[0016]
A fourth problem of the present invention is to provide means for holding information indicating whether or not a unit connected to each port is a multicast target unit in the crossbar switch, and determine a transfer destination port based on this information. This is achieved by providing a means and setting a multicast destination in a means for determining a transfer destination port based on information indicating whether or not the unit is a multicast target unit, and then performing the multicast.
[0017]
By connecting each unit using a crossbar switch, multiple data transfers can be executed at the same time if the transfer destination ports are different. This prevents a decrease in performance due to bus contention by increasing the number of processors. Can do.
[0018]
Also, by connecting each unit and the crossbar switch on a one-to-one basis, it is possible to obtain better electrical characteristics than the bus, and as a result, the number of connectable processors can be increased.
And become possible.
[0019]
By broadcasting the transfer of addresses necessary for maintaining data coherency, the address snooping function of an existing processor can be used, and a method for maintaining low-cost and efficient data coherency can be realized.
[0020]
Eliminate unnecessary data transfer and improve effective data transfer throughput by transferring coherent transaction addresses only to units connected to each port that need to participate in address snoop Can be made.
[0021]
Also, by holding information indicating whether or not the unit is a multicast target unit corresponding to the port, it becomes possible to connect an arbitrary unit to an arbitrary port, and a flexible system configuration is possible.
[0022]
The multicast method of the present invention has been described by taking address snoop as an example, but it can be generally used when data is transferred to a plurality of ports.
[0023]
For example, if you want to transfer a reset command to all I / O devices, a means is provided to hold whether the I / O unit is connected to the port as information indicating whether it is a multicast target or not. Just do it.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, it demonstrates in detail using the Example of this invention.
[0025]
FIG. 2 shows a first embodiment of the present invention in which three processor units 20, 30, 40, two memory units 50, 60 and one input / output unit 70 are connected by a system connection unit 100 having six ports. .
[0026]
The input / output unit 70 is connected to input / output devices such as a disk device 75, a display (not shown), and a keyboard (not shown).
[0027]
Since each unit has the same function except for the interface unit between the corresponding unit in the normal bus-connected system and the system connection unit, in this embodiment, the difference between the bus-connected system and this embodiment is as follows. The details will be described in detail, and only the parts necessary for the explanation will be explained for the same points.
[0028]
The processor unit 30 is connected to the system connection unit 100 via the port 4 and includes a unit identification register idr31, a connection information generation circuit 33, and a transfer destination identification register dr32, which are features of the present invention. Details of these circuits will be described later.
[0029]
Similarly, other units are also connected to the system connection unit 100 via ports, and each has a unit identification register idr, a connection information generation circuit, and a transfer destination identification register dr.
[0030]
The system connection unit 100 includes six switch control circuits 110 to 160 and 36 switches sw1-1 to sw6-6 that connect input ports and output ports.
[0031]
The switch control circuit 140 is provided for the input of the port 4, controls the opening and closing of the six switches sw4-1 to sw4-6, and the input bus 14 of the port 4 is connected to the output of the port 1 from the output bus 21 of the port 1, respectively. Connect to bus 26.
[0032]
Similarly, other switch control circuits are also provided corresponding to the input of each port. If i is a natural number from 1 to 6, the switch control circuit of port i controls the opening and closing of the switches swi-1 to swi-6, The input bus of port i is connected to the output bus of any port.
[0033]
In the case of unicast, any input port is connected to the input port by closing one of the switches, and in the case of broadcast, the input port is connected to all the output ports simultaneously by closing all the switches. Control.
[0034]
In this switch control, the switch control circuit arbitrates the right to connect the output ports so that a plurality of input ports are not connected to the same output port. This output port connection right arbitration circuit is the same as the bus right arbitration circuit of a normal bus-connected system, and its description is omitted in this embodiment.
[0035]
FIG. 3 shows an example of a unit identification method based on the contents of the register idr for identifying a unit which is a feature of the present invention of each unit. It is assumed that each unit holds the information shown in FIG. 3 in the unit identification register idr of each unit.
[0036]
FIG. 4 shows the type of data transfer trtyp generated by each unit of this embodiment. In this embodiment, the data transfer type trtyp is (1) non-coherent block read request, (2) non-coherent block read response, (3) non-coherent block write request, (4) non-coherent word read request, and (5) non-coherent. There are eight types: coherent word read response, (6) non-coherent word write request, (7) coherent shared block read request, and (8) coherent exclusive block read request.
[0037]
FIG. 5 shows address space allocation in the system of this embodiment. In this embodiment, an area from address 0 to less than address A is provided in the main memory provided in the memory unit 0, an area from address A to less than address B is provided in the main memory provided in the memory unit 1, and an area greater than address B is provided. Allocated as I / O space for memory mapped control registers and the like.
[0038]
In this embodiment, the address of the I / O space to which the control register of each unit is mapped is determined to correspond to the port, and the area from the B address to the C address is the unit of the port 1, the area from the C address to the D address Is port 2 unit, the area from D address to less than E address is port 3 unit, the area from E address to less than F address is port 4 unit, the area from F address to less than G address is port 5 unit, G address The area below the MAX address is assigned to the port 6 unit.
[0039]
FIG. 6 shows the value of the transfer destination identification register dr in this embodiment. In this embodiment, in order to identify the memory unit of which port the memory area of the address space is provided, two port numbers can be held as the transfer destination identification register dr.
[0040]
The value of the transfer destination identification register dr is set based on the information of the unit identification register idr, which is a feature of the present invention. This operation will be described in detail later.
[0041]
The data transfer type trtyp and the address space allocation method are the same as the data transfer type and address space allocation method used in the bus-connected system, and are not unique to the present invention.
[0042]
In the present invention, the type of data transfer, the address of the data to be transferred, and the transfer destination identification register dr that is a feature of the present invention are used, and the connection information generation circuit that is a feature of the present invention of each unit determines the transfer destination. A data transfer request is issued to the system connection unit together with the five types of control information scctl shown in FIG.
[0043]
Next, the data transfer type trtyp requested from each unit of this embodiment will be described.
[0044]
In a multiprocessor system, when data is read out, it is necessary to read out the latest data that should originally exist in the main memory at the time of reading, and in order to check whether another processor unit holds the latest data. Reading is performed by a coherent shared block read request or a coherent exclusive block read request.
[0045]
When writing, in order to prevent other processor units from holding old data, the data is read once by a coherent exclusive read request.
[0046]
When a read request is made, it is necessary to transmit the address of the data to another processor unit and check the coherency. However, when the read data is transferred, the coherency check is not necessary, and the read response is a non-coherent block. A read response or a non-coherent word read response is used.
[0047]
When the processor unit rewrites certain data and stores it in the cache memory, when the cache memory is replaced or when a coherent read request for the data from another processor unit is detected, the rewritten data must be transferred. At this time, data is transferred by a non-coherent block write request or a non-coherent block read response, respectively.
[0048]
Not all data is held in the cache memory. For example, when a non-cache area is determined, the processor unit reads data with a non-coherent block read request. In addition, since data (word data) that is not read / written in units of blocks like the I / O register is not cached, the processor unit uses a non-coherent word read request or a non-coherent word write request.
[0049]
The data transfer required from each unit differs in the cycle required for the transfer depending on the type trtyp. The number of cycles required for transfer is necessary as control information for the system connection unit. For the sake of explanation, in this embodiment, the read request is one cycle for transferring an address, the block write request is five cycles, the block read response is four cycles, It is assumed that the write request is transferred in 2 cycles and the word read response is transferred in 1 cycle.
[0050]
FIG. 7 shows control information scctl to the system connection unit generated by the connection information generation circuit from the data transfer type trtyp and the address of the transferred data. Since the data transfer type trtyp itself is sent as data to the transfer destination unit, the control information scctl to the system connection unit is information indicating whether it is unicast or broadcast, the number of cycles required for transfer, the port number of the transfer source and the transfer Only the previous port number is required.
[0051]
Based on the data transfer type trtyp, the connection information generation circuit generates information as to whether it is unicast or broadcast and the number of cycles required for transfer as follows. If it is a non-coherent block read request, one cycle of unicast.
[0052]
4 cycles of unicast for non-coherent block read response.
[0053]
5 cycles of unicast for non-coherent block write requests.
[0054]
One cycle of unicast for non-coherent word read request.
[0055]
1 cycle unicast for non-coherent word read response.
[0056]
If it is a non-coherent word write request, two cycles of unicast.
[0057]
1 cycle broadcast if it is a coherent shared block read request or a coherent exclusive block read request.
[0058]
The connection information generation circuit embeds the port number connected to itself as the transfer source port number in the src field of the control information scctl.
[0059]
The connection information generation circuit generates a transfer destination port number based on the data transfer type trtyp, the address of the data, and the transfer destination identification register dr, and embeds it in the dest field of the control information scctl.
[0060]
When the requested data transfer is a response to the read request, the port number of the request source included in the src field of the control information scctl issued to the system connection unit at the time of the read request is embedded in the dest field.
[0061]
If the requested data transfer is a write request or a read request, regardless of whether it is unicast or broadcast, if the address is in the memory space, as shown in FIG. 6, if it is an area from address 0 to address A If 1 is the value of dr0, and if the area is greater than or equal to the A address and less than the B address, then the dr1 value of 4 is embedded in the dest field as the transfer destination port number. If the address is in the I / O space, as shown in FIG. 5, it is 1 if it is an area of B address or more and less than C address, 2 if it is an area of C address or more and less than D address, and D address or more and less than E address. 3 for an area of E, 4 for an area of E or more and less than F, 5 for an area of F or more and less than G, and 6 for an area of G or more and less than MAX. Embed in the dest field as a number.
[0062]
As is clear from the above description, the port number of the transfer destination is determined before setting the value in the transfer destination identification register dr, and data transfer can be performed via the system connection unit. It is only unicast for a fixed I / O space.
[0063]
For this reason, in order to operate the software operating in the bus-connected system on the multiprocessor system of the present invention without changing, the unicast transfer to the I / O space is performed in the transfer destination identification register dr. There is a procedure for setting a value correctly, and after setting a value correctly in the transfer destination identification register dr, it is necessary to use unicast or broadcast transfer for the memory space. Next, this procedure will be described.
[0064]
In this embodiment, the unit identification register idr and the transfer destination identification register dr possessed by each unit are I / O registers mapped to the I / O space of the connected port. The offset address in the space is determined in common.
[0065]
Each processor unit has a ROM that holds a boot program executed immediately after reset, and the processor immediately after reset initializes the cache memory in the processor unit itself according to the boot program. At this initialization stage, no data transfer request is issued to the system connection unit.
[0066]
In the present embodiment, it is assumed that only one main processor unit is selected from a plurality of processor units in the initialization process. For example, a part of the boot program is made different from the boot program of other processor units only for the processor unit that is the main processor unit. Alternatively, if a signal indicating whether or not the processor unit is corresponding to the port is provided, it is easy to provide a signal indicating whether or not the processor unit has the smallest port number from the system connection unit 100.
[0067]
In addition, the system connection unit 100 immediately after the reset is waiting for a data transfer request from each port and is in a state of doing nothing.
[0068]
If the processor unit that has completed initialization in the processor unit is not the main processor unit, it enters a state of waiting for an interrupt from the main processor unit. The main processor unit that has completed initialization in the processor unit reads the unit identification register idr of the unit connected to each port in order of the port number by unicast to the I / O space, and to which port the memory unit is connected Recognize
[0069]
Thereafter, the port number to which the memory unit is connected is set in the transfer destination identification register dr of each unit by unicast to the I / O space.
[0070]
According to the above procedure, a value can be correctly set in the transfer destination identification register dr using only unicast transfer to the I / O space.
[0071]
In the above embodiment, the I / O space is allocated to the address space corresponding to the port. For this reason, a method of setting a value in the transfer destination identification register dr by unicast with respect to the I / O space is shown. However, in the same way as in a bus-connected system, each unit has a mechanism for discarding whether to access the I / O register of the unit by an address, so that I / O space can be replaced with unicast. It is also possible to set a value in the transfer destination identification register dr using only the broadcast for the / O space.
[0072]
In the above embodiment, only one type of memory unit is assumed to simplify the description. For this reason, based on the fixed address A determined by the memory capacity of one memory unit, the memory space is also determined to be an area below address A and an area after address A.
[0073]
Obviously, when memory units having different memory capacities may be connected, the following two means may be provided.
[0074]
(1) The transfer destination identification register dr stores not only the port number but also the minimum address and the maximum address of the address area to which the memory unit is allocated.
[0075]
(2) The connection information generation circuit compares the address of the data to be transferred with the minimum address and the maximum address, and if it is in the address area, the port number is embedded in the dest field.
[0076]
In the above embodiment, since the transfer destination identification register dr can hold information corresponding to only two ports, a maximum of two memory units can be connected. Obviously, in order to increase the number of connectable memory units, the transfer destination identification register dr need only hold information corresponding to the number of ports.
[0077]
In the above embodiment, a fixed address is defined for each port in the I / O space. However, in the above embodiment, only the unit identification register idr and the transfer destination identification register dr need to be fixed in correspondence with the port. These registers are assigned to fixed addresses, and other I / O registers are Similarly to the memory space, it is possible to have means having the same function as the transfer destination identification register dr, which holds the minimum address, the maximum address, and the port number of the area of the I / O space.
[0078]
Next, the second embodiment will be described with reference to FIG. 1, focusing on the differences from the first embodiment of FIG.
[0079]
The first embodiment shows an example in which broadcast is used as a method for realizing address snoop. The second embodiment is an example in which a coherent read transaction is transferred only to a unit that needs to participate in address snoop using multicast.
[0080]
In the second embodiment, the system connection unit 100 has two multicast registers, mcrA180 and mcrB190, which are one of the features of the present invention, and the switch control circuits 110 to 160 switch the switch by referring to the multicast register mcr. The point which produces | generates the signal which controls is different from a 1st Example.
[0081]
The multicast register mcr is a register that is set based on the information of the unit identification register idr, like the transfer destination identification register dr of the first embodiment, and is 1 if the multicast target is connected to the port. Otherwise it holds a value of 0.
[0082]
In FIG. 8, port 3, port 4 and port 6 to which the processor unit is connected as a multicast target are selected to realize address snoop, and port 1 to which the input / output unit 70 is connected as a multicast target is selected in the multicast register mcrA180. An example is shown in which a value is selected and set in the multicast register mcrB190.
[0083]
FIG. 9 shows a circuit of the switch swi-j of the system connection unit 100 of the second embodiment. In the first embodiment, the switch swi-j is controlled only by the signal on-ij, but in FIG. 9, when the mcA-i or mcB-i is 1, the signal mcrA-j from the multicast register mcrA, respectively. Whether or not to connect is determined by the value of the signal mcrB-j from mcrB.
[0084]
Accordingly, when address snooping is performed, by setting mc0-i to 1, a coherent read request can be issued simultaneously to the three processor units and the memory unit indicated by dest.
[0085]
In the second embodiment, as shown in FIG. 10, two multicasts are added corresponding to the multicast registers mcrA and mcrB as types of control information scctl to the system connection unit, and a coherent shared block read request or a coherent exclusive block read If the request is a request, multicast A is used instead of the broadcast in the first embodiment.
[0086]
It is obvious that the multicast register mcr can be set only by unicast transfer to the I / O space based on the information of the unit identification register idr in the same procedure as the transfer destination identification register dr of the first embodiment. Use forwarding.
[0087]
The multicast register mcr may be set immediately before a multicast transfer request using the register is issued. For this reason, the multicast transfer destination can be changed not only by setting a fixed value in the initial setting but also by rewriting the contents of the multicast register mcr by software.
[0088]
In the above embodiment, the multicast register mcr is provided in the system connection unit 100. However, the multicast register mcr may be provided in each unit, and the contents thereof may be included in the control information scctl for the system connection unit 100.
[0089]
In the above embodiment, one bit of the multicast register mcr is associated with each port. However, the ports of the system connection unit 100 are divided into, for example, three groups of ports 1, 2, 3, 4, 5, and 6. It is also possible to connect only units of the same type and associate the bits of the multicast register mcr with the group correspondence. This reduces the increase in hardware having the multicast register mcr.
You can.
[0090]
【The invention's effect】
Multiple processors can be connected.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a table showing a unit identification method.
FIG. 4 is a table showing types of data transfer.
FIG. 5 is a table showing address assignment.
FIG. 6 is a table showing a transfer destination identification register.
FIG. 7 is a table showing control information.
FIG. 8 is a table showing registers.
FIG. 9 is a circuit diagram of a switch.
FIG. 10 is a table showing connection unit control information.

Claims (8)

A multiprocessor system comprising a processor unit having at least one processor, a memory unit having a part of a main memory, an input / output unit for connecting an input / output device, and a system connection, the system connection being determined by a port number A plurality of ports are identified, and any one of the processor unit, the memory unit, and the input / output unit can be connected to the one port, and the processor unit, the memory unit, and the input / output unit are connected to the one port. It is a multiprocessor system that constitutes a system by connecting at least one or more ports to each other, and the system connection section has a mechanism for transferring data one-to-one between arbitrary ports (hereinafter referred to as unicast). And all ports from one port In a multiprocessor system having a mechanism for transferring data (hereinafter referred to as “broadcast”) and having a mechanism for simultaneously executing a plurality of unicasts having different transfer destination ports, the system connection unit is connected to each port. having a first means for identifying the units in either the data transfer by said unicast mechanism based on the type or / and the address of the data to be transferred in the information and data transfer obtained by the first means multi characterized in that it comprises a third means for holding the information for determining the second means and the unicast mechanism data when using the destination port to determine the data transfer by said broadcast mechanism Processor system. 2. The multiprocessor system according to claim 1, wherein the system connection unit further includes a mechanism for transferring data in a one-to-many manner (hereinafter referred to as multicast) from any port to a plurality of ports, and a transfer destination port. Information and data obtained by the first means for identifying a unit connected to each port of the system connection unit in a multiprocessor system having a mechanism for simultaneously executing a plurality of unicasts and multicasts having different multiprocessor system, comprising a fourth means for holding the information for determining the destination port of the data when using the multicast mechanism based on the type or / and the data transfer destination address of the transfer. In the first means is a multiprocessor system of the second term belonging to each unit, read the first means using the unicast mechanism to identify the unit being connected, then the based on the identification information, by using the unicast mechanism to set said third and fourth means, after setting the third and fourth means, the data transfer using the broadcast mechanism or the multicast mechanism A data transfer method characterized by starting. The multiprocessor system according to item 2, wherein the first means belongs to each unit , and each unit is assigned a broadcast read / write request address to a resource belonging to the unit. discriminates whether or not from, performs read / write requested the former case, in the latter case in a multiprocessor system having a mechanism to ignore the read / write request, first, the first using the broadcast mechanism reading means, to identify the unit being connected, then, based on the identification information, and setting the third and fourth means using the broadcast mechanism, the third and fourth means after setting, to initiate a data transfer using the unicast mechanism or the multicast mechanism Laid Data transfer method to be. 4. The multiprocessor system according to claim 2 , wherein each unit has the fourth means. 4. The multiprocessor system according to claim 2 , wherein the system connection unit has the fourth means. Wherein a second term multiprocessor system, said fourth means corresponds to 1 bit of information is one port for holding, the fourth port against the data transfer specified by the information held by the means A multiprocessor system having a multicast mechanism for performing Designated by the a second term multiprocessor system, the 1-bit information the fourth means is held corresponds to one group that summarizes the plurality of ports, information held by the said fourth means A multiprocessor system comprising a multicast mechanism for transferring data to all ports belonging to the group.

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